1 # Hitachi H8 testcase 'bset', 'bclr'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
13 # Instructions tested:
15 # bset xx:3, rd8 ; 7 0 ?xxx rd8
16 # bclr xx:3, rd8 ; 7 2 ?xxx rd8
17 # bset xx:3, @erd ; 7 d 0rd ???? 7 0 ?xxx ????
18 # bclr xx:3, @erd ; 7 d 0rd ???? 7 2 ?xxx ????
19 # bset xx:3, @abs16 ; 6 a 1 1??? aa:16 7 0 ?xxx ????
20 # bclr xx:3, @abs16 ; 6 a 1 1??? aa:16 7 2 ?xxx ????
21 # bset reg8, rd8 ; 6 0 rs8 rd8
22 # bclr reg8, rd8 ; 6 2 rs8 rd8
23 # bset reg8, @erd ; 7 d 0rd ???? 6 0 rs8 ????
24 # bclr reg8, @erd ; 7 d 0rd ???? 6 2 rs8 ????
25 # bset reg8, @abs32 ; 6 a 3 1??? aa:32 6 0 rs8 ????
26 # bclr reg8, @abs32 ; 6 a 3 1??? aa:32 6 2 rs8 ????
39 set_grs_a5a5 ; Fill all general regs with a fixed pattern
83 .if (sim_cpu == h8300)
84 test_h_gr16 0xa5ff, r1
86 test_h_gr32 0xa5a5a5ff er1
130 test_gr_a5a5 0 ; Make sure other general regs not disturbed
131 .if (sim_cpu == h8300)
132 test_h_gr16 0xa500 r1
134 test_h_gr32 0xa5a5a500 er1
145 set_grs_a5a5 ; Fill all general regs with a fixed pattern
197 .if (sim_cpu == h8300)
198 test_h_gr16 0xa5ff r2
200 test_h_gr32 0xa5a5a5ff er2
252 test_gr_a5a5 0 ; Make sure other general regs not disturbed
253 .if (sim_cpu == h8300)
254 test_h_gr16 byte_dst r1
255 test_h_gr16 0xa500 r2
257 test_h_gr32 byte_dst er1
258 test_h_gr32 0xa5a5a500 er2
266 .if (sim_cpu > h8300h)
268 set_grs_a5a5 ; Fill all general regs with a fixed pattern
272 bset #0, @byte_dst:16
278 bset #1, @byte_dst:16
284 bset #2, @byte_dst:16
290 bset #3, @byte_dst:16
296 bset #4, @byte_dst:16
302 bset #5, @byte_dst:16
308 bset #6, @byte_dst:16
314 bset #7, @byte_dst:16
319 .if (sim_cpu == h8300)
320 test_h_gr16 0xa5ff r2
322 test_h_gr32 0xa5a5a5ff er2
327 bclr #7, @byte_dst:16
333 bclr #6, @byte_dst:16
339 bclr #5, @byte_dst:16
345 bclr #4, @byte_dst:16
351 bclr #3, @byte_dst:16
357 bclr #2, @byte_dst:16
363 bclr #1, @byte_dst:16
369 bclr #0, @byte_dst:16
374 test_gr_a5a5 0 ; Make sure other general regs not disturbed
376 .if (sim_cpu == h8300)
377 test_h_gr16 0xa500 r2
379 test_h_gr32 0xa5a5a500 er2
390 set_grs_a5a5 ; Fill all general regs with a fixed pattern
442 .if (sim_cpu == h8300)
443 test_h_gr16 0x07ff, r1
445 test_h_gr32 0xa5a507ff er1
497 test_gr_a5a5 0 ; Make sure other general regs not disturbed
498 .if (sim_cpu == h8300)
499 test_h_gr16 0x0000 r1
501 test_h_gr32 0xa5a50000 er1
512 set_grs_a5a5 ; Fill all general regs with a fixed pattern
572 .if (sim_cpu == h8300)
573 test_h_gr16 0x07ff r2
575 test_h_gr32 0xa5a507ff er2
635 test_gr_a5a5 0 ; Make sure other general regs not disturbed
636 .if (sim_cpu == h8300)
637 test_h_gr16 byte_dst r1
638 test_h_gr16 0x0000 r2
640 test_h_gr32 byte_dst er1
641 test_h_gr32 0xa5a50000 er2
649 .if (sim_cpu > h8300h)
651 set_grs_a5a5 ; Fill all general regs with a fixed pattern
656 bset r2h, @byte_dst:32
663 bset r2h, @byte_dst:32
670 bset r2h, @byte_dst:32
677 bset r2h, @byte_dst:32
684 bset r2h, @byte_dst:32
691 bset r2h, @byte_dst:32
698 bset r2h, @byte_dst:32
705 bset r2h, @byte_dst:32
710 .if (sim_cpu == h8300)
711 test_h_gr16 0x07ff r2
713 test_h_gr32 0xa5a507ff er2
719 bclr r2h, @byte_dst:32
726 bclr r2h, @byte_dst:32
733 bclr r2h, @byte_dst:32
740 bclr r2h, @byte_dst:32
747 bclr r2h, @byte_dst:32
754 bclr r2h, @byte_dst:32
761 bclr r2h, @byte_dst:32
768 bclr r2h, @byte_dst:32
773 test_gr_a5a5 0 ; Make sure other general regs not disturbed
775 .if (sim_cpu == h8300)
776 test_h_gr16 0x0000 r2
778 test_h_gr32 0xa5a50000 er2
788 .if (sim_cpu == h8sx)
790 set_grs_a5a5 ; Fill all general regs with a fixed pattern
795 bset/eq #0, @byte_dst:16 ; Zero is clear, should have no effect.
801 orc #4, ccr ; Set zero flag
802 bset/eq #0, @byte_dst:16 ; Zero is set: operation should succeed.
815 bclr/eq #0, @byte_dst:32 ; Zero is clear, should have no effect.
821 orc #4, ccr ; Set zero flag
822 bclr/eq #0, @byte_dst:32 ; Zero is set: operation should succeed.
830 test_gr_a5a5 0 ; Make sure other general regs not disturbed
831 test_h_gr32 0xa5a5a500 er1
840 set_grs_a5a5 ; Fill all general regs with a fixed pattern
842 ;; bset/ne xx:3, aa:16
845 orc #4, ccr ; Set zero flag
846 bset/ne #0, @byte_dst:16 ; Zero is set; should have no effect.
855 bset/ne #0, @byte_dst:16 ; Zero is clear: operation should succeed.
863 orc #4, ccr ; Set zero flag
864 ;; bclr/ne xx:3, aa:16
865 bclr/ne #0, @byte_dst:32 ; Zero is set, should have no effect.
874 bclr/ne #0, @byte_dst:32 ; Zero is clear: operation should succeed.
879 test_gr_a5a5 0 ; Make sure other general regs not disturbed
880 test_h_gr32 0xa5a5a500 er1