sim/testsuite/sim/frv/tra.cgs

   1 # frv testcase for tra $GRi,$GRj
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global tra
   9 tra:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr7
  12         inc_gr_immed    2112,gr7                ; address of exception handler
  13         set_bctrlr_0_0  gr7
  14
  15         set_spr_immed   128,lcr
  16         set_gr_immed    0,gr7
  17         set_gr_immed    4,gr8
  18
  19         set_psr_et      1
  20         set_spr_addr    ok0,lr
  21         set_icc         0x0 0
  22         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  23 bad0:
  24         fail
  25 ok0:
  26         test_spr_addr   bad0,pcsr
  27         set_psr_et      1
  28         set_spr_addr    ok1,lr
  29         set_icc         0x1 0
  30         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  31         fail
  32 ok1:
  33         set_psr_et      1
  34         set_spr_addr    ok2,lr
  35         set_icc         0x2 0
  36         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  37         fail
  38 ok2:
  39         set_psr_et      1
  40         set_spr_addr    ok3,lr
  41         set_icc         0x3 0
  42         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  43         fail
  44 ok3:
  45         set_psr_et      1
  46         set_spr_addr    ok4,lr
  47         set_icc         0x4 0
  48         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  49         fail
  50 ok4:
  51         set_psr_et      1
  52         set_spr_addr    ok5,lr
  53         set_icc         0x5 0
  54         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  55         fail
  56 ok5:
  57         set_psr_et      1
  58         set_spr_addr    ok6,lr
  59         set_icc         0x6 0
  60         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  61         fail
  62 ok6:
  63         set_psr_et      1
  64         set_spr_addr    ok7,lr
  65         set_icc         0x7 0
  66         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  67         fail
  68 ok7:
  69         set_psr_et      1
  70         set_spr_addr    ok8,lr
  71         set_icc         0x8 0
  72         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  73         fail
  74 ok8:
  75         set_psr_et      1
  76         set_spr_addr    ok9,lr
  77         set_icc         0x9 0
  78         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  79         fail
  80 ok9:
  81         set_psr_et      1
  82         set_spr_addr    oka,lr
  83         set_icc         0xa 0
  84         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  85         fail
  86 oka:
  87         set_psr_et      1
  88         set_spr_addr    okb,lr
  89         set_icc         0xb 0
  90         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  91         fail
  92 okb:
  93         set_psr_et      1
  94         set_spr_addr    okc,lr
  95         set_icc         0xc 0
  96         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
  97         fail
  98 okc:
  99         set_psr_et      1
 100         set_spr_addr    okd,lr
 101         set_icc         0xd 0
 102         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
 103         fail
 104 okd:
 105         set_psr_et      1
 106         set_spr_addr    oke,lr
 107         set_icc         0xe 0
 108         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
 109         fail
 110 oke:
 111         set_psr_et      1
 112         set_spr_addr    okf,lr
 113         set_icc         0xf 0
 114         tra             gr7,gr8 ; should branch to tbr + (128 + 4)*16
 115         fail
 116 okf:
 117         pass