sim/testsuite/sim/frv/tgt.cgs

   1 # frv testcase for tgt $ICCi_2,$GRi,$GRj
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global tgt
   9 tgt:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr7
  12         inc_gr_immed    2112,gr7                ; address of exception handler
  13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
  14
  15         set_spr_immed   128,lcr
  16         set_gr_immed    0,gr7
  17         set_gr_immed    4,gr8
  18
  19         set_psr_et      1
  20         set_spr_addr    ok0,lr
  21         set_icc         0x0 0
  22         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  23         fail
  24 ok0:
  25         set_psr_et      1
  26         set_spr_addr    ok1,lr
  27         set_icc         0x1 0
  28         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  29         fail
  30 ok1:
  31         set_spr_addr    bad,lr
  32         set_icc         0x2 0
  33         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  34
  35         set_spr_addr    bad,lr
  36         set_icc         0x3 0
  37         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  38
  39         set_spr_addr    bad,lr
  40         set_icc         0x4 0
  41         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  42
  43         set_spr_addr    bad,lr
  44         set_icc         0x5 0
  45         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  46
  47         set_spr_addr    bad,lr
  48         set_icc         0x6 0
  49         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  50
  51         set_spr_addr    bad,lr
  52         set_icc         0x7 0
  53         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  54
  55         set_spr_addr    bad,lr
  56         set_icc         0x8 0
  57         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  58
  59         set_spr_addr    bad,lr
  60         set_icc         0x9 0
  61         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  62
  63         set_psr_et      1
  64         set_spr_addr    oka,lr
  65         set_icc         0xa 0
  66         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  67         fail
  68 oka:
  69         set_psr_et      1
  70         set_spr_addr    okb,lr
  71         set_icc         0xb 0
  72         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  73         fail
  74 okb:
  75         set_spr_addr    bad,lr
  76         set_icc         0xc 0
  77         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  78
  79         set_spr_addr    bad,lr
  80         set_icc         0xd 0
  81         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  82
  83         set_spr_addr    bad,lr
  84         set_icc         0xe 0
  85         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  86
  87         set_spr_addr    bad,lr
  88         set_icc         0xf 0
  89         tgt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  90
  91         pass
  92 bad:
  93         fail