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tizen 2.4 release
[external/binutils.git]
/
sim
/
testsuite
/
sim
/
frv
/
fcbugelr.cgs
1
# frv testcase for fcbugelr $FCCi,$ccond,$hint
2
# mach: all
3
4
.include "testutils.inc"
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start
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8
.global fcbugelr
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fcbugelr:
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; ccond is true
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set_spr_immed 128,lcr
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set_spr_addr bad,lr
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set_fcc 0x0 0
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fcbugelr fcc0,0,0
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set_spr_addr ok2,lr
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set_fcc 0x1 1
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fcbugelr fcc1,0,1
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fail
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ok2:
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set_spr_addr ok3,lr
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set_fcc 0x2 2
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fcbugelr fcc2,0,2
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fail
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ok3:
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set_spr_addr ok4,lr
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set_fcc 0x3 3
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fcbugelr fcc3,0,3
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fail
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ok4:
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set_spr_addr bad,lr
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set_fcc 0x4 0
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fcbugelr fcc0,0,0
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set_spr_addr ok6,lr
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set_fcc 0x5 1
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fcbugelr fcc1,0,1
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fail
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ok6:
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set_spr_addr ok7,lr
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set_fcc 0x6 2
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fcbugelr fcc2,0,2
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fail
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ok7:
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set_spr_addr ok8,lr
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set_fcc 0x7 3
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fcbugelr fcc3,0,3
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fail
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ok8:
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set_spr_addr ok9,lr
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set_fcc 0x8 0
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fcbugelr fcc0,0,0
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fail
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ok9:
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set_spr_addr oka,lr
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set_fcc 0x9 1
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fcbugelr fcc1,0,1
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fail
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oka:
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set_spr_addr okb,lr
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set_fcc 0xa 2
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fcbugelr fcc2,0,2
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fail
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okb:
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set_spr_addr okc,lr
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set_fcc 0xb 3
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fcbugelr fcc3,0,3
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fail
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okc:
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set_spr_addr okd,lr
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set_fcc 0xc 0
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fcbugelr fcc0,0,0
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fail
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okd:
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set_spr_addr oke,lr
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set_fcc 0xd 1
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fcbugelr fcc1,0,1
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fail
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oke:
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set_spr_addr okf,lr
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set_fcc 0xe 2
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fcbugelr fcc2,0,2
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fail
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okf:
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set_spr_addr okg,lr
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set_fcc 0xf 3
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fcbugelr fcc3,0,3
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fail
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okg:
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; ccond is true
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_fcc 0x0 0
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fcbugelr fcc0,1,0
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set_spr_immed 1,lcr
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set_spr_addr oki,lr
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set_fcc 0x1 1
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fcbugelr fcc1,1,1
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fail
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oki:
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set_spr_immed 1,lcr
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set_spr_addr okj,lr
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set_fcc 0x2 2
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fcbugelr fcc2,1,2
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fail
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okj:
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set_spr_immed 1,lcr
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set_spr_addr okk,lr
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set_fcc 0x3 3
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fcbugelr fcc3,1,3
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fail
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okk:
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_fcc 0x4 0
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fcbugelr fcc0,1,0
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set_spr_immed 1,lcr
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set_spr_addr okm,lr
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set_fcc 0x5 1
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fcbugelr fcc1,1,1
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fail
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okm:
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set_spr_immed 1,lcr
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set_spr_addr okn,lr
128
set_fcc 0x6 2
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fcbugelr fcc2,1,2
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fail
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okn:
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set_spr_immed 1,lcr
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set_spr_addr oko,lr
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set_fcc 0x7 3
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fcbugelr fcc3,1,3
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fail
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oko:
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set_spr_immed 1,lcr
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set_spr_addr okp,lr
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set_fcc 0x8 0
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fcbugelr fcc0,1,0
142
fail
143
okp:
144
set_spr_immed 1,lcr
145
set_spr_addr okq,lr
146
set_fcc 0x9 1
147
fcbugelr fcc1,1,1
148
fail
149
okq:
150
set_spr_immed 1,lcr
151
set_spr_addr okr,lr
152
set_fcc 0xa 2
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fcbugelr fcc2,1,2
154
fail
155
okr:
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set_spr_immed 1,lcr
157
set_spr_addr oks,lr
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set_fcc 0xb 3
159
fcbugelr fcc3,1,3
160
fail
161
oks:
162
set_spr_immed 1,lcr
163
set_spr_addr okt,lr
164
set_fcc 0xc 0
165
fcbugelr fcc0,1,0
166
fail
167
okt:
168
set_spr_immed 1,lcr
169
set_spr_addr oku,lr
170
set_fcc 0xd 1
171
fcbugelr fcc1,1,1
172
fail
173
oku:
174
set_spr_immed 1,lcr
175
set_spr_addr okv,lr
176
set_fcc 0xe 2
177
fcbugelr fcc2,1,2
178
fail
179
okv:
180
set_spr_immed 1,lcr
181
set_spr_addr okw,lr
182
set_fcc 0xf 3
183
fcbugelr fcc3,1,3
184
fail
185
okw:
186
; ccond is false
187
set_spr_immed 128,lcr
188
189
set_fcc 0x0 0
190
fcbugelr fcc0,1,0
191
set_fcc 0x1 1
192
fcbugelr fcc1,1,1
193
set_fcc 0x2 2
194
fcbugelr fcc2,1,2
195
set_fcc 0x3 3
196
fcbugelr fcc3,1,3
197
set_fcc 0x4 0
198
fcbugelr fcc0,1,0
199
set_fcc 0x5 1
200
fcbugelr fcc1,1,1
201
set_fcc 0x6 2
202
fcbugelr fcc2,1,2
203
set_fcc 0x7 3
204
fcbugelr fcc3,1,3
205
set_fcc 0x8 0
206
fcbugelr fcc0,1,0
207
set_fcc 0x9 1
208
fcbugelr fcc1,1,1
209
set_fcc 0xa 2
210
fcbugelr fcc2,1,2
211
set_fcc 0xb 3
212
fcbugelr fcc3,1,3
213
set_fcc 0xc 0
214
fcbugelr fcc0,1,0
215
set_fcc 0xd 1
216
fcbugelr fcc1,1,1
217
set_fcc 0xe 2
218
fcbugelr fcc2,1,2
219
set_fcc 0xf 3
220
fcbugelr fcc3,1,3
221
222
; ccond is false
223
set_spr_immed 1,lcr
224
set_fcc 0x0 0
225
fcbugelr fcc0,0,0
226
set_spr_immed 1,lcr
227
set_fcc 0x1 1
228
fcbugelr fcc1,0,1
229
set_spr_immed 1,lcr
230
set_fcc 0x2 2
231
fcbugelr fcc2,0,2
232
set_spr_immed 1,lcr
233
set_fcc 0x3 3
234
fcbugelr fcc3,0,3
235
set_spr_immed 1,lcr
236
set_fcc 0x4 0
237
fcbugelr fcc0,0,0
238
set_spr_immed 1,lcr
239
set_fcc 0x5 1
240
fcbugelr fcc1,0,1
241
set_spr_immed 1,lcr
242
set_fcc 0x6 2
243
fcbugelr fcc2,0,2
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set_spr_immed 1,lcr
245
set_fcc 0x7 3
246
fcbugelr fcc3,0,3
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set_spr_immed 1,lcr
248
set_fcc 0x8 0
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fcbugelr fcc0,0,0
250
set_spr_immed 1,lcr
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set_fcc 0x9 1
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fcbugelr fcc1,0,1
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set_spr_immed 1,lcr
254
set_fcc 0xa 2
255
fcbugelr fcc2,0,2
256
set_spr_immed 1,lcr
257
set_fcc 0xb 3
258
fcbugelr fcc3,0,3
259
set_spr_immed 1,lcr
260
set_fcc 0xc 0
261
fcbugelr fcc0,0,0
262
set_spr_immed 1,lcr
263
set_fcc 0xd 1
264
fcbugelr fcc1,0,1
265
set_spr_immed 1,lcr
266
set_fcc 0xe 2
267
fcbugelr fcc2,0,2
268
set_spr_immed 1,lcr
269
set_fcc 0xf 3
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fcbugelr fcc3,0,3
271
272
pass
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bad:
274
fail