tizen 2.4 release
[external/binutils.git] / sim / testsuite / sim / frv / commitgr.cgs
1 # frv testcase for commitgr $GRk
2 # mach: frv
3
4         .include "testutils.inc"
5
6         start
7
8         .global commitgr
9 commitgr:
10         and_spr_immed   -4081,tbr               ; clear tbr.tt
11         set_gr_spr      tbr,gr17
12         inc_gr_immed    0x190,gr17              ; address of exception handler
13         set_bctrlr_0_0  gr17
14         set_spr_immed   128,lcr
15         set_psr_et      1
16         set_gr_immed    0,gr15
17
18         nldi            @(sp,0),gr20    ; Activate gr20 with nesr.fr==0
19         nldfi           @(sp,0),fr20    ; Activate fr20 with nesr.fr==1
20         nldi            @(sp,0),gr52    ; Activate gr52 with nesr.fr==0
21         set_spr_immed   0x00000000,gner1
22         set_spr_immed   0x00000000,gner0
23         set_spr_addr    bad,lr
24         commitgr        gr20            ; should only clear ne flags
25         test_gr_immed   0,gr15
26         test_spr_immed  0x00000000,gner1
27         test_spr_immed  0x00000000,gner0
28         test_spr_immed  0x94800001,nesr0
29         test_spr_gr     neear0,sp
30         test_spr_immed  0xd4800401,nesr1
31         test_spr_gr     neear1,sp
32         test_spr_immed  0xb4800801,nesr2
33         test_spr_gr     neear2,sp
34
35         or_spr_immed    0x00100000,gner1
36         or_spr_immed    0x00200000,gner1
37         or_spr_immed    0x00100000,gner0
38         set_spr_addr    ok,lr
39         set_gr_addr     com1,gr16
40 com1:   commitgr        gr20
41         test_gr_immed   1,gr15
42
43         pass
44
45 ok:     test_spr_immed  0x1,esfr1               ; esr0 is active
46         test_spr_gr     epcr0,gr16
47         test_spr_bits   0x0001,0,0x1,esr0       ; esr0 is valid
48         test_spr_bits   0x003e,1,0x14,esr0      ; esr0.ec is set
49         test_spr_bits   0x0800,11,0x0,esr0      ; esr0.eav is clear
50         test_spr_bits   0x01000,12,0x0,esr0     ; esr0.edv is clear
51         test_spr_immed  0x00200000,gner1
52         test_spr_immed  0x00100000,gner0
53         test_spr_immed  0,nesr0
54         test_spr_immed  0,neear0
55         test_spr_immed  0xd4800401,nesr1
56         test_spr_gr     neear1,sp
57         test_spr_immed  0xb4800801,nesr2
58         test_spr_gr     neear2,sp
59         inc_gr_immed    1,gr15
60         rett            0
61
62 bad:    fail