2 #sim(crisv10): --hw-device "/rv/trace? true"
3 #sim(crisv32): --hw-device "/rv/trace? true"
5 #output: /rv: REG R 0xd0000032\n
6 #output: /rv: := 0xabcdef01\n
7 #output: /rv: IRQ 0x4\n
8 #output: /rv: REG R 0xd0000036\n
9 #output: /rv: := 0x76543210\n
10 #output: /rv: REG R 0xd0000030\n
11 #output: /rv: IRQ 0x0\n
12 #output: /rv: IRQ 0x8\n
13 #output: /rv: := 0xeeff4455\n
14 #output: /rv: REG R 0xd0000034\n
15 #output: /rv: := 0xdd001122\n
16 #output: /rv: REG R 0xd0000038\n
17 #output: /rv: := 0xaaeeff44\n
18 #output: /rv: REG R 0xd000003c\n
19 #output: /rv: := 0xff445511\n
22 # Test two successive ints; that flags are disabled when an interrupt
23 # is taken, and then automatically (or by register restore) enabled at
39 .include "testutils.inc"
41 test_h_mem 0xabcdef01 0xd0000032
44 .if ..asm.arch.cris.v32
53 ; Here after the first interrupt, or perhaps the second interrupt is
54 ; taken directly; leave it optional. Anyway, the second interrupt
55 ; should be taken no later than this branch.
62 .if ..asm.arch.cris.v32
63 ; Nothing needed to save flags - "shift" should happen, and back at rfe.
65 ; The missing sim support for interrupt-excluding instructions is matched
66 ; by the flaw that sim doesn't service interrupts in straight code.
67 ; So, we can use a sequence that would work on actual hardware.
72 test_h_mem 0x76543210 0xd0000036
73 test_h_mem 0xeeff4455 0xd0000030
74 test_h_mem 0xdd001122 0xd0000034
77 .if ..asm.arch.cris.v32
90 test_h_mem 0xaaeeff44 0xd0000038
91 test_h_mem 0xff445511 0xd000003c
97 singlevec irqvec1,0x33,irq0x33
99 singlevec irqvec2,0x34,irq0x34