tizen 2.4 release
[external/binutils.git] / sim / testsuite / sim / bfin / saatest.s
1 # mach: bfin
2
3 .include "testutils.inc"
4         start
5
6
7         I0 = 0 (X);
8         I1 = 0 (X);
9         A0 = A1 = 0;
10         init_r_regs 0;
11         ASTAT = R0;
12
13 // This section of code will test the SAA instructions and sum of accumulators;
14
15         loadsym I0, tstvecI;
16
17         R0 = [ I0 ++ ];
18         R2 = [ I0 ++ ];
19
20 // +++++++++++++++   TG11.001   +++++++++++++ //
21 //                                            //
22 //                     HH   HL   LH   LL      //
23 //       Input: r0 ==> 15   15   15   15      //
24 //              r1 ==>  0    0    0    0      //
25 //                                            //
26 //       Output:r2 ==> 0    0    0   30       //
27 //              r3 ==> 0    0    0   30       //
28 // ++++++++++++++++++++++++++++++++++++++++++ //
29
30         SAA ( R1:0 , R3:2 );
31         R6 = A1.L + A1.H, R7 = A0.L + A0.H;
32         DBGA ( R6.L , 0x001e );
33         DBGA ( R6.H , 0x0000 );
34         DBGA ( R7.L , 0x001e );
35         DBGA ( R7.H , 0x0000 );
36
37         A1 = A0 = 0;
38
39 // +++++++++++++++   TG11.002   +++++++++++++ //
40 //                                            //
41 //                     HH   HL   LH   LL      //
42 //       Input: r0 ==> 15   15   15   15      //
43 //              r1 ==>  0    0    0    0      //
44 //                                            //
45 //       Output:r2 ==> 0    0    0   30       //
46 //              r3 ==> 0    0    0   30       //
47 // ++++++++++++++++++++++++++++++++++++++++++ //
48
49         SAA ( R1:0 , R3:2 );
50         R6 = A1.L + A1.H, R7 = A0.L + A0.H;
51         DBGA ( R6.L , 0x001e );
52         DBGA ( R6.H , 0x0000 );
53         DBGA ( R7.L , 0x001e );
54         DBGA ( R7.H , 0x0000 );
55
56         A1 = A0 = 0;
57
58 // +++++++++++++++   TG11.003   +++++++++++++ //
59 //                                            //
60 //                     HH   HL   LH   LL      //
61 //       Input: r0 ==> 240  240  240  240     //
62 //              r1 ==>  0    0    0    0      //
63 //                                            //
64 //       Output:r2 ==> 0    480               //
65 //              r3 ==> 0    480               //
66 // ++++++++++++++++++++++++++++++++++++++++++ //
67
68         R0 = [ I0 ++ ];
69         R2 = [ I0 ++ ];
70
71         SAA ( R3:2 , R1:0 );
72         R6 = A1.L + A1.H, R7 = A0.L + A0.H;
73         DBGA ( R6.L , 0x01e0 );
74         DBGA ( R6.H , 0x0000 );
75         DBGA ( R7.L , 0x01e0 );
76         DBGA ( R7.H , 0x0000 );
77
78         A1 = A0 = 0;
79
80 // +++++++++++++++   TG11.004   +++++++++++++ //
81 //                                            //
82 //                     HH   HL   LH   LL      //
83 //       Input: r0 ==> 240  240  240  240     //
84 //              r1 ==>  0    0    0    0      //
85 //                                            //
86 //       Output:r2 ==> 0    480               //
87 //              r3 ==> 0    480               //
88 // ++++++++++++++++++++++++++++++++++++++++++ //
89
90         SAA ( R1:0 , R3:2 );
91         R6 = A1.L + A1.H, R7 = A0.L + A0.H;
92         DBGA ( R6.L , 0x01e0 );
93         DBGA ( R6.H , 0x0000 );
94         DBGA ( R7.L , 0x01e0 );
95         DBGA ( R7.H , 0x0000 );
96
97         A1 = A0 = 0;
98 // +++++++++++++++   TG11.005   +++++++++++++ //
99 //                                            //
100 //                     HH   HL   LH   LL      //
101 //       Input: r0 ==>  0    0    0    0      //
102 //              r1 ==>  0    0    0    0      //
103 //                                            //
104 //       Output:r2 ==> 0    0                 //
105 //              r3 ==> 0    0                 //
106 // ++++++++++++++++++++++++++++++++++++++++++ //
107
108         R0 = [ I0 ++ ];
109         R2 = [ I0 ++ ];
110
111         SAA ( R1:0 , R3:2 );
112         R6 = A1.L + A1.H, R7 = A0.L + A0.H;
113         DBGA ( R6.L , 0x0000 );
114         DBGA ( R6.H , 0x0000 );
115         DBGA ( R7.L , 0x0000 );
116         DBGA ( R7.H , 0x0000 );
117
118 // +++++++++++++++   TG11.006   +++++++++++++ //
119 //                                            //
120 //                     HH   HL   LH   LL      //
121 //       Input: r0 ==> 255  255  255  255     //
122 //              r1 ==> 255  255  255  255     //
123 //                                            //
124 //       Output:r2 ==> 0    0                 //
125 //              r3 ==> 0    0                 //
126 // ++++++++++++++++++++++++++++++++++++++++++ //
127
128         SAA ( R3:2 , R1:0 );
129         R6 = A1.L + A1.H, R7 = A0.L + A0.H;
130         DBGA ( R6.L , 0x0000 );
131         DBGA ( R6.H , 0x0000 );
132         DBGA ( R7.L , 0x0000 );
133         DBGA ( R7.H , 0x0000 );
134
135         A1 = A0 = 0;
136
137 // +++++++++++++++   TG12.001   +++++++++++++ //
138 //                                            //
139 //                     HH   HL   LH   LL      //
140 //       Input: r0 ==> 255  255  255  255     //
141 //              r1 ==> 255  255  255  255     //
142 //                                            //
143 //       Output:r2 ==> 0    0                 //
144 //              r3 ==> 0    0                 //
145 // ++++++++++++++++++++++++++++++++++++++++++ //
146
147         loadsym I0, tstvecK;
148         B0 = I0;
149         L0.L = 4;
150         loadsym I1, tstvecJ;
151         B1 = I1;
152         L1.L = 4;
153
154         P0 = 64 (X);
155         R0 = [ I0 ++ ];
156         R2 = [ I1 ++ ];
157         LSETUP ( l$1 , l$1 ) LC0 = P0;
158 l$1:
159         SAA ( R1:0 , R3:2 ) || R0 = [ I0 ++ ] || R1 = [ I1 ++ ];
160
161         R2 = A1.L + A1.H, R3 = A0.L + A0.H;
162         R7 = R2 + R3 (NS);
163         DBGA ( R7.L , 0xff00 );
164         DBGA ( R7.H , 0x0000 );
165
166         R5.L = 0xfffa;
167         A1 = R5;
168         R5.H = 0xfff0;
169         A0 = R5;
170
171         loadsym I0, tstvecI;
172         R0 = [ I0 ++ ];
173         R2 = [ I0 ++ ];
174         SAA ( R1:0 , R3:2 );
175         R6 = A1.L + A1.H, R7 = A0.L + A0.H;
176         DBGA ( R6.L , 0x000e );
177         DBGA ( R6.H , 0x0000 );
178         DBGA ( R7.L , 0xfffe );
179         DBGA ( R7.H , 0xffff );
180
181         pass
182
183         .data
184 tstvecI:
185         .dw 0x0000
186         .dw 0x0000
187         .dw 0x0f0f
188         .dw 0x0f0f
189         .dw 0x0000
190         .dw 0x0000
191         .dw 0xf0f0
192         .dw 0xf0f0
193         .dw 0x0000
194         .dw 0x0000
195         .dw 0x0000
196         .dw 0x0000
197         .dw 0xffff
198         .dw 0xffff
199         .dw 0xffff
200         .dw 0xffff
201
202         .data
203 tstvecJ:
204         .dw 0xffff
205         .dw 0xffff
206         .dw 0xffff
207         .dw 0xffff
208         .dw 0xffff
209         .dw 0xffff
210         .dw 0xffff
211         .dw 0xffff
212
213         .data
214 tstvecK:
215         .dw 0x0000
216         .dw 0x0000
217         .dw 0x0000
218         .dw 0x0000
219         .dw 0x0000
220         .dw 0x0000
221         .dw 0x0000
222         .dw 0x0000