tizen 2.4 release
[external/binutils.git] / sim / testsuite / sim / bfin / c_loopsetup_preg_lc1.s
1 //Original:/testcases/core/c_loopsetup_preg_lc1/c_loopsetup_preg_lc1.dsp
2 // Spec Reference: loopsetup preg lc1
3 # mach: bfin
4
5 .include "testutils.inc"
6         start
7
8
9 INIT_R_REGS 0;
10
11 ASTAT = r0;
12
13 P1 = 12;
14 P2 = 14;
15 P3 = 16;
16 P4 = 18;
17 P5 = 20;
18 SP = 22;
19 FP = 24;
20
21 R0 = 0x05;
22 R1 = 0x10;
23 R2 = 0x20;
24 R3 = 0x30;
25 R4 = 0x40 (X);
26 R5 = 0x50 (X);
27 R6 = 0x60 (X);
28 R7 = 0x70 (X);
29 LSETUP ( start11 , end11 ) LC1 = P1;
30 start11: R0 += 1;
31  R1 += -1;
32 end11: R2 += 1;
33  R3 += 1;
34 LSETUP ( start12 , end12 ) LC1 = P2;
35 start12: R4 += 1;
36 end12: R5 += -1;
37  R3 += 1;
38 LSETUP ( start13 , end13 ) LC1 = P3;
39 start13: R6 += 1;
40 end13: R7 += -1;
41  R3 += 1;
42 CHECKREG r0, 0x00000011;
43 CHECKREG r1, 0x00000004;
44 CHECKREG r2, 0x0000002C;
45 CHECKREG r3, 0x00000033;
46 CHECKREG r4, 0x0000004E;
47 CHECKREG r5, 0x00000042;
48 CHECKREG r6, 0x00000070;
49 CHECKREG r7, 0x00000060;
50
51 R0 = 0x05;
52 R1 = 0x10;
53 R2 = 0x20;
54 R3 = 0x30;
55 R4 = 0x40 (X);
56 R5 = 0x50 (X);
57 R6 = 0x60 (X);
58 R7 = 0x70 (X);
59 LSETUP ( start14 , end14 ) LC1 = P4;
60 start14: R0 += 1;
61  R1 += -1;
62 end14: R2 += 1;
63  R3 += 1;
64 LSETUP ( start15 , end15 ) LC1 = P5;
65 start15: R4 += 1;
66 end15: R5 += -1;
67  R3 += 1;
68 LSETUP ( start16 , end16 ) LC1 = SP;
69 start16: R6 += 1;
70 end16: R7 += -1;
71  R3 += 1;
72 CHECKREG r0, 0x00000017;
73 CHECKREG r1, 0xFFFFFFFE;
74 CHECKREG r2, 0x00000032;
75 CHECKREG r3, 0x00000033;
76 CHECKREG r4, 0x00000054;
77 CHECKREG r5, 0x0000003c;
78 CHECKREG r6, 0x00000076;
79 CHECKREG r7, 0x0000005A;
80 LSETUP ( start17 , end17 ) LC1 = FP;
81 start17: R4 += 1;
82 end17: R5 += -1;
83  R3 += 1;
84 CHECKREG r0, 0x00000017;
85 CHECKREG r1, 0xFFFFFFFE;
86 CHECKREG r2, 0x00000032;
87 CHECKREG r3, 0x00000034;
88 CHECKREG r4, 0x0000006c;
89 CHECKREG r5, 0x00000024;
90 CHECKREG r6, 0x00000076;
91 CHECKREG r7, 0x0000005A;
92
93 pass