1 //Original:testcases/core/c_ldstpmod_st_dr_hi/c_ldstpmod_st_dr_hi.dsp
2 // Spec Reference: c_ldstpmod store dreg hi
5 .include "testutils.inc"
26 I1 = P3; P3 = I0; I3 = SP; SP = I2;
27 loadsym p1, DATA_ADDR_1, 0x00;
28 loadsym p2, DATA_ADDR_2, 0x02;
29 loadsym i1, DATA_ADDR_3, 0x04;
30 loadsym p4, DATA_ADDR_4, 0x06;
31 loadsym p5, DATA_ADDR_5, 0x08;
32 loadsym fp, DATA_ADDR_6, 0x0a;
33 loadsym i3, DATA_ADDR_7, 0x0c;
49 CHECKREG r0, 0xC0095000;
50 CHECKREG r1, 0x600F6001;
51 CHECKREG r2, 0xB00A7002;
52 CHECKREG r3, 0xA00B8003;
53 CHECKREG r4, 0x900C9004;
54 CHECKREG r5, 0x800DA005;
55 CHECKREG r6, 0x700EB006;
66 I1 = P3; P3 = I0; I3 = SP; SP = I2;
67 loadsym p1, DATA_ADDR_1, 0x0c;
68 loadsym p2, DATA_ADDR_2, 0x0a;
69 loadsym i1, DATA_ADDR_3, 0x08;
70 loadsym p4, DATA_ADDR_4, 0x06;
71 loadsym p5, DATA_ADDR_5, 0x04;
72 loadsym fp, DATA_ADDR_6, 0x02;
73 loadsym i3, DATA_ADDR_7, 0x00;
89 CHECKREG r0, 0x105F204E;
90 CHECKREG r1, 0x204E3003;
91 CHECKREG r2, 0x3003402C;
92 CHECKREG r3, 0x402C501B;
93 CHECKREG r4, 0x501B600A;
94 CHECKREG r5, 0x600A7019;
95 CHECKREG r6, 0x7019D028;
100 imm32 r2, 0x30bd70b2;
101 imm32 r3, 0x40bc80b3;
102 imm32 r4, 0x55bb90b4;
103 imm32 r5, 0x12345675;
104 imm32 r6, 0x70b9b0b6;
105 imm32 r7, 0x80b8c0b7;
106 I1 = P3; P3 = I0; I3 = SP; SP = I2;
107 loadsym p1, DATA_ADDR_1, 0x10;
108 loadsym p2, DATA_ADDR_2, 0x02;
109 loadsym i1, DATA_ADDR_3, 0x00;
110 loadsym p4, DATA_ADDR_4, 0x08;
111 loadsym p5, DATA_ADDR_5, 0x04;
112 loadsym fp, DATA_ADDR_6, 0x06;
113 loadsym i3, DATA_ADDR_7, 0x02;
129 CHECKREG r0, 0x30BD50B0;
130 CHECKREG r1, 0x20BE60B1;
131 CHECKREG r2, 0x10BF70B2;
132 CHECKREG r3, 0x80B880B3;
133 CHECKREG r4, 0x70B990B4;
134 CHECKREG r5, 0x12345675;
135 CHECKREG r6, 0x40BCB0B6;
140 // Pre-load memory with known data
141 // More data is defined than will actually be used