1 //Original:testcases/core/c_ldst_ld_d_p_mm_xh/c_ldst_ld_d_p_mm_xh.dsp
2 // Spec Reference: c_ldst ld d [p++/--] h b xh xb
5 .include "testutils.inc"
18 I1 = P3; P3 = I0; I3 = SP; SP = I2;
19 loadsym p5, DATA_ADDR_1, 0x08;
20 loadsym p1, DATA_ADDR_2, 0x08;
21 loadsym p2, DATA_ADDR_3, 0x08;
22 loadsym i1, DATA_ADDR_4, 0x08;
23 loadsym p4, DATA_ADDR_5, 0x08;
24 loadsym fp, DATA_ADDR_6, 0x08;
25 loadsym i3, DATA_ADDR_7, 0x08;
35 CHECKREG r0, 0xFFFF8A8B;
36 CHECKREG r1, 0x00000A0B;
37 CHECKREG r2, 0xFFFF8A8B;
38 CHECKREG r3, 0x00000000;
39 CHECKREG r4, 0x00000A0B;
40 CHECKREG r5, 0x00002A2B;
41 CHECKREG r6, 0x00004A4B;
42 CHECKREG r7, 0x00006A6B;
51 CHECKREG r0, 0x00006465;
52 CHECKREG r1, 0xFFFF8485;
53 CHECKREG r2, 0x00000405;
54 CHECKREG r3, 0xFFFF8485;
55 CHECKREG r4, 0x00000A0B;
56 CHECKREG r5, 0x00000405;
57 CHECKREG r6, 0x00002425;
58 CHECKREG r7, 0x00004445;
67 CHECKREG r0, 0x00004647;
68 CHECKREG r1, 0x00006667;
69 CHECKREG r2, 0xFFFF8687;
70 CHECKREG r3, 0x00000607;
71 CHECKREG r4, 0xFFFF8687;
72 CHECKREG r5, 0x00000405;
73 CHECKREG r6, 0x00000607;
74 CHECKREG r7, 0x00002627;
83 CHECKREG r0, 0x00002021;
84 CHECKREG r1, 0x00004041;
85 CHECKREG r2, 0x00006061;
86 CHECKREG r3, 0xFFFF8081;
87 CHECKREG r4, 0x00000001;
88 CHECKREG r5, 0xFFFF8081;
89 CHECKREG r6, 0x00000607;
90 CHECKREG r7, 0x00000001;
95 // Pre-load memory with known data
96 // More data is defined than will actually be used