sim/testsuite/sim/bfin/c_ldimmhalf_l_ibml.s

   1 //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_ibml/c_ldimmhalf_l_ibml.dsp
   2 // Spec Reference: ldimmhalf l ibml
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         INIT_I_REGS -1;
   9         INIT_L_REGS -1;
  10         INIT_M_REGS -1;
  11         INIT_B_REGS -1;
  12
  13         I0.L = 0x2001;
  14         I1.L = 0x2003;
  15         I2.L = 0x2005;
  16         I3.L = 0x2007;
  17         L0.L = 0x2009;
  18         L1.L = 0x200b;
  19         L2.L = 0x200d;
  20         L3.L = 0x200f;
  21
  22         R0 = I0;
  23         R1 = I1;
  24         R2 = I2;
  25         R3 = I3;
  26         R4 = L0;
  27         R5 = L1;
  28         R6 = L2;
  29         R7 = L3;
  30         CHECKREG r0, 0xffff2001;
  31         CHECKREG r1, 0xffff2003;
  32         CHECKREG r2, 0xffff2005;
  33         CHECKREG r3, 0xffff2007;
  34         CHECKREG r4, 0xffff2009;
  35         CHECKREG r5, 0xffff200b;
  36         CHECKREG r6, 0xffff200d;
  37         CHECKREG r7, 0xffff200f;
  38
  39         I0.L = 0x0111;
  40         I1.L = 0x1111;
  41         I2.L = 0x2222;
  42         I3.L = 0x3333;
  43         L0.L = 0x4444;
  44         L1.L = 0x5555;
  45         L2.L = 0x6666;
  46         L3.L = 0x7777;
  47         R0 = I0;
  48         R1 = I1;
  49         R2 = I2;
  50         R3 = I3;
  51         R4 = L0;
  52         R5 = L1;
  53         R6 = L2;
  54         R7 = L3;
  55         CHECKREG r0, 0xffff0111;
  56         CHECKREG r1, 0xffff1111;
  57         CHECKREG r2, 0xffff2222;
  58         CHECKREG r3, 0xffff3333;
  59         CHECKREG r4, 0xffff4444;
  60         CHECKREG r5, 0xffff5555;
  61         CHECKREG r6, 0xffff6666;
  62         CHECKREG r7, 0xffff7777;
  63
  64         I0.L = 0x8888;
  65         I1.L = 0x9aaa;
  66         I2.L = 0xabbb;
  67         I3.L = 0xbccc;
  68         L0.L = 0xcddd;
  69         L1.L = 0xdeee;
  70         L2.L = 0xefff;
  71         L3.L = 0xf111;
  72         R0 = I0;
  73         R1 = I1;
  74         R2 = I2;
  75         R3 = I3;
  76         R4 = L0;
  77         R5 = L1;
  78         R6 = L2;
  79         R7 = L3;
  80         CHECKREG r0, 0xffff8888;
  81         CHECKREG r1, 0xffff9aaa;
  82         CHECKREG r2, 0xffffabbb;
  83         CHECKREG r3, 0xffffbccc;
  84         CHECKREG r4, 0xffffcddd;
  85         CHECKREG r5, 0xffffdeee;
  86         CHECKREG r6, 0xffffefff;
  87         CHECKREG r7, 0xfffff111;
  88
  89         B0.L = 0x3001;
  90         B1.L = 0x3003;
  91         B2.L = 0x3005;
  92         B3.L = 0x3007;
  93         M0.L = 0x3009;
  94         M1.L = 0x300b;
  95         M2.L = 0x300d;
  96         M3.L = 0x300f;
  97
  98         R0 = B0;
  99         R1 = B1;
 100         R2 = B2;
 101         R3 = B3;
 102         R4 = M0;
 103         R5 = M1;
 104         R6 = M2;
 105         R7 = M3;
 106         CHECKREG r0, 0xffff3001;
 107         CHECKREG r1, 0xffff3003;
 108         CHECKREG r2, 0xffff3005;
 109         CHECKREG r3, 0xffff3007;
 110         CHECKREG r4, 0xffff3009;
 111         CHECKREG r5, 0xffff300B;
 112         CHECKREG r6, 0xffff300d;
 113         CHECKREG r7, 0xffff300f;
 114
 115         B0.L = 0x0110;
 116         B1.L = 0x1110;
 117         B2.L = 0x2220;
 118         B3.L = 0x3330;
 119         M0.L = 0x4440;
 120         M1.L = 0x5550;
 121         M2.L = 0x6660;
 122         M3.L = 0x7770;
 123         R0 = B0;
 124         R1 = B1;
 125         R2 = B2;
 126         R3 = B3;
 127         R4 = M0;
 128         R5 = M1;
 129         R6 = M2;
 130         R7 = M3;
 131         CHECKREG r0, 0xffff0110;
 132         CHECKREG r1, 0xffff1110;
 133         CHECKREG r2, 0xffff2220;
 134         CHECKREG r3, 0xffff3330;
 135         CHECKREG r4, 0xffff4440;
 136         CHECKREG r5, 0xffff5550;
 137         CHECKREG r6, 0xffff6660;
 138         CHECKREG r7, 0xffff7770;
 139
 140         B0.L = 0xf880;
 141         B1.L = 0xfaa0;
 142         B2.L = 0xfbb0;
 143         B3.L = 0xfcc0;
 144         M0.L = 0xfdd0;
 145         M1.L = 0xfee0;
 146         M2.L = 0xfff0;
 147         M3.L = 0xf110;
 148         R0 = B0;
 149         R1 = B1;
 150         R2 = B2;
 151         R3 = B3;
 152         R4 = M0;
 153         R5 = M1;
 154         R6 = M2;
 155         R7 = M3;
 156         CHECKREG r0, 0xfffff880;
 157         CHECKREG r1, 0xfffffaa0;
 158         CHECKREG r2, 0xfffffbb0;
 159         CHECKREG r3, 0xfffffcc0;
 160         CHECKREG r4, 0xfffffdd0;
 161         CHECKREG r5, 0xfffffee0;
 162         CHECKREG r6, 0xfffffff0;
 163         CHECKREG r7, 0xfffff110;
 164
 165         pass