1 //Original:/testcases/core/c_dspldst_ld_drhi_ipp/c_dspldst_ld_drhi_ipp.dsp
2 // Spec Reference: c_dspldst ld_drhi_i++/--
5 .include "testutils.inc"
17 loadsym I0, DATA_ADDR_3;
18 loadsym I1, DATA_ADDR_4;
19 loadsym I2, DATA_ADDR_5;
20 loadsym I3, DATA_ADDR_6;
22 // Load Upper half of Dregs
31 CHECKREG r0, 0x02030000;
32 CHECKREG r1, 0x22230000;
33 CHECKREG r2, 0x42430000;
34 CHECKREG r3, 0x62630000;
35 CHECKREG r4, 0x00010000;
36 CHECKREG r5, 0x20210000;
37 CHECKREG r6, 0x40410000;
38 CHECKREG r7, 0x60610000;
48 CHECKREG r0, 0x64650000;
49 CHECKREG r1, 0x06070000;
50 CHECKREG r2, 0x26270000;
51 CHECKREG r3, 0x46470000;
52 CHECKREG r4, 0x66670000;
53 CHECKREG r5, 0x04050000;
54 CHECKREG r6, 0x24250000;
55 CHECKREG r7, 0x44450000;
65 CHECKREG r0, 0x48490000;
66 CHECKREG r1, 0x68690000;
67 CHECKREG r2, 0x0A0B0000;
68 CHECKREG r3, 0x2A2B0000;
69 CHECKREG r4, 0x4A4B0000;
70 CHECKREG r5, 0x6A6B0000;
71 CHECKREG r6, 0x08090000;
72 CHECKREG r7, 0x28290000;
83 CHECKREG r0, 0x2C2D0000;
84 CHECKREG r1, 0x4C4D0000;
85 CHECKREG r2, 0x6C6D0000;
86 CHECKREG r3, 0x0E0F0000;
87 CHECKREG r4, 0x2E2F0000;
88 CHECKREG r5, 0x4E4F0000;
89 CHECKREG r6, 0x6E6F0000;
90 CHECKREG r7, 0x0C0D0000;
92 // reverse to minus mninus i--
93 // Load Upper half of Dregs
102 CHECKREG r0, 0x12130000;
103 CHECKREG r1, 0x32330000;
104 CHECKREG r2, 0x52530000;
105 CHECKREG r3, 0x72730000;
106 CHECKREG r4, 0x0C0D0000;
107 CHECKREG r5, 0x2C2D0000;
108 CHECKREG r6, 0x4C4D0000;
109 CHECKREG r7, 0x6C6D0000;
119 CHECKREG r0, 0x68690000;
120 CHECKREG r1, 0x0E0F0000;
121 CHECKREG r2, 0x2E2F0000;
122 CHECKREG r3, 0x4E4F0000;
123 CHECKREG r4, 0x6E6F0000;
124 CHECKREG r5, 0x08090000;
125 CHECKREG r6, 0x28290000;
126 CHECKREG r7, 0x48490000;
136 CHECKREG r0, 0x44450000;
137 CHECKREG r1, 0x64650000;
138 CHECKREG r2, 0x0A0B0000;
139 CHECKREG r3, 0x2A2B0000;
140 CHECKREG r4, 0x4A4B0000;
141 CHECKREG r5, 0x6A6B0000;
142 CHECKREG r6, 0x04050000;
143 CHECKREG r7, 0x24250000;
154 CHECKREG r0, 0x20210000;
155 CHECKREG r1, 0x40410000;
156 CHECKREG r2, 0x60610000;
157 CHECKREG r3, 0x06070000;
158 CHECKREG r4, 0x26270000;
159 CHECKREG r5, 0x46470000;
160 CHECKREG r6, 0x66670000;
161 CHECKREG r7, 0x00010000;
165 // Pre-load memory with known data
166 // More data is defined than will actually be used