1 //Original:/testcases/core/c_dspldst_ld_drhi_i/c_dspldst_ld_drhi_i.dsp
2 // Spec Reference: c_dspldst ld_drhi_i
5 .include "testutils.inc"
12 loadsym i0, DATA_ADDR_3;
13 loadsym i1, DATA_ADDR_4;
14 loadsym i2, DATA_ADDR_5;
15 loadsym i3, DATA_ADDR_6;
17 // Load upper half of Dregs
26 CHECKREG r0, 0x02030000;
27 CHECKREG r1, 0x22230000;
28 CHECKREG r2, 0x42430000;
29 CHECKREG r3, 0x62630000;
30 CHECKREG r4, 0x02030000;
31 CHECKREG r5, 0x22230000;
32 CHECKREG r6, 0x42430000;
33 CHECKREG r7, 0x62630000;
43 CHECKREG r0, 0x62630000;
44 CHECKREG r1, 0x02030000;
45 CHECKREG r2, 0x22230000;
46 CHECKREG r3, 0x42430000;
47 CHECKREG r4, 0x62630000;
48 CHECKREG r5, 0x02030000;
49 CHECKREG r6, 0x22230000;
50 CHECKREG r7, 0x42430000;
60 CHECKREG r0, 0x42430000;
61 CHECKREG r1, 0x62630000;
62 CHECKREG r2, 0x02030000;
63 CHECKREG r3, 0x22230000;
64 CHECKREG r4, 0x42430000;
65 CHECKREG r5, 0x62630000;
66 CHECKREG r6, 0x02030000;
67 CHECKREG r7, 0x22230000;
78 CHECKREG r0, 0x22230000;
79 CHECKREG r1, 0x42430000;
80 CHECKREG r2, 0x62630000;
81 CHECKREG r3, 0x02030000;
82 CHECKREG r4, 0x22230000;
83 CHECKREG r5, 0x42430000;
84 CHECKREG r6, 0x62630000;
85 CHECKREG r7, 0x02030000;
89 // Pre-load memory with known data
90 // More data is defined than will actually be used