sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp.s

   1 //Original:/testcases/core/c_dsp32shiftim_ahalf_rp/c_dsp32shiftim_ahalf_rp.dsp
   2 // Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 // Ashift : positive data, count (+)=right (half reg)
   9 // d_lo = ashft (d_lo BY d_lo)
  10 // RLx by RLx
  11 imm32 r0, 0x00000000;
  12 R0.L = -1;
  13 imm32 r1, 0x00010001;
  14 imm32 r2, 0x00010002;
  15 imm32 r3, 0x00010003;
  16 imm32 r4, 0x00010004;
  17 imm32 r5, 0x00010005;
  18 imm32 r6, 0x00010006;
  19 imm32 r7, 0x00010007;
  20 R0.L = R0.L >>> 1;
  21 R1.L = R1.L >>> 1;
  22 R2.L = R2.L >>> 1;
  23 R3.L = R3.L >>> 1;
  24 R4.L = R4.L >>> 1;
  25 R5.L = R5.L >>> 1;
  26 R6.L = R6.L >>> 1;
  27 R7.L = R7.L >>> 1;
  28 CHECKREG r0, 0x0000FFFF;
  29 CHECKREG r1, 0x00010000;
  30 CHECKREG r2, 0x00010001;
  31 CHECKREG r3, 0x00010001;
  32 CHECKREG r4, 0x00010002;
  33 CHECKREG r5, 0x00010002;
  34 CHECKREG r6, 0x00010003;
  35 CHECKREG r7, 0x00010003;
  36
  37 imm32 r0, 0x00201001;
  38 R1.L = -1;
  39 imm32 r2, 0x00202002;
  40 imm32 r3, 0x00203003;
  41 imm32 r4, 0x00204004;
  42 imm32 r5, 0x00205005;
  43 imm32 r6, 0x00206006;
  44 imm32 r7, 0x00207007;
  45 R7.L = R0.L >>> 5;
  46 R0.L = R1.L >>> 5;
  47 R1.L = R2.L >>> 5;
  48 R2.L = R3.L >>> 5;
  49 R3.L = R4.L >>> 5;
  50 R4.L = R5.L >>> 5;
  51 R5.L = R6.L >>> 5;
  52 R6.L = R7.L >>> 5;
  53 CHECKREG r0, 0x0020FFFF;
  54 CHECKREG r1, 0x00010100;
  55 CHECKREG r2, 0x00200180;
  56 CHECKREG r3, 0x00200200;
  57 CHECKREG r4, 0x00200280;
  58 CHECKREG r5, 0x00200300;
  59 CHECKREG r6, 0x00200004;
  60 CHECKREG r7, 0x00200080;
  61
  62
  63 imm32 r0, 0x03001001;
  64 imm32 r1, 0x03001001;
  65 R2.L = -15;
  66 imm32 r3, 0x03003003;
  67 imm32 r4, 0x03004004;
  68 imm32 r5, 0x03005005;
  69 imm32 r6, 0x03006006;
  70 imm32 r7, 0x03007007;
  71 R6.L = R0.L >>> 2;
  72 R7.L = R1.L >>> 2;
  73 R0.L = R2.L >>> 2;
  74 R1.L = R3.L >>> 2;
  75 R2.L = R4.L >>> 2;
  76 R3.L = R5.L >>> 2;
  77 R4.L = R6.L >>> 2;
  78 R5.L = R7.L >>> 2;
  79 CHECKREG r0, 0x0300FFFC;
  80 CHECKREG r1, 0x03000C00;
  81 CHECKREG r2, 0x00201001;
  82 CHECKREG r3, 0x03001401;
  83 CHECKREG r4, 0x03000100;
  84 CHECKREG r5, 0x03000100;
  85 CHECKREG r6, 0x03000400;
  86 CHECKREG r7, 0x03000400;
  87
  88 imm32 r0, 0x40001001;
  89 imm32 r1, 0x40001001;
  90 imm32 r2, 0x40002002;
  91 R3.L = -16;
  92 imm32 r4, 0x40004004;
  93 imm32 r5, 0x40005005;
  94 imm32 r6, 0x40006006;
  95 imm32 r7, 0x40007007;
  96 R5.L = R0.L >>> 13;
  97 R6.L = R1.L >>> 13;
  98 R7.L = R2.L >>> 13;
  99 R0.L = R3.L >>> 13;
 100 R1.L = R4.L >>> 13;
 101 R2.L = R5.L >>> 13;
 102 R3.L = R6.L >>> 13;
 103 R4.L = R7.L >>> 13;
 104 CHECKREG r0, 0x4000FFFF;
 105 CHECKREG r1, 0x40000002;
 106 CHECKREG r2, 0x40000000;
 107 CHECKREG r3, 0x03000000;
 108 CHECKREG r4, 0x40000000;
 109 CHECKREG r5, 0x40000000;
 110 CHECKREG r6, 0x40000000;
 111 CHECKREG r7, 0x40000001;
 112
 113 // d_lo = ashift (d_hi BY d_lo)
 114 // RHx by RLx
 115 imm32 r0, 0x50000000;
 116 imm32 r1, 0x50010000;
 117 imm32 r2, 0x50020000;
 118 imm32 r3, 0x50030000;
 119 imm32 r4, 0x50040000;
 120 imm32 r5, 0x50050000;
 121 imm32 r6, 0x50060000;
 122 imm32 r7, 0x50070000;
 123 R3.L = R0.H >>> 10;
 124 R4.L = R1.H >>> 10;
 125 R5.L = R2.H >>> 10;
 126 R6.L = R3.H >>> 10;
 127 R7.L = R4.H >>> 10;
 128 R0.L = R5.H >>> 10;
 129 R1.L = R6.H >>> 10;
 130 R2.L = R7.H >>> 10;
 131 CHECKREG r0, 0x50000014;
 132 CHECKREG r1, 0x50010014;
 133 CHECKREG r2, 0x50020014;
 134 CHECKREG r3, 0x50030014;
 135 CHECKREG r4, 0x50040014;
 136 CHECKREG r5, 0x50050014;
 137 CHECKREG r6, 0x50060014;
 138 CHECKREG r7, 0x50070014;
 139
 140 imm32 r0, 0x10016000;
 141 R1.L = -1;
 142 imm32 r2, 0x20026000;
 143 imm32 r3, 0x30036000;
 144 imm32 r4, 0x40046000;
 145 imm32 r5, 0x50056000;
 146 imm32 r6, 0x60060000;
 147 imm32 r7, 0x70076000;
 148 R0.L = R0.H >>> 11;
 149 R1.L = R1.H >>> 11;
 150 R2.L = R2.H >>> 11;
 151 R3.L = R3.H >>> 11;
 152 R4.L = R4.H >>> 11;
 153 R5.L = R5.H >>> 11;
 154 R6.L = R6.H >>> 11;
 155 R7.L = R7.H >>> 11;
 156 CHECKREG r0, 0x10010002;
 157 CHECKREG r1, 0x5001000A;
 158 CHECKREG r2, 0x20020004;
 159 CHECKREG r3, 0x30030006;
 160 CHECKREG r4, 0x40040008;
 161 CHECKREG r5, 0x5005000A;
 162 CHECKREG r6, 0x6006000C;
 163 CHECKREG r7, 0x7007000E;
 164
 165
 166 imm32 r0, 0x10010700;
 167 imm32 r1, 0x10010700;
 168 R2.L = -15;
 169 imm32 r3, 0x30030700;
 170 imm32 r4, 0x40040000;
 171 imm32 r5, 0x50050700;
 172 imm32 r6, 0x60060000;
 173 imm32 r7, 0x70070700;
 174 R0.L = R0.H >>> 15;
 175 R1.L = R1.H >>> 15;
 176 R2.L = R2.H >>> 15;
 177 R3.L = R3.H >>> 15;
 178 R4.L = R4.H >>> 15;
 179 R5.L = R5.H >>> 15;
 180 R6.L = R6.H >>> 15;
 181 R7.L = R7.H >>> 15;
 182 CHECKREG r0, 0x10010000;
 183 CHECKREG r1, 0x10010000;
 184 CHECKREG r2, 0x20020000;
 185 CHECKREG r3, 0x30030000;
 186 CHECKREG r4, 0x40040000;
 187 CHECKREG r5, 0x50050000;
 188 CHECKREG r6, 0x60060000;
 189 CHECKREG r7, 0x70070000;
 190
 191 imm32 r0, 0x18010001;
 192 imm32 r1, 0x18010001;
 193 imm32 r2, 0x28020002;
 194 R3.L = -16;
 195 imm32 r4, 0x48040004;
 196 imm32 r5, 0x58050005;
 197 imm32 r6, 0x68060006;
 198 imm32 r7, 0x78070007;
 199 R0.L = R0.H >>> 13;
 200 R1.L = R1.H >>> 13;
 201 R2.L = R2.H >>> 13;
 202 R3.L = R3.H >>> 13;
 203 R4.L = R4.H >>> 13;
 204 R5.L = R5.H >>> 13;
 205 R6.L = R6.H >>> 13;
 206 R7.L = R7.H >>> 13;
 207 CHECKREG r0, 0x18010000;
 208 CHECKREG r1, 0x18010000;
 209 CHECKREG r2, 0x28020001;
 210 CHECKREG r3, 0x30030001;
 211 CHECKREG r4, 0x48040002;
 212 CHECKREG r5, 0x58050002;
 213 CHECKREG r6, 0x68060003;
 214 CHECKREG r7, 0x78070003;
 215
 216 // d_hi = ashft (d_lo BY d_lo)
 217 // RLx by RLx
 218 imm32 r0, 0x09000091;
 219 imm32 r1, 0x09000091;
 220 imm32 r2, 0x09000092;
 221 imm32 r3, 0x09000093;
 222 imm32 r4, 0x09000090;
 223 imm32 r5, 0x09000095;
 224 imm32 r6, 0x09000096;
 225 imm32 r7, 0x09000097;
 226 R0.H = R0.L >>> 14;
 227 R1.H = R1.L >>> 14;
 228 R2.H = R2.L >>> 14;
 229 R3.H = R3.L >>> 14;
 230 R4.H = R4.L >>> 14;
 231 R5.H = R5.L >>> 14;
 232 R6.H = R6.L >>> 14;
 233 R7.H = R7.L >>> 14;
 234 CHECKREG r0, 0x00000091;
 235 CHECKREG r1, 0x00000091;
 236 CHECKREG r2, 0x00000092;
 237 CHECKREG r3, 0x00000093;
 238 CHECKREG r4, 0x00000090;
 239 CHECKREG r5, 0x00000095;
 240 CHECKREG r6, 0x00000096;
 241 CHECKREG r7, 0x00000097;
 242
 243 imm32 r0, 0xa0000001;
 244 imm32 r1, 0xa0000001;
 245 imm32 r2, 0xa0000002;
 246 imm32 r3, 0xa0000003;
 247 imm32 r4, 0xa0000004;
 248 R5.L = -1;
 249 imm32 r6, 0xa0000006;
 250 imm32 r7, 0xa0000007;
 251 R0.H = R0.L >>> 15;
 252 R1.H = R1.L >>> 15;
 253 R2.H = R2.L >>> 15;
 254 R3.H = R3.L >>> 15;
 255 R4.H = R4.L >>> 15;
 256 R5.H = R5.L >>> 15;
 257 R6.H = R6.L >>> 15;
 258 R7.H = R7.L >>> 15;
 259 CHECKREG r0, 0x00000001;
 260 CHECKREG r1, 0x00000001;
 261 CHECKREG r2, 0x00000002;
 262 CHECKREG r3, 0x00000003;
 263 CHECKREG r4, 0x00000004;
 264 CHECKREG r5, 0xFFFFFFFF;
 265 CHECKREG r6, 0x00000006;
 266 CHECKREG r7, 0x00000007;
 267
 268
 269 imm32 r0, 0xb0001001;
 270 imm32 r1, 0xb0001001;
 271 imm32 r1, 0xb0002002;
 272 imm32 r3, 0xb0003003;
 273 imm32 r4, 0xb0004004;
 274 imm32 r5, 0xb0005005;
 275 R6.L = -15;
 276 imm32 r7, 0xb0007007;
 277 R0.H = R0.L >>> 6;
 278 R1.H = R1.L >>> 6;
 279 R2.H = R2.L >>> 6;
 280 R3.H = R3.L >>> 6;
 281 R4.H = R4.L >>> 6;
 282 R5.H = R5.L >>> 6;
 283 R6.H = R6.L >>> 6;
 284 R7.H = R7.L >>> 6;
 285 CHECKREG r0, 0x00401001;
 286 CHECKREG r1, 0x00802002;
 287 CHECKREG r2, 0x00000002;
 288 CHECKREG r3, 0x00C03003;
 289 CHECKREG r4, 0x01004004;
 290 CHECKREG r5, 0x01405005;
 291 CHECKREG r6, 0xFFFFFFF1;
 292 CHECKREG r7, 0x01C07007;
 293
 294 imm32 r0, 0x0c001c01;
 295 imm32 r1, 0x0c002c01;
 296 imm32 r2, 0x0c002c02;
 297 imm32 r3, 0x0c003c03;
 298 imm32 r4, 0x0c004c04;
 299 imm32 r5, 0x0c005c05;
 300 imm32 r6, 0x0c006c06;
 301 R7.L = -16;
 302 R0.H = R0.L >>> 7;
 303 R1.H = R1.L >>> 7;
 304 R2.H = R2.L >>> 7;
 305 R3.H = R3.L >>> 7;
 306 R4.H = R4.L >>> 7;
 307 R5.H = R5.L >>> 7;
 308 R6.H = R6.L >>> 7;
 309 R7.H = R7.L >>> 7;
 310 CHECKREG r0, 0x00381C01;
 311 CHECKREG r1, 0x00582C01;
 312 CHECKREG r2, 0x00582C02;
 313 CHECKREG r3, 0x00783C03;
 314 CHECKREG r4, 0x00984C04;
 315 CHECKREG r5, 0x00B85C05;
 316 CHECKREG r6, 0x00D86C06;
 317 CHECKREG r7, 0xFFFFFFF0;
 318
 319 // d_lo = ashft (d_hi BY d_lo)
 320 // RHx by RLx
 321 imm32 r0, 0x0d01d000;
 322 imm32 r1, 0x0d01d000;
 323 imm32 r2, 0x0d02d000;
 324 imm32 r3, 0x0d03d000;
 325 R4.L = -1;
 326 imm32 r5, 0x0d05d000;
 327 imm32 r6, 0x0d06d000;
 328 imm32 r7, 0x0d07d000;
 329 R0.H = R0.H >>> 4;
 330 R1.H = R1.H >>> 4;
 331 R2.H = R2.H >>> 4;
 332 R3.H = R3.H >>> 4;
 333 R4.H = R4.H >>> 4;
 334 R5.H = R5.H >>> 4;
 335 R6.H = R6.H >>> 4;
 336 R7.H = R6.H >>> 4;
 337 CHECKREG r0, 0x00D0D000;
 338 CHECKREG r1, 0x00D0D000;
 339 CHECKREG r2, 0x00D0D000;
 340 CHECKREG r3, 0x00D0D000;
 341 CHECKREG r4, 0x0009FFFF;
 342 CHECKREG r5, 0x00D0D000;
 343 CHECKREG r6, 0x00D0D000;
 344 CHECKREG r7, 0x000DD000;
 345
 346 imm32 r0, 0x1e010000;
 347 imm32 r1, 0x1e010000;
 348 imm32 r2, 0x2e020000;
 349 imm32 r3, 0x3e030000;
 350 imm32 r4, 0x4e040000;
 351 R5.L = -1;
 352 imm32 r6, 0x6e060000;
 353 imm32 r7, 0x7e070000;
 354 R7.H = R0.H >>> 15;
 355 R6.H = R1.H >>> 15;
 356 R0.H = R2.H >>> 15;
 357 R1.H = R3.H >>> 15;
 358 R2.H = R4.H >>> 15;
 359 R3.H = R5.H >>> 15;
 360 R4.H = R6.H >>> 15;
 361 R5.H = R7.H >>> 15;
 362 CHECKREG r0, 0x00000000;
 363 CHECKREG r1, 0x00000000;
 364 CHECKREG r2, 0x00000000;
 365 CHECKREG r3, 0x00000000;
 366 CHECKREG r4, 0x00000000;
 367 CHECKREG r5, 0x0000FFFF;
 368 CHECKREG r6, 0x00000000;
 369 CHECKREG r7, 0x00000000;
 370
 371 imm32 r0, 0x1f010000;
 372 imm32 r1, 0x1f010000;
 373 imm32 r2, 0x2f020000;
 374 imm32 r3, 0x3f030000;
 375 imm32 r4, 0x4f040000;
 376 imm32 r5, 0x5f050000;
 377 R6.L = -15;
 378 imm32 r7, 0x70070000;
 379 R6.H = R0.H >>> 6;
 380 R7.H = R1.H >>> 6;
 381 R5.H = R2.H >>> 6;
 382 R0.H = R3.H >>> 6;
 383 R1.H = R4.H >>> 6;
 384 R2.H = R5.H >>> 6;
 385 R3.H = R6.H >>> 6;
 386 R4.H = R7.H >>> 6;
 387 CHECKREG r0, 0x00FC0000;
 388 CHECKREG r1, 0x013C0000;
 389 CHECKREG r2, 0x00020000;
 390 CHECKREG r3, 0x00010000;
 391 CHECKREG r4, 0x00010000;
 392 CHECKREG r5, 0x00BC0000;
 393 CHECKREG r6, 0x007CFFF1;
 394 CHECKREG r7, 0x007C0000;
 395
 396 imm32 r0, 0x11010a00;
 397 imm32 r1, 0x11010b00;
 398 imm32 r2, 0x21020d00;
 399 imm32 r2, 0x31030c00;
 400 imm32 r4, 0x41040d00;
 401 imm32 r5, 0x51050e00;
 402 imm32 r6, 0x610600f0;
 403 R7.L = -16;
 404 R5.H = R0.H >>> 7;
 405 R6.H = R1.H >>> 7;
 406 R7.H = R2.H >>> 7;
 407 R2.H = R3.H >>> 7;
 408 R3.H = R4.H >>> 7;
 409 R4.H = R5.H >>> 7;
 410 R0.H = R6.H >>> 7;
 411 R1.H = R7.H >>> 7;
 412 CHECKREG r0, 0x00000A00;
 413 CHECKREG r1, 0x00000B00;
 414 CHECKREG r2, 0x00000C00;
 415 CHECKREG r3, 0x00820000;
 416 CHECKREG r4, 0x00000D00;
 417 CHECKREG r5, 0x00220E00;
 418 CHECKREG r6, 0x002200F0;
 419 CHECKREG r7, 0x0062FFF0;
 420 pass