sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln.s

   1 //Original:/testcases/core/c_dsp32shiftim_ahalf_ln/c_dsp32shiftim_ahalf_ln.dsp
   2 // Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 // Ashift : neg data, count (+)=left (half reg)
   9 // d_lo = ashft (d_lo BY d_lo)
  10 // RLx by RLx
  11 imm32 r0, 0x1000c000;
  12 imm32 r1, 0x1000c001;
  13 imm32 r2, 0x1000c002;
  14 imm32 r3, 0x1000c003;
  15 imm32 r4, 0x1000c004;
  16 imm32 r5, 0x1000c005;
  17 imm32 r6, 0x1000c006;
  18 imm32 r7, 0x1000c007;
  19 R0.L = R0.L << 1;
  20 R1.L = R1.L << 1;
  21 R2.L = R2.L << 1;
  22 R3.L = R3.L << 1;
  23 R4.L = R4.L << 1;
  24 R5.L = R5.L << 1;
  25 R6.L = R6.L << 1;
  26 R7.L = R7.L << 1;
  27 CHECKREG r0, 0x10008000;
  28 CHECKREG r1, 0x10008002;
  29 CHECKREG r2, 0x10008004;
  30 CHECKREG r3, 0x10008006;
  31 CHECKREG r4, 0x10008008;
  32 CHECKREG r5, 0x1000800A;
  33 CHECKREG r6, 0x1000800C;
  34 CHECKREG r7, 0x1000800E;
  35
  36 imm32 r0, 0x20008001;
  37 imm32 r1, 0x20000001;
  38 imm32 r2, 0x2000d002;
  39 imm32 r3, 0x2000e003;
  40 imm32 r4, 0x2000f004;
  41 imm32 r5, 0x2000c005;
  42 imm32 r6, 0x2000d006;
  43 imm32 r7, 0x2000e007;
  44 R7.L = R0.L << 1;
  45 R6.L = R1.L << 1;
  46 R5.L = R2.L << 1;
  47 R4.L = R3.L << 1;
  48 R3.L = R4.L << 1;
  49 R2.L = R5.L << 1;
  50 R1.L = R6.L << 1;
  51 R0.L = R7.L << 1;
  52
  53 imm32 r0, 0x3000c001;
  54 imm32 r1, 0x3000d001;
  55 imm32 r2, 0x3000000f;
  56 imm32 r3, 0x3000e003;
  57 imm32 r4, 0x3000f004;
  58 imm32 r5, 0x3000f005;
  59 imm32 r6, 0x3000f006;
  60 imm32 r7, 0x3000f007;
  61 R6.L = R0.L << 12;
  62 R7.L = R1.L << 12;
  63 R5.L = R2.L << 12;
  64 R4.L = R3.L << 12;
  65 R3.L = R4.L << 12;
  66 R2.L = R5.L << 12;
  67 R1.L = R6.L << 12;
  68 R0.L = R7.L << 12;
  69 CHECKREG r1, 0x30000000;
  70 CHECKREG r0, 0x30000000;
  71 CHECKREG r2, 0x30000000;
  72 CHECKREG r3, 0x30000000;
  73 CHECKREG r4, 0x30003000;
  74 CHECKREG r5, 0x3000F000;
  75 CHECKREG r6, 0x30001000;
  76 CHECKREG r7, 0x30001000;
  77
  78 imm32 r0, 0x40009001;
  79 imm32 r1, 0x4000a001;
  80 imm32 r2, 0x4000b002;
  81 imm32 r3, 0x40000010;
  82 imm32 r4, 0x4000c004;
  83 imm32 r5, 0x4000d005;
  84 imm32 r6, 0x4000e006;
  85 imm32 r7, 0x4000f007;
  86 R5.L = R0.L << 13;
  87 R6.L = R1.L << 13;
  88 R7.L = R2.L << 13;
  89 R0.L = R3.L << 13;
  90 R1.L = R4.L << 13;
  91 R2.L = R5.L << 13;
  92 R3.L = R6.L << 13;
  93 R4.L = R7.L << 13;
  94 CHECKREG r0, 0x40000000;
  95 CHECKREG r1, 0x40008000;
  96 CHECKREG r2, 0x40000000;
  97 CHECKREG r3, 0x40000000;
  98 CHECKREG r4, 0x40000000;
  99 CHECKREG r5, 0x40002000;
 100 CHECKREG r6, 0x40002000;
 101 CHECKREG r7, 0x40004000;
 102
 103 imm32 r0, 0x00005000;
 104 imm32 r1, 0x00015000;
 105 imm32 r2, 0x00025000;
 106 imm32 r3, 0x00035000;
 107 imm32 r4, 0x00045000;
 108 imm32 r5, 0x00055000;
 109 imm32 r6, 0x00065000;
 110 imm32 r7, 0x00075500;
 111 R0.L = R0.H << 10;
 112 R1.L = R1.H << 10;
 113 R2.L = R2.H << 10;
 114 R3.L = R3.H << 10;
 115 R4.L = R4.H << 10;
 116 R5.L = R5.H << 10;
 117 R6.L = R6.H << 10;
 118 R7.L = R7.H << 10;
 119 CHECKREG r0, 0x00000000;
 120 CHECKREG r1, 0x00010400;
 121 CHECKREG r2, 0x00020800;
 122 CHECKREG r3, 0x00030C00;
 123 CHECKREG r4, 0x00041000;
 124 CHECKREG r5, 0x00051400;
 125 CHECKREG r6, 0x00061800;
 126 CHECKREG r7, 0x00071C00;
 127
 128 imm32 r0, 0x90010000;
 129 imm32 r1, 0x90010001;
 130 imm32 r2, 0x90020000;
 131 imm32 r3, 0x90030000;
 132 imm32 r4, 0x90040000;
 133 imm32 r5, 0x90050000;
 134 imm32 r6, 0x90060000;
 135 imm32 r7, 0x90070000;
 136 R2.L = R0.H << 11;
 137 R3.L = R1.H << 11;
 138 R4.L = R2.H << 11;
 139 R5.L = R3.H << 11;
 140 R6.L = R4.H << 11;
 141 R7.L = R5.H << 11;
 142 R0.L = R6.H << 11;
 143 R1.L = R7.H << 11;
 144 CHECKREG r0, 0x90013000;
 145 CHECKREG r1, 0x90013800;
 146 CHECKREG r2, 0x90020800;
 147 CHECKREG r3, 0x90030800;
 148 CHECKREG r4, 0x90041000;
 149 CHECKREG r5, 0x90051800;
 150 CHECKREG r6, 0x90062000;
 151 CHECKREG r7, 0x90072800;
 152
 153
 154 imm32 r0, 0xa0010600;
 155 imm32 r1, 0xa0010600;
 156 imm32 r2, 0xa002060f;
 157 imm32 r3, 0xa0030600;
 158 imm32 r4, 0xa0040600;
 159 imm32 r5, 0xa0050600;
 160 imm32 r6, 0xa0060600;
 161 imm32 r7, 0xa0070600;
 162 R0.L = R0.H << 12;
 163 R1.L = R1.H << 12;
 164 R2.L = R2.H << 12;
 165 R3.L = R3.H << 12;
 166 R4.L = R4.H << 12;
 167 R5.L = R5.H << 12;
 168 R6.L = R6.H << 12;
 169 R7.L = R7.H << 12;
 170 CHECKREG r0, 0xA0011000;
 171 CHECKREG r1, 0xA0011000;
 172 CHECKREG r2, 0xA0022000;
 173 CHECKREG r3, 0xA0033000;
 174 CHECKREG r4, 0xA0044000;
 175 CHECKREG r5, 0xA0055000;
 176 CHECKREG r6, 0xA0066000;
 177 CHECKREG r7, 0xA0077000;
 178
 179 imm32 r0, 0xc0010701;
 180 imm32 r1, 0xc0010701;
 181 imm32 r2, 0xc0020702;
 182 imm32 r3, 0xc0030710;
 183 imm32 r4, 0xc0040704;
 184 imm32 r5, 0xc0050705;
 185 imm32 r6, 0xc0060706;
 186 imm32 r7, 0xc0070707;
 187 R0.L = R0.H << 13;
 188 R1.L = R1.H << 13;
 189 R2.L = R2.H << 13;
 190 R3.L = R3.H << 13;
 191 R4.L = R4.H << 13;
 192 R5.L = R5.H << 13;
 193 R6.L = R6.H << 13;
 194 R7.L = R7.H << 13;
 195 CHECKREG r0, 0xC0012000;
 196 CHECKREG r1, 0xC0012000;
 197 CHECKREG r2, 0xC0024000;
 198 CHECKREG r3, 0xC0036000;
 199 CHECKREG r4, 0xC0048000;
 200 CHECKREG r5, 0xC005A000;
 201 CHECKREG r6, 0xC006C000;
 202 CHECKREG r7, 0xC007E000;
 203
 204 imm32 r0, 0x00008000;
 205 imm32 r1, 0x00008001;
 206 imm32 r2, 0x00008002;
 207 imm32 r3, 0x00008003;
 208 imm32 r4, 0x00008004;
 209 imm32 r5, 0x00008005;
 210 imm32 r6, 0x00008006;
 211 imm32 r7, 0x00008007;
 212 R0.H = R0.L << 0;
 213 R1.H = R1.L << 1;
 214 R2.H = R2.L << 2;
 215 R3.H = R3.L << 3;
 216 R4.H = R4.L << 4;
 217 R5.H = R5.L << 5;
 218 R6.H = R6.L << 6;
 219 R7.H = R7.L << 7;
 220 CHECKREG r0, 0x80008000;
 221 CHECKREG r1, 0x00028001;
 222 CHECKREG r2, 0x00088002;
 223 CHECKREG r3, 0x00188003;
 224 CHECKREG r4, 0x00408004;
 225 CHECKREG r5, 0x00A08005;
 226 CHECKREG r6, 0x01808006;
 227 CHECKREG r7, 0x03808007;
 228
 229 imm32 r0, 0x0000d001;
 230 imm32 r1, 0x00000001;
 231 imm32 r2, 0x0000d002;
 232 imm32 r3, 0x0000d003;
 233 imm32 r4, 0x0000d004;
 234 imm32 r5, 0x0000d005;
 235 imm32 r6, 0x0000d006;
 236 imm32 r7, 0x0000d007;
 237 R2.H = R0.L << 8;
 238 R3.H = R1.L << 9;
 239 R4.H = R2.L << 10;
 240 R5.H = R3.L << 11;
 241 R6.H = R4.L << 12;
 242 R7.H = R5.L << 13;
 243 R0.H = R6.L << 14;
 244 R1.H = R7.L << 15;
 245 CHECKREG r0, 0x8000D001;
 246 CHECKREG r1, 0x80000001;
 247 CHECKREG r2, 0x0100D002;
 248 CHECKREG r3, 0x0200D003;
 249 CHECKREG r4, 0x0800D004;
 250 CHECKREG r5, 0x1800D005;
 251 CHECKREG r6, 0x4000D006;
 252 CHECKREG r7, 0xA000D007;
 253
 254 imm32 r0, 0x0000e001;
 255 imm32 r1, 0x0000e001;
 256 imm32 r2, 0x0000000f;
 257 imm32 r3, 0x0000e003;
 258 imm32 r4, 0x0000e004;
 259 imm32 r5, 0x0000e005;
 260 imm32 r6, 0x0000e006;
 261 imm32 r7, 0x0000e007;
 262 R0.H = R0.L << 12;
 263 R1.H = R1.L << 12;
 264 R2.H = R2.L << 12;
 265 R3.H = R3.L << 12;
 266 R4.H = R4.L << 12;
 267 R5.H = R5.L << 12;
 268 R6.H = R6.L << 12;
 269 R7.H = R7.L << 12;
 270 CHECKREG r0, 0x1000E001;
 271 CHECKREG r1, 0x1000E001;
 272 CHECKREG r2, 0xF000000F;
 273 CHECKREG r3, 0x3000E003;
 274 CHECKREG r4, 0x4000E004;
 275 CHECKREG r5, 0x5000E005;
 276 CHECKREG r6, 0x6000E006;
 277 CHECKREG r7, 0x7000E007;
 278
 279 imm32 r0, 0x0000f001;
 280 imm32 r1, 0x0000f001;
 281 imm32 r2, 0x0000f002;
 282 imm32 r3, 0x00000010;
 283 imm32 r4, 0x0000f004;
 284 imm32 r5, 0x0000f005;
 285 imm32 r6, 0x0000f006;
 286 imm32 r7, 0x0000f007;
 287 R5.H = R0.L << 13;
 288 R6.H = R1.L << 13;
 289 R7.H = R2.L << 13;
 290 R0.H = R3.L << 13;
 291 R1.H = R4.L << 13;
 292 R2.H = R5.L << 13;
 293 R3.H = R6.L << 13;
 294 R4.H = R7.L << 13;
 295 CHECKREG r0, 0x0000F001;
 296 CHECKREG r1, 0x8000F001;
 297 CHECKREG r2, 0xA000F002;
 298 CHECKREG r3, 0xC0000010;
 299 CHECKREG r4, 0xE000F004;
 300 CHECKREG r5, 0x2000F005;
 301 CHECKREG r6, 0x2000F006;
 302 CHECKREG r7, 0x4000F007;
 303
 304 // d_lo = ashift (d_hi BY d_lo)
 305 // RHx by RLx
 306 imm32 r0, 0x90000000;
 307 imm32 r1, 0x90010000;
 308 imm32 r2, 0x90020000;
 309 imm32 r3, 0x90030000;
 310 imm32 r4, 0x90040000;
 311 imm32 r5, 0x90050000;
 312 imm32 r6, 0x90060000;
 313 imm32 r7, 0x90070000;
 314 R4.H = R0.H << 10;
 315 R5.H = R1.H << 10;
 316 R6.H = R2.H << 10;
 317 R7.H = R3.H << 10;
 318 R0.H = R4.H << 10;
 319 R1.H = R5.H << 10;
 320 R2.H = R6.H << 10;
 321 R3.H = R7.H << 10;
 322 CHECKREG r0, 0x00000000;
 323 CHECKREG r1, 0x00000000;
 324 CHECKREG r2, 0x00000000;
 325 CHECKREG r3, 0x00000000;
 326 CHECKREG r4, 0x00000000;
 327 CHECKREG r5, 0x04000000;
 328 CHECKREG r6, 0x08000000;
 329 CHECKREG r7, 0x0C000000;
 330
 331 imm32 r0, 0xa0010000;
 332 imm32 r1, 0x00010001;
 333 imm32 r2, 0xa0020000;
 334 imm32 r3, 0xa0030000;
 335 imm32 r4, 0xa0040000;
 336 imm32 r5, 0xa0050000;
 337 imm32 r6, 0xa0060000;
 338 imm32 r7, 0xa0070000;
 339 R7.H = R0.H << 11;
 340 R0.H = R1.H << 11;
 341 R1.H = R2.H << 11;
 342 R2.H = R3.H << 11;
 343 R3.H = R4.H << 11;
 344 R4.H = R5.H << 11;
 345 R5.H = R6.H << 11;
 346 R6.H = R7.H << 11;
 347 CHECKREG r0, 0x08000000;
 348 CHECKREG r1, 0x10000001;
 349 CHECKREG r2, 0x18000000;
 350 CHECKREG r3, 0x20000000;
 351 CHECKREG r4, 0x28000000;
 352 CHECKREG r5, 0x30000000;
 353 CHECKREG r6, 0x00000000;
 354 CHECKREG r7, 0x08000000;
 355
 356
 357 imm32 r0, 0xb0010000;
 358 imm32 r1, 0xb0010000;
 359 imm32 r2, 0xb002000f;
 360 imm32 r3, 0xb0030000;
 361 imm32 r4, 0xb0040000;
 362 imm32 r5, 0xb0050000;
 363 imm32 r6, 0xb0060000;
 364 imm32 r7, 0xb0070000;
 365 R6.H = R0.H << 12;
 366 R7.H = R1.H << 12;
 367 R0.H = R2.H << 12;
 368 R1.H = R3.H << 12;
 369 R2.H = R4.H << 12;
 370 R3.H = R5.H << 12;
 371 R4.H = R6.H << 12;
 372 R5.H = R7.H << 12;
 373 CHECKREG r0, 0x20000000;
 374 CHECKREG r1, 0x30000000;
 375 CHECKREG r2, 0x4000000F;
 376 CHECKREG r3, 0x50000000;
 377 CHECKREG r4, 0x00000000;
 378 CHECKREG r5, 0x00000000;
 379 CHECKREG r6, 0x10000000;
 380 CHECKREG r7, 0x10000000;
 381
 382 imm32 r0, 0xd0010000;
 383 imm32 r1, 0xd0010000;
 384 imm32 r2, 0xd0020000;
 385 imm32 r3, 0xd0030010;
 386 imm32 r4, 0xd0040000;
 387 imm32 r5, 0xd0050000;
 388 imm32 r6, 0xd0060000;
 389 imm32 r7, 0xd0070000;
 390 R5.H = R0.H << 3;
 391 R6.H = R1.H << 3;
 392 R7.H = R2.H << 3;
 393 R0.H = R3.H << 3;
 394 R1.H = R4.H << 3;
 395 R2.H = R5.H << 3;
 396 R3.H = R6.H << 3;
 397 R4.H = R7.H << 3;
 398 CHECKREG r0, 0x80180000;
 399 CHECKREG r1, 0x80200000;
 400 CHECKREG r2, 0x00400000;
 401 CHECKREG r3, 0x00400010;
 402 CHECKREG r4, 0x00800000;
 403 CHECKREG r5, 0x80080000;
 404 CHECKREG r6, 0x80080000;
 405 CHECKREG r7, 0x80100000;
 406 pass