1 //Original:/testcases/core/c_dsp32mult_dr_m_iutsh/c_dsp32mult_dr_m_iutsh.dsp
2 // Spec Reference: dsp32mult single dr munop iu tu is ih
5 .include "testutils.inc"
16 R4.L = R0.H * R0.L (TFU);
17 R5.H = R0.L * R1.L (IU);
18 R6.L = R1.L * R0.H (TFU);
19 R7.L = R1.L * R1.L (TFU);
20 R0.H = R0.L * R0.L (IU);
21 R1.L = R0.L * R1.L (TFU);
22 R2.L = R1.H * R0.L (IU);
23 R3.H = R1.L * R1.L (TFU);
24 CHECKREG r0, 0xFFFF5625;
25 CHECKREG r1, 0x9FBA1B4E;
26 CHECKREG r2, 0xA3FFFFFF;
27 CHECKREG r3, 0x02E9F027;
28 CHECKREG r4, 0xB0AB5482;
29 CHECKREG r5, 0xFFFFEF2B;
30 CHECKREG r6, 0xC0FC4F9C;
31 CHECKREG r7, 0xD24F19B9;
41 R4.H = R2.L * R2.L (ISS2);
42 R5.L = R2.L * R3.H (IH);
43 R6.L = R3.H * R2.L (ISS2);
44 R7.H = R3.L * R3.L (ISS2);
45 R2.H = R2.L * R2.H (IH);
46 R3.L = R2.H * R3.H (ISS2);
47 R0.H = R3.L * R2.L (IH);
48 R1.L = R3.L * R3.L (ISS2);
49 CHECKREG r0, 0xDBF3A635;
50 CHECKREG r1, 0x6FBA7FFF;
51 CHECKREG r2, 0xFA9CB7E5;
52 CHECKREG r3, 0x9E067FFF;
53 CHECKREG r4, 0x7FFFCD39;
54 CHECKREG r5, 0xB0AE1B99;
55 CHECKREG r6, 0xA00C7FFF;
56 CHECKREG r7, 0x17A27E03;
66 R0.L = R4.L * R4.H (IU);
67 R1.H = R4.H * R5.L (TFU);
68 R2.L = R5.H * R4.L (ISS2);
69 R3.L = R5.L * R5.L (IH);
70 R4.H = R4.L * R4.H (ISS2);
71 R5.L = R4.L * R5.H (TFU);
72 R6.H = R5.H * R4.H (IU);
73 R7.L = R5.H * R5.H (ISS2);
74 CHECKREG r0, 0xDD23FFFF;
75 CHECKREG r1, 0x876F5157;
76 CHECKREG r2, 0x63248000;
77 CHECKREG r3, 0x00060115;
78 CHECKREG r4, 0x7FFFC509;
79 CHECKREG r5, 0x10AD0CD5;
80 CHECKREG r6, 0xFFFFD05D;
81 CHECKREG r7, 0x12467FFF;
91 // test the unsigned U=1
92 R0.L = R6.L * R6.L (TFU);
93 R1.H = R6.H * R7.L (IH);
94 R2.L = R7.L * R6.L (ISS2);
95 R3.L = R7.L * R7.L (IH);
96 R6.L = R6.L * R6.L (TFU);
97 R7.L = R6.L * R7.L (IH);
98 R4.L = R7.L * R6.L (TFU);
99 R5.L = R7.L * R7.L (ISS2);
100 CHECKREG r0, 0xCB2390A3;
101 CHECKREG r1, 0xC1CE5166;
102 CHECKREG r2, 0x1C248000;
103 CHECKREG r3, 0xF0063C7C;
104 CHECKREG r4, 0x90CB720D;
105 CHECKREG r5, 0x10AC7FFF;
106 CHECKREG r6, 0x800C90A3;
107 CHECKREG r7, 0x1246C9DF;
110 imm32 r0, 0xab23a675;
111 imm32 r1, 0xcfba5127;
112 imm32 r2, 0x13246705;
113 imm32 r3, 0xe0060007;
114 imm32 r4, 0x9eabcd09;
115 imm32 r5, 0x10ecdfdb;
116 imm32 r6, 0x000e000d;
117 imm32 r7, 0x1246e00f;
118 R0.H = R0.L * R7.H (IU);
119 R1.L = R1.H * R6.H (ISS2);
120 R2.L = R2.L * R5.L (IU);
121 R3.H = R3.H * R4.H (ISS2);
122 R4.L = R4.L * R3.H (IU);
123 R5.L = R5.H * R2.H (ISS2);
124 R6.H = R6.H * R1.L (IH);
125 R7.L = R7.L * R0.H (IU);
126 CHECKREG r0, 0xFFFFA675;
127 CHECKREG r1, 0xCFBA8000;
128 CHECKREG r2, 0x1324FFFF;
129 CHECKREG r3, 0x7FFF0007;
130 CHECKREG r4, 0x9EABFFFF;
131 CHECKREG r5, 0x10EC7FFF;
132 CHECKREG r6, 0xFFF9000D;
133 CHECKREG r7, 0x1246FFFF;
135 imm32 r0, 0x9b235a75;
136 imm32 r1, 0xcfba5127;
137 imm32 r2, 0x93246905;
138 imm32 r3, 0x09060007;
139 imm32 r4, 0x909bcd09;
140 imm32 r5, 0x10a9e9db;
141 imm32 r6, 0x000c9d0d;
142 imm32 r7, 0x1246790f;
143 R0.L = R7.L * R0.H (TFU);
144 R1.L = R6.L * R1.L (TFU);
145 R2.H = R5.L * R2.L (TFU);
146 R3.L = R4.H * R3.L (TFU);
147 R4.L = R3.H * R4.H (TFU);
148 R5.H = R2.H * R5.L (TFU);
149 R6.L = R1.H * R6.L (TFU);
150 R7.L = R0.L * R7.L (TFU);
151 CHECKREG r0, 0x9B23495C;
152 CHECKREG r1, 0xCFBA31C9;
153 CHECKREG r2, 0x5FEF6905;
154 CHECKREG r3, 0x09060003;
155 CHECKREG r4, 0x909B0518;
156 CHECKREG r5, 0x57A2E9DB;
157 CHECKREG r6, 0x000C7F6F;
158 CHECKREG r7, 0x124622B0;
160 imm32 r0, 0xa9235675;
161 imm32 r1, 0xc8ba5127;
162 imm32 r2, 0x13246705;
163 imm32 r3, 0x08060007;
164 imm32 r4, 0x908bcd09;
165 imm32 r5, 0x10a88fdb;
166 imm32 r6, 0x000c080d;
167 imm32 r7, 0x1246708f;
168 R2.L = R0.L * R6.L (IU);
169 R3.L = R1.H * R7.L (IH);
170 R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IU);
171 R1.H = R3.L * R1.L (IH);
172 R4.L = R4.H * R2.L (IU);
173 R5.L = R5.L * R3.L (ISS2);
174 R6.L = R6.L * R4.L (IH);
175 R7.H = R7.H * R5.L (IU);
176 CHECKREG r0, 0xFFFFFFFF;
177 CHECKREG r1, 0xF84C5127;
178 CHECKREG r2, 0x1324FFFF;
179 CHECKREG r3, 0x0806E7B2;
180 CHECKREG r4, 0x908BFFFF;
181 CHECKREG r5, 0x10A87FFF;
182 CHECKREG r6, 0x000C0000;
183 CHECKREG r7, 0xFFFF708F;
185 imm32 r0, 0x7b235675;
186 imm32 r1, 0xcfba5127;
187 imm32 r2, 0x17246705;
188 imm32 r3, 0x00760007;
189 imm32 r4, 0x907bcd09;
190 imm32 r5, 0x10a7efdb;
191 imm32 r6, 0x000c700d;
192 imm32 r7, 0x1246770f;
193 R4.L = R5.L * R2.L (TFU);
194 R6.L = R6.L * R3.H (ISS2);
195 R0.H = R7.L * R4.H (ISS2);
196 R1.L = R0.H * R5.L (ISS2);
197 R2.L = R1.L * R6.L (IH);
198 R5.L = R2.L * R7.H (TFU);
199 R3.H = R3.H * R0.L (IH);
200 R7.L = R4.H * R1.H (IU);
201 CHECKREG r0, 0x80005675;
202 CHECKREG r1, 0xCFBA7FFF;
203 CHECKREG r2, 0x17243FFF;
204 CHECKREG r3, 0x00280007;
205 CHECKREG r4, 0x907B6085;
206 CHECKREG r5, 0x10A70491;
207 CHECKREG r6, 0x000C7FFF;
208 CHECKREG r7, 0x1246FFFF;