sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s

   1 //Original:/testcases/core/c_dsp32mac_a1a0_m/c_dsp32mac_a1a0_m.dsp
   2 // Spec Reference: dsp32mac a1 a0 m MNOP
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9         INIT_R_REGS 0;
  10
  11
  12         imm32 r0, 0x00000000;
  13         A0 = 0;
  14         A1 = 0;
  15         ASTAT = r0;
  16
  17 // test the MNOP  default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1
  18         imm32 r0, 0x123c5678;
  19         imm32 r1, 0x2345c789;
  20         imm32 r2, 0x34567c9a;
  21         imm32 r3, 0x456789c2;
  22         imm32 r4, 0xc678912c;
  23         imm32 r5, 0x6c891234;
  24         imm32 r6, 0xa1c34567;
  25         imm32 r7, 0xc12c4567;
  26
  27         A0 = 0;
  28         A1 = 0;
  29
  30         A1 = R0.L * R1.L (M);
  31         R0 = A0.w;
  32         R1 = A1.w;
  33         A0 += R2.H * R3.H;
  34         R2 = A0.w;
  35         R3 = A1.w;
  36         A1 += R4.L * R5.H;
  37         R4 = A0.w;
  38         R5 = A1.w;
  39         A0 += R6.L * R7.H;
  40         R6 = A0.w;
  41         R7 = A1.w;
  42         CHECKREG r0, 0x00000000;
  43         CHECKREG r1, 0x43658E38;
  44         CHECKREG r2, 0x1C607934;
  45         CHECKREG r3, 0x43658E38;
  46         CHECKREG r4, 0x1C607934;
  47         CHECKREG r5, 0xE56C0F50;
  48         CHECKREG r6, 0xFA4FA29C;
  49         CHECKREG r7, 0xE56C0F50;
  50
  51         imm32 r0, 0xd2345678;
  52         imm32 r1, 0x2d456789;
  53         imm32 r2, 0x34d6789a;
  54         imm32 r3, 0x456d8912;
  55         imm32 r4, 0x5678d123;
  56         imm32 r5, 0x67891d34;
  57         imm32 r6, 0xa12345d7;
  58         imm32 r7, 0xc123456d;
  59         A0 += R6.H * R7.L;
  60         R6 = A0.w;
  61         R7 = A1.w;
  62         A1 += R4.L * R5.H;
  63         R4 = A0.w;
  64         R5 = A1.w;
  65         A0 += R2.L * R3.L;
  66         R2 = A0.w;
  67         R3 = A1.w;
  68         A1 += R0.H * R1.L;
  69         R0 = A0.w;
  70         R1 = A1.w;
  71         CHECKREG r0, 0x56CD8212;
  72         CHECKREG r1, 0x9A78E46E;
  73         CHECKREG r2, 0x56CD8212;
  74         CHECKREG r3, 0xBF8410C6;
  75         CHECKREG r4, 0xC6DBB86A;
  76         CHECKREG r5, 0xBF8410C6;
  77         CHECKREG r6, 0xC6DBB86A;
  78         CHECKREG r7, 0xE56C0F50;
  79
  80 // test MM=1(Mix mode), MAC1 executes a mixed mode multiplication: (one input is
  81 // signed, the other input is unsigned
  82         imm32 r0, 0x12345678;
  83         imm32 r1, 0x33456789;
  84         imm32 r2, 0x5556789a;
  85         imm32 r3, 0x75678912;
  86         imm32 r4, 0x86789123;
  87         imm32 r5, 0xa7891234;
  88         imm32 r6, 0xc1234567;
  89         imm32 r7, 0xf1234567;
  90         A1 += R0.L * R1.L (M), A0 = R0.L * R1.L;
  91         R0 = A0.w;
  92         R1 = A1.w;
  93         A1 = R2.L * R3.L (M), A0 += R2.L * R3.H;
  94         R2 = A0.w;
  95         R3 = A1.w;
  96         A1 += R4.L * R5.L (M), A0 = R4.H * R5.L;
  97         R4 = A0.w;
  98         R5 = A1.w;
  99         A1 = R6.L * R7.L (M), A0 = R6.H * R7.H;
 100         R6 = A0.w;
 101         R7 = A1.w;
 102         CHECKREG r0, 0x45F11C70;
 103         CHECKREG r1, 0xBD7172A6;
 104         CHECKREG r2, 0xB48EEC5C;
 105         CHECKREG r3, 0x4092E4D4;
 106         CHECKREG r4, 0xEEB780C0;
 107         CHECKREG r5, 0x38B0D5F0;
 108         CHECKREG r6, 0x074CB592;
 109         CHECKREG r7, 0x12D0AF71;
 110
 111         imm32 r0, 0x12245618;
 112         imm32 r1, 0x23256719;
 113         imm32 r2, 0x3426781a;
 114         imm32 r3, 0x45278912;
 115         imm32 r4, 0x56289113;
 116         imm32 r5, 0x67291214;
 117         imm32 r6, 0xa1234517;
 118         imm32 r7, 0xc1234517;
 119         A1 += R0.L * R1.H (M), A0 = R0.L * R1.L;
 120         R0 = A0.w;
 121         R1 = A1.w;
 122         A1 += R2.L * R3.H (M), A0 = R2.L * R3.H;
 123         R2 = A0.w;
 124         R3 = A1.w;
 125         A1 += R4.L * R5.H (M), A0 = R4.H * R5.L;
 126         R4 = A0.w;
 127         R5 = A1.w;
 128         A1 += R6.L * R7.H (M), A0 += R6.H * R7.H;
 129         R6 = A0.w;
 130         R7 = A1.w;
 131         CHECKREG r0, 0x455820B0;
 132         CHECKREG r1, 0x1EA268E9;
 133         CHECKREG r2, 0x40E29BEC;
 134         CHECKREG r3, 0x3F13B6DF;
 135         CHECKREG r4, 0x0C2B1640;
 136         CHECKREG r5, 0x126097EA;
 137         CHECKREG r6, 0x3AC1EBD2;
 138         CHECKREG r7, 0x4680610F;
 139
 140         imm32 r0, 0x15245648;
 141         imm32 r1, 0x25256749;
 142         imm32 r2, 0x3526784a;
 143         imm32 r3, 0x45278942;
 144         imm32 r4, 0x55389143;
 145         imm32 r5, 0x65391244;
 146         imm32 r6, 0xa5334547;
 147         imm32 r7, 0xc5334547;
 148         A1 = R0.H * R1.H (M), A0 = R0.L * R1.L;
 149         R0 = A0.w;
 150         R1 = A1.w;
 151         A1 += R2.H * R3.H (M), A0 += R2.L * R3.H;
 152         R2 = A0.w;
 153         R3 = A1.w;
 154         A1 = R4.H * R5.H (M), A0 = R4.H * R5.L;
 155         R4 = A0.w;
 156         R5 = A1.w;
 157         A1 = R6.H * R7.H (M), A0 = R6.H * R7.H;
 158         R6 = A0.w;
 159         R7 = A1.w;
 160         CHECKREG r0, 0x459F2510;
 161         CHECKREG r1, 0x03114234;
 162         CHECKREG r2, 0x869BAF9C;
 163         CHECKREG r3, 0x116C98FE;
 164         CHECKREG r4, 0x0C2925C0;
 165         CHECKREG r5, 0x21B21178;
 166         CHECKREG r6, 0x29B65052;
 167         CHECKREG r7, 0xBA0E2829;
 168
 169         imm32 r0, 0x13245628;
 170         imm32 r1, 0x23256729;
 171         imm32 r2, 0x3326782a;
 172         imm32 r3, 0x43278922;
 173         imm32 r4, 0x56389123;
 174         imm32 r5, 0x67391224;
 175         imm32 r6, 0xa1334527;
 176         imm32 r7, 0xc1334527;
 177         A1 = R0.H * R1.L (M), A0 = R0.L * R1.L;
 178         R0 = A0.w;
 179         R1 = A1.w;
 180         A1 += R2.H * R3.L (M), A0 = R2.L * R3.H;
 181         R2 = A0.w;
 182         R3 = A1.w;
 183         A1 = R4.H * R5.L (M), A0 = R4.H * R5.L;
 184         R4 = A0.w;
 185         R5 = A1.w;
 186         A1 += R6.H * R7.L (M), A0 = R6.H * R7.H;
 187         R6 = A0.w;
 188         R7 = A1.w;
 189         CHECKREG r0, 0x456FC8D0;
 190         CHECKREG r1, 0x07B68CC4;
 191         CHECKREG r2, 0x3F0A98CC;
 192         CHECKREG r3, 0x231CADD0;
 193         CHECKREG r4, 0x0C381FC0;
 194         CHECKREG r5, 0x061C0FE0;
 195         CHECKREG r6, 0x2E832052;
 196         CHECKREG r7, 0xEC805DA5;
 197
 198 // test the MNOP  default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1
 199         imm32 r0, 0x123c5678;
 200         imm32 r1, 0x2345c789;
 201         imm32 r2, 0x34567c9a;
 202         imm32 r3, 0x456789c2;
 203         imm32 r4, 0xc678912c;
 204         imm32 r5, 0x6c891234;
 205         imm32 r6, 0xa1c34567;
 206         imm32 r7, 0xc12c4567;
 207
 208         A0 = 0;
 209         A1 = 0;
 210
 211         A1 += R0.L * R1.L (M);
 212         R0 = A0.w;
 213         R1 = A1.w;
 214         A0 += R2.H * R3.H;
 215         R2 = A0.w;
 216         R3 = A1.w;
 217         A1 = R4.L * R5.H (M);
 218         R4 = A0.w;
 219         R5 = A1.w;
 220         A0 += R6.L * R7.H;
 221         R6 = A0.w;
 222         R7 = A1.w;
 223         CHECKREG r0, 0x00000000;
 224         CHECKREG r1, 0x43658E38;
 225         CHECKREG r2, 0x1C607934;
 226         CHECKREG r3, 0x43658E38;
 227         CHECKREG r4, 0x1C607934;
 228         CHECKREG r5, 0xD103408C;
 229         CHECKREG r6, 0xFA4FA29C;
 230         CHECKREG r7, 0xD103408C;
 231
 232         imm32 r0, 0xd2345678;
 233         imm32 r1, 0x2d456789;
 234         imm32 r2, 0x34d6789a;
 235         imm32 r3, 0x456d8912;
 236         imm32 r4, 0x5678d123;
 237         imm32 r5, 0x67891d34;
 238         imm32 r6, 0xa12345d7;
 239         imm32 r7, 0xc123456d;
 240         A0 = R6.H * R7.L;
 241         R6 = A0.w;
 242         R7 = A1.w;
 243         A1 = R4.L * R5.H (M);
 244         R4 = A0.w;
 245         R5 = A1.w;
 246         A0 = R2.L * R3.L;
 247         R2 = A0.w;
 248         R3 = A1.w;
 249         A1 += R0.H * R1.L (M);
 250         R0 = A0.w;
 251         R1 = A1.w;
 252         CHECKREG r0, 0x8FF1C9A8;
 253         CHECKREG r1, 0xDA866A8F;
 254         CHECKREG r2, 0x8FF1C9A8;
 255         CHECKREG r3, 0xED0C00BB;
 256         CHECKREG r4, 0xCC8C15CE;
 257         CHECKREG r5, 0xED0C00BB;
 258         CHECKREG r6, 0xCC8C15CE;
 259         CHECKREG r7, 0xD103408C;
 260
 261         imm32 r0, 0x123c5678;
 262         imm32 r1, 0x2345c789;
 263         imm32 r2, 0x34567c9a;
 264         imm32 r3, 0x456789c2;
 265         imm32 r4, 0xc678912c;
 266         imm32 r5, 0x6c891234;
 267         imm32 r6, 0xa1c34567;
 268         imm32 r7, 0xc12c4567;
 269
 270         A0 = 0;
 271         A1 = 0;
 272
 273         A1 -= R0.L * R1.L (M);
 274         R0 = A0.w;
 275         R1 = A1.w;
 276         A0 -= R2.H * R3.H;
 277         R2 = A0.w;
 278         R3 = A1.w;
 279         A1 -= R4.L * R5.H (M);
 280         R4 = A0.w;
 281         R5 = A1.w;
 282         A0 -= R6.L * R7.H;
 283         R6 = A0.w;
 284         R7 = A1.w;
 285         CHECKREG r0, 0x00000000;
 286         CHECKREG r1, 0xBC9A71C8;
 287         CHECKREG r2, 0xE39F86CC;
 288         CHECKREG r3, 0xBC9A71C8;
 289         CHECKREG r4, 0xE39F86CC;
 290         CHECKREG r5, 0xEB97313C;
 291         CHECKREG r6, 0x05B05D64;
 292         CHECKREG r7, 0xEB97313C;
 293
 294         imm32 r0, 0xd2345678;
 295         imm32 r1, 0x2d456789;
 296         imm32 r2, 0x34d6789a;
 297         imm32 r3, 0x456d8912;
 298         imm32 r4, 0x5678d123;
 299         imm32 r5, 0x67891d34;
 300         imm32 r6, 0xa12345d7;
 301         imm32 r7, 0xc123456d;
 302         A0 -= R6.H * R7.L;
 303         R6 = A0.w;
 304         R7 = A1.w;
 305         A1 -= R4.L * R5.H (M);
 306         R4 = A0.w;
 307         R5 = A1.w;
 308         A0 -= R2.L * R3.L;
 309         R2 = A0.w;
 310         R3 = A1.w;
 311         A1 -= R0.H * R1.L (M);
 312         R0 = A0.w;
 313         R1 = A1.w;
 314         CHECKREG r0, 0xA9327DEE;
 315         CHECKREG r1, 0x1110C6AD;
 316         CHECKREG r2, 0xA9327DEE;
 317         CHECKREG r3, 0xFE8B3081;
 318         CHECKREG r4, 0x39244796;
 319         CHECKREG r5, 0xFE8B3081;
 320         CHECKREG r6, 0x39244796;
 321         CHECKREG r7, 0xEB97313C;
 322
 323         pass
 324
 325         .data
 326 DATA0:
 327         .dd 0x000a0000
 328         .dd 0x000b0001
 329         .dd 0x000c0002
 330         .dd 0x000d0003
 331         .dd 0x000e0004
 332         .dd 0x000f0005
 333
 334 DATA1:
 335         .dd 0x00f00100
 336         .dd 0x00e00101
 337         .dd 0x00d00102
 338         .dd 0x00c00103
 339         .dd 0x00b00104
 340         .dd 0x00a00105