sim/testsuite/sim/bfin/c_dsp32alu_rpm.s

   1 //Original:/testcases/core/c_dsp32alu_rpm/c_dsp32alu_rpm.dsp
   2 // Spec Reference: dsp32alu dreg = +/- ( dreg, dreg)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 // ALU operations include parallel addition, subtraction
  12 // and 32-bit data. If an operation use a single ALU only, it uses ALU0.
  13
  14 imm32 r0, 0x65678911;
  15 imm32 r1, 0x2789ab1d;
  16 imm32 r2, 0x34845515;
  17 imm32 r3, 0x46697717;
  18 imm32 r4, 0x5567191b;
  19 imm32 r5, 0x6789a31d;
  20 imm32 r6, 0x74445545;
  21 imm32 r7, 0x86667779;
  22 R0 = R0 +|- R0;
  23 R1 = R0 +|- R1;
  24 R2 = R0 +|- R2;
  25 R3 = R0 +|- R3;
  26 R4 = R0 +|- R4;
  27 R5 = R0 +|- R5;
  28 R6 = R0 +|- R6;
  29 R7 = R0 +|- R7;
  30 CHECKREG r0, 0xCACE0000;
  31 CHECKREG r1, 0xF25754E3;
  32 CHECKREG r2, 0xFF52AAEB;
  33 CHECKREG r3, 0x113788E9;
  34 CHECKREG r4, 0x2035E6E5;
  35 CHECKREG r5, 0x32575CE3;
  36 CHECKREG r6, 0x3F12AABB;
  37 CHECKREG r7, 0x51348887;
  38
  39 imm32 r0, 0x9567892b;
  40 imm32 r1, 0xa789ab2d;
  41 imm32 r2, 0xb4445525;
  42 imm32 r3, 0xc6667727;
  43 imm32 r4, 0xd8889929;
  44 imm32 r5, 0xeaaabb2b;
  45 imm32 r6, 0xfcccdd2d;
  46 imm32 r7, 0x0eeeffff;
  47 R0 = R1 +|- R0;
  48 R1 = R1 +|- R1;
  49 R2 = R1 +|- R2;
  50 R3 = R1 +|- R3;
  51 R4 = R1 +|- R4;
  52 R5 = R1 +|- R5;
  53 R6 = R1 +|- R6;
  54 R7 = R1 +|- R7;
  55 CHECKREG r0, 0x3CF02202;
  56 CHECKREG r1, 0x4F120000;
  57 CHECKREG r2, 0x0356AADB;
  58 CHECKREG r3, 0x157888D9;
  59 CHECKREG r4, 0x279A66D7;
  60 CHECKREG r5, 0x39BC44D5;
  61 CHECKREG r6, 0x4BDE22D3;
  62 CHECKREG r7, 0x5E000001;
  63
  64 imm32 r0, 0x416789ab;
  65 imm32 r1, 0x6289abcd;
  66 imm32 r2, 0x43445555;
  67 imm32 r3, 0x64667777;
  68 imm32 r4, 0x456789ab;
  69 imm32 r5, 0x6689abcd;
  70 imm32 r6, 0x47445555;
  71 imm32 r7, 0x68667777;
  72 R0 = R2 +|- R0;
  73 R1 = R2 +|- R1;
  74 R2 = R2 +|- R2;
  75 R3 = R2 +|- R3;
  76 R4 = R2 +|- R4;
  77 R5 = R2 +|- R5;
  78 R6 = R2 +|- R6;
  79 R7 = R2 +|- R7;
  80 CHECKREG r0, 0x84ABCBAA;
  81 CHECKREG r1, 0xA5CDA988;
  82 CHECKREG r2, 0x86880000;
  83 CHECKREG r3, 0xEAEE8889;
  84 CHECKREG r4, 0xCBEF7655;
  85 CHECKREG r5, 0xED115433;
  86 CHECKREG r6, 0xCDCCAAAB;
  87 CHECKREG r7, 0xEEEE8889;
  88
  89 imm32 r0, 0xa567892b;
  90 imm32 r1, 0xaa89ab2d;
  91 imm32 r2, 0xb4445525;
  92 imm32 r3, 0xc6a67727;
  93 imm32 r0, 0x9a67892b;
  94 imm32 r1, 0xa7a9ab2d;
  95 imm32 r2, 0xb44a5525;
  96 imm32 r3, 0xc666a727;
  97 R0 = R3 +|- R0;
  98 R1 = R3 +|- R1;
  99 R2 = R3 +|- R2;
 100 R3 = R3 +|- R3;
 101 R4 = R3 +|- R4;
 102 R5 = R3 +|- R5;
 103 R6 = R3 +|- R6;
 104 R7 = R3 +|- R7;
 105 CHECKREG r0, 0x60CD1DFC;
 106 CHECKREG r1, 0x6E0FFBFA;
 107 CHECKREG r2, 0x7AB05202;
 108 CHECKREG r3, 0x8CCC0000;
 109 CHECKREG r4, 0x58BB89AB;
 110 CHECKREG r5, 0x79DDABCD;
 111 CHECKREG r6, 0x5A985555;
 112 CHECKREG r7, 0x7BBA7777;
 113
 114 imm32 r0, 0x4537891b;
 115 imm32 r1, 0x6759ab2d;
 116 imm32 r2, 0x44555535;
 117 imm32 r3, 0x66665747;
 118 imm32 r4, 0x88789565;
 119 imm32 r5, 0xaa8abb5b;
 120 imm32 r6, 0xcc9cdd85;
 121 imm32 r7, 0xeeaeff9f;
 122 R0 = R4 +|- R0;
 123 R1 = R4 +|- R1;
 124 R2 = R4 +|- R2;
 125 R3 = R4 +|- R3;
 126 R4 = R4 +|- R4;
 127 R5 = R4 +|- R5;
 128 R6 = R4 +|- R6;
 129 R7 = R4 +|- R7;
 130 CHECKREG r0, 0xCDAF0C4A;
 131 CHECKREG r1, 0xEFD1EA38;
 132 CHECKREG r2, 0xCCCD4030;
 133 CHECKREG r3, 0xEEDE3E1E;
 134 CHECKREG r4, 0x10F00000;
 135 CHECKREG r5, 0xBB7A44A5;
 136 CHECKREG r6, 0xDD8C227B;
 137 CHECKREG r7, 0xFF9E0061;
 138
 139 imm32 r0, 0x456b89ab;
 140 imm32 r1, 0x69764bcd;
 141 imm32 r2, 0x49736564;
 142 imm32 r3, 0x61278394;
 143 imm32 r4, 0x98876439;
 144 imm32 r5, 0xaaaa0bbb;
 145 imm32 r6, 0xcccc1ddd;
 146 imm32 r7, 0x12346fff;
 147 R0 = R5 +|- R0;
 148 R1 = R5 +|- R1;
 149 R2 = R5 +|- R2;
 150 R3 = R5 +|- R3;
 151 R4 = R5 +|- R4;
 152 R5 = R5 +|- R5;
 153 R6 = R5 +|- R6;
 154 R7 = R5 +|- R7;
 155 CHECKREG r0, 0xF0158210;
 156 CHECKREG r1, 0x1420BFEE;
 157 CHECKREG r2, 0xF41DA657;
 158 CHECKREG r3, 0x0BD18827;
 159 CHECKREG r4, 0x4331A782;
 160 CHECKREG r5, 0x55540000;
 161 CHECKREG r6, 0x2220E223;
 162 CHECKREG r7, 0x67889001;
 163
 164 imm32 r0, 0x456739ab;
 165 imm32 r1, 0x67694bcd;
 166 imm32 r2, 0x03456755;
 167 imm32 r3, 0x66666777;
 168 imm32 r4, 0x12345699;
 169 imm32 r5, 0x45678b6b;
 170 imm32 r6, 0x043290d6;
 171 imm32 r7, 0x1234567f;
 172 R0 = R6 +|- R0;
 173 R1 = R6 +|- R1;
 174 R2 = R6 +|- R2;
 175 R3 = R6 +|- R3;
 176 R4 = R6 +|- R4;
 177 R5 = R6 +|- R5;
 178 R6 = R6 +|- R6;
 179 R7 = R6 +|- R7;
 180 CHECKREG r0, 0x4999572B;
 181 CHECKREG r1, 0x6B9B4509;
 182 CHECKREG r2, 0x07772981;
 183 CHECKREG r3, 0x6A98295F;
 184 CHECKREG r4, 0x16663A3D;
 185 CHECKREG r5, 0x4999056B;
 186 CHECKREG r6, 0x08640000;
 187 CHECKREG r7, 0x1A98A981;
 188
 189 imm32 r0, 0xb76789ab;
 190 imm32 r1, 0x6779abcd;
 191 imm32 r2, 0x2b456755;
 192 imm32 r3, 0x56789007;
 193 imm32 r4, 0x78bab799;
 194 imm32 r5, 0xaaaa0bbb;
 195 imm32 r6, 0x89ab1d7d;
 196 imm32 r7, 0xabcdbff7;
 197 R0 = R7 +|- R0;
 198 R1 = R7 +|- R1;
 199 R2 = R7 +|- R2;
 200 R3 = R7 +|- R3;
 201 R4 = R7 +|- R4;
 202 R5 = R7 +|- R5;
 203 R6 = R7 +|- R6;
 204 R7 = R7 +|- R7;
 205 CHECKREG r0, 0x6334364C;
 206 CHECKREG r1, 0x1346142A;
 207 CHECKREG r2, 0xD71258A2;
 208 CHECKREG r3, 0x02452FF0;
 209 CHECKREG r4, 0x2487085E;
 210 CHECKREG r5, 0x5677B43C;
 211 CHECKREG r6, 0x3578A27A;
 212 CHECKREG r7, 0x579A0000;
 213 imm32 r0, 0x456739ab;
 214 imm32 r1, 0x67694bcd;
 215 imm32 r2, 0x03456755;
 216 imm32 r3, 0x66666777;
 217 imm32 r4, 0x12345699;
 218 imm32 r5, 0x45678b6b;
 219 imm32 r6, 0x043290d6;
 220 imm32 r7, 0x1234567f;
 221 R4 = R4 +|- R7 (S);
 222 R5 = R5 +|- R5 (CO);
 223 R2 = R6 +|- R3 (SCO);
 224 R6 = R0 +|- R4 (S);
 225 R0 = R1 +|- R6 (S);
 226 R2 = R2 +|- R1 (CO);
 227 R1 = R3 +|- R0 (CO);
 228 R7 = R7 +|- R4 (SCO);
 229 CHECKREG r0, 0x7FFF123C;
 230 CHECKREG r1, 0x553BE665;
 231 CHECKREG r2, 0x1ECBE769;
 232 CHECKREG r3, 0x66666777;
 233 CHECKREG r4, 0x2468001A;
 234 CHECKREG r5, 0x00008ACE;
 235 CHECKREG r6, 0x69CF3991;
 236 CHECKREG r7, 0x5665369C;
 237
 238 imm32 r0, 0xb76789ab;
 239 imm32 r1, 0x6b79abcd;
 240 imm32 r2, 0x2b456755;
 241 imm32 r3, 0x56b89007;
 242 imm32 r4, 0x78bab799;
 243 imm32 r5, 0xaaab0bbb;
 244 imm32 r6, 0x89abbd7d;
 245 imm32 r7, 0xabcd2bf7;
 246 R3 = R4 +|- R0 (S);
 247 R5 = R5 +|- R1 (SCO);
 248 R2 = R2 +|- R2 (S);
 249 R7 = R7 +|- R3 (CO);
 250 R4 = R3 +|- R4 (CO);
 251 R0 = R1 +|- R5 (S);
 252 R1 = R0 +|- R6 (SCO);
 253 R6 = R6 +|- R7 (SCO);
 254 CHECKREG r0, 0x7FFF95A9;
 255 CHECKREG r1, 0xD82C09AA;
 256 CHECKREG r2, 0x568A0000;
 257 CHECKREG r3, 0x30212DEE;
 258 CHECKREG r4, 0x7655A8DB;
 259 CHECKREG r5, 0x5FEE1624;
 260 CHECKREG r6, 0xE18F87B4;
 261 CHECKREG r7, 0xFE09DBEE;
 262
 263
 264 pass