sim/testsuite/sim/bfin/c_dsp32alu_rlh_rnd.s

   1 //Original:/testcases/core/c_dsp32alu_rlh_rnd/c_dsp32alu_rlh_rnd.dsp
   2 // Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 imm32 r0, 0x4537891b;
  12 imm32 r1, 0x6759ab2d;
  13 imm32 r2, 0x44555535;
  14 imm32 r3, 0x66665747;
  15 imm32 r4, 0x88789565;
  16 imm32 r5, 0xaa8abb5b;
  17 imm32 r6, 0xcc9cdd85;
  18 imm32 r7, 0xeeaeff9f;
  19 R0.L = R1 (RND);
  20 R0.H = R2 (RND);
  21 R1.L = R3 (RND);
  22 R1.H = R4 (RND);
  23 R2.L = R5 (RND);
  24 R2.H = R6 (RND);
  25 CHECKREG r0, 0x4455675A;
  26 CHECKREG r1, 0x88796666;
  27 CHECKREG r2, 0xCC9DAA8B;
  28
  29
  30 imm32 r0, 0xe537891b;
  31 imm32 r1, 0xf759ab2d;
  32 imm32 r2, 0x4ef55535;
  33 imm32 r3, 0x666b5747;
  34 imm32 r4, 0xc8789565;
  35 imm32 r5, 0xaa8abb5b;
  36 imm32 r6, 0x8c9cdd85;
  37 imm32 r7, 0x9eaeff9f;
  38 R3.L = R0 (RND);
  39 R3.H = R1 (RND);
  40 R4.L = R2 (RND);
  41 R4.H = R5 (RND);
  42 R5.L = R6 (RND);
  43 R5.H = R7 (RND);
  44 CHECKREG r3, 0xF75AE538;
  45 CHECKREG r4, 0xAA8B4EF5;
  46 CHECKREG r5, 0x9EAF8C9D;
  47
  48 imm32 r0, 0x5537891b;
  49 imm32 r1, 0x6759ab2d;
  50 imm32 r2, 0x8ef55535;
  51 imm32 r3, 0x666b5747;
  52 imm32 r4, 0xc8789565;
  53 imm32 r5, 0xea8abb5b;
  54 imm32 r6, 0xfc9cdd85;
  55 imm32 r7, 0x9eaeff9f;
  56 R6.L = R0 (RND);
  57 R6.H = R1 (RND);
  58 R7.L = R2 (RND);
  59 R7.H = R3 (RND);
  60 R5.L = R4 (RND);
  61 R5.H = R5 (RND);
  62 CHECKREG r5, 0xEA8BC879;
  63 CHECKREG r6, 0x675A5538;
  64 CHECKREG r7, 0x666B8EF5;
  65
  66 pass