sim/testsuite/sim/bfin/c_alu2op_divq.s

   1 //Original:/testcases/core/c_alu2op_divq/c_alu2op_divq.dsp
   2 // Spec Reference: alu2op divide q
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 imm32 r0, 0x00000000;
  11 imm32 r1, 0x12345678;
  12 imm32 r2, 0x23456789;
  13 imm32 r3, 0x3456789a;
  14 imm32 r4, 0x856789ab;
  15 imm32 r5, 0x96789abc;
  16 imm32 r6, 0xa789abcd;
  17 imm32 r7, 0xb89abcde;
  18 R0.L = 1;
  19 DIVQ ( R1 , R0 );
  20 DIVQ ( R2 , R0 );
  21 DIVQ ( R3 , R0 );
  22 DIVQ ( R4 , R0 );
  23 DIVQ ( R5 , R0 );
  24 DIVQ ( R6 , R0 );
  25 DIVQ ( R7 , R0 );
  26 DIVQ ( R4 , R0 );
  27 DIVQ ( R0 , R0 );
  28 CHECKREG r1, 0x2466ACF1;
  29 CHECKREG r2, 0x4688CF13;
  30 CHECKREG r3, 0x68AAF135;
  31 CHECKREG r4, 0x159C26AD;
  32 CHECKREG r5, 0x2CF33578;
  33 CHECKREG r6, 0x4F15579A;
  34 CHECKREG r7, 0x713779BC;
  35 CHECKREG r0, 0xFFFE0002;
  36
  37 imm32 r0, 0x01230002;
  38 imm32 r1, 0x00000000;
  39 imm32 r2, 0x93456789;
  40 imm32 r3, 0xa456789a;
  41 imm32 r4, 0xb56789ab;
  42 imm32 r5, 0xc6789abc;
  43 imm32 r6, 0xd789abcd;
  44 imm32 r7, 0xe89abcde;
  45 R1.L = -1;
  46 DIVQ ( R0 , R1 );
  47 DIVQ ( R2 , R1 );
  48 DIVQ ( R3 , R1 );
  49 DIVQ ( R4 , R1 );
  50 DIVQ ( R5 , R1 );
  51 DIVQ ( R6 , R1 );
  52 DIVQ ( R7 , R1 );
  53 DIVQ ( R1 , R1 );
  54 CHECKREG r0, 0x02440004;
  55 CHECKREG r1, 0x0003FFFE;
  56 CHECKREG r2, 0x2688CF13;
  57 CHECKREG r3, 0x48AEF135;
  58 CHECKREG r4, 0x6AD11357;
  59 CHECKREG r5, 0x8CF33579;
  60 CHECKREG r6, 0xAF15579B;
  61 CHECKREG r7, 0xD13779BD;
  62
  63 imm32 r0, 0x51230002;
  64 imm32 r1, 0x12345678;
  65 imm32 r2, 0x00000000;
  66 imm32 r3, 0x3456789a;
  67 imm32 r4, 0x956789ab;
  68 imm32 r5, 0x86789abc;
  69 imm32 r6, 0x6789abcd;
  70 imm32 r7, 0x789abcde;
  71 R2.L = 31;
  72 DIVQ ( R0 , R2 );
  73 DIVQ ( R1 , R2 );
  74 DIVQ ( R3 , R2 );
  75 DIVQ ( R4 , R2 );
  76 DIVQ ( R5 , R2 );
  77 DIVQ ( R6 , R2 );
  78 DIVQ ( R7 , R2 );
  79 DIVQ ( R2 , R2 );
  80 CHECKREG r0, 0xA2840005;
  81 CHECKREG r1, 0x242AACF1;
  82 CHECKREG r2, 0xFFC2003E;
  83 CHECKREG r3, 0x686EF135;
  84 CHECKREG r4, 0x2A911356;
  85 CHECKREG r5, 0x0D2F3578;
  86 CHECKREG r6, 0xCF51579B;
  87 CHECKREG r7, 0xF0F779BD;
  88
  89 imm32 r0, 0x01230002;
  90 imm32 r1, 0x82345678;
  91 imm32 r2, 0x93456789;
  92 imm32 r3, 0x00000000;
  93 imm32 r4, 0xb56789ab;
  94 imm32 r5, 0xc6789abc;
  95 imm32 r6, 0xd789abcd;
  96 imm32 r7, 0xe89abcde;
  97 R3.L = -31;
  98 DIVQ ( R0 , R3 );
  99 DIVQ ( R1 , R3 );
 100 DIVQ ( R2 , R3 );
 101 DIVQ ( R4 , R3 );
 102 DIVQ ( R5 , R3 );
 103 DIVQ ( R6 , R3 );
 104 DIVQ ( R7 , R3 );
 105 DIVQ ( R3 , R3 );
 106 CHECKREG r0, 0x02080004;
 107 CHECKREG r1, 0x042AACF1;
 108 CHECKREG r2, 0x26C8CF13;
 109 CHECKREG r3, 0x003FFFC2;
 110 CHECKREG r4, 0x6B0D1357;
 111 CHECKREG r5, 0x8D2F3579;
 112 CHECKREG r6, 0xAF51579B;
 113 CHECKREG r7, 0xD17379BD;
 114
 115 imm32 r0, 0x00000001;
 116 imm32 r1, 0x12345678;
 117 imm32 r2, 0x23456789;
 118 imm32 r3, 0x3456789a;
 119 imm32 r4, 0x00000000;
 120 imm32 r5, 0x96789abc;
 121 imm32 r6, 0xa789abcd;
 122 imm32 r7, 0xb89abcde;
 123 R4.L = 15;
 124 DIVQ ( R1 , R4 );
 125 DIVQ ( R2 , R4 );
 126 DIVQ ( R3 , R4 );
 127 DIVQ ( R0 , R4 );
 128 DIVQ ( R5 , R4 );
 129 DIVQ ( R6 , R4 );
 130 DIVQ ( R7 , R4 );
 131 DIVQ ( R4 , R4 );
 132 CHECKREG r0, 0xFFE20002;
 133 CHECKREG r1, 0x2486ACF1;
 134 CHECKREG r2, 0x466CCF13;
 135 CHECKREG r3, 0x688EF135;
 136 CHECKREG r4, 0x001E001F;
 137 CHECKREG r5, 0x2D0F3578;
 138 CHECKREG r6, 0x4F31579A;
 139 CHECKREG r7, 0x715379BC;
 140
 141 imm32 r0, 0x01230002;
 142 imm32 r1, 0x00000000;
 143 imm32 r2, 0x93456789;
 144 imm32 r3, 0xa456789a;
 145 imm32 r4, 0xb56789ab;
 146 imm32 r5, 0x00000000;
 147 imm32 r6, 0xd789abcd;
 148 imm32 r7, 0xe89abcde;
 149 R5.L = -15;
 150 DIVQ ( R0 , R5 );
 151 DIVQ ( R1 , R5 );
 152 DIVQ ( R2 , R5 );
 153 DIVQ ( R3 , R5 );
 154 DIVQ ( R4 , R5 );
 155 DIVQ ( R6 , R5 );
 156 DIVQ ( R7 , R5 );
 157 DIVQ ( R5 , R5 );
 158 CHECKREG r0, 0x02640004;
 159 CHECKREG r1, 0xFFE20001;
 160 CHECKREG r2, 0x26A8CF13;
 161 CHECKREG r3, 0x48CAF135;
 162 CHECKREG r4, 0x6AED1357;
 163 CHECKREG r5, 0x001FFFE2;
 164 CHECKREG r6, 0xAF31579B;
 165 CHECKREG r7, 0xD15379BD;
 166
 167 imm32 r0, 0x51230002;
 168 imm32 r1, 0x12345678;
 169 imm32 r2, 0xb1256790;
 170 imm32 r3, 0x3456789a;
 171 imm32 r4, 0x956789ab;
 172 imm32 r5, 0x86789abc;
 173 imm32 r6, 0x00000000;
 174 imm32 r7, 0x789abcde;
 175 R6.L = 24;
 176 DIVQ ( R0 , R6 );
 177 DIVQ ( R1 , R6 );
 178 DIVQ ( R2 , R6 );
 179 DIVQ ( R3 , R6 );
 180 DIVQ ( R4 , R6 );
 181 DIVQ ( R5 , R6 );
 182 DIVQ ( R7 , R6 );
 183 DIVQ ( R6 , R6 );
 184 CHECKREG r0, 0xA2760005;
 185 CHECKREG r1, 0x2438ACF1;
 186 CHECKREG r2, 0x621ACF20;
 187 CHECKREG r3, 0x68DCF135;
 188 CHECKREG r4, 0x2A9F1356;
 189 CHECKREG r5, 0x0D213578;
 190 CHECKREG r6, 0xFFD00030;
 191 CHECKREG r7, 0xF16579BD;
 192
 193 imm32 r0, 0x01230002;
 194 imm32 r1, 0x82345678;
 195 imm32 r2, 0x93456789;
 196 imm32 r3, 0xa456789a;
 197 imm32 r4, 0xb56789ab;
 198 imm32 r5, 0xc6789abc;
 199 imm32 r6, 0xd789abcd;
 200 imm32 r7, 0x00000000;
 201 R7.L = -24;
 202 DIVQ ( R0 , R7 );
 203 DIVQ ( R1 , R7 );
 204 DIVQ ( R2 , R7 );
 205 DIVQ ( R3 , R7 );
 206 DIVQ ( R4 , R7 );
 207 DIVQ ( R5 , R7 );
 208 DIVQ ( R6 , R7 );
 209 DIVQ ( R7 , R7 );
 210 CHECKREG r0, 0x02160004;
 211 CHECKREG r1, 0x0438ACF1;
 212 CHECKREG r2, 0x26BACF13;
 213 CHECKREG r3, 0x48DCF135;
 214 CHECKREG r4, 0x6AFF1357;
 215 CHECKREG r5, 0x8D213579;
 216 CHECKREG r6, 0xAF43579B;
 217 CHECKREG r7, 0x0031FFD0;
 218
 219
 220 pass