1 /* Decode header for sparc64.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1999 Cygnus Solutions, Inc.
7 This file is part of the Cygnus Simulators.
12 #ifndef SPARC64_DECODE_H
13 #define SPARC64_DECODE_H
15 extern const IDESC *sparc64_decode (SIM_CPU *, IADDR,
16 CGEN_INSN_INT, CGEN_INSN_INT,
18 extern void sparc64_init_idesc_table (SIM_CPU *);
20 /* Enum declaration for instructions in cpu family sparc64. */
21 typedef enum sparc64_insn_type {
22 SPARC64_INSN_X_INVALID, SPARC64_INSN_X_AFTER, SPARC64_INSN_X_BEFORE, SPARC64_INSN_X_CTI_CHAIN
23 , SPARC64_INSN_X_CHAIN, SPARC64_INSN_X_BEGIN, SPARC64_INSN_BEQZ, SPARC64_INSN_BGEZ
24 , SPARC64_INSN_BGTZ, SPARC64_INSN_BLEZ, SPARC64_INSN_BLTZ, SPARC64_INSN_BNEZ
25 , SPARC64_INSN_BPCC_BA, SPARC64_INSN_BPCC_BN, SPARC64_INSN_BPCC_BNE, SPARC64_INSN_BPCC_BE
26 , SPARC64_INSN_BPCC_BG, SPARC64_INSN_BPCC_BLE, SPARC64_INSN_BPCC_BGE, SPARC64_INSN_BPCC_BL
27 , SPARC64_INSN_BPCC_BGU, SPARC64_INSN_BPCC_BLEU, SPARC64_INSN_BPCC_BCC, SPARC64_INSN_BPCC_BCS
28 , SPARC64_INSN_BPCC_BPOS, SPARC64_INSN_BPCC_BNEG, SPARC64_INSN_BPCC_BVC, SPARC64_INSN_BPCC_BVS
29 , SPARC64_INSN_DONE, SPARC64_INSN_RETRY, SPARC64_INSN_FLUSH, SPARC64_INSN_FLUSH_IMM
30 , SPARC64_INSN_FLUSHW, SPARC64_INSN_IMPDEP1, SPARC64_INSN_IMPDEP2, SPARC64_INSN_MEMBAR
31 , SPARC64_INSN_MOVA_ICC_ICC, SPARC64_INSN_MOVA_IMM_ICC_ICC, SPARC64_INSN_MOVA_XCC_XCC, SPARC64_INSN_MOVA_IMM_XCC_XCC
32 , SPARC64_INSN_MOVN_ICC_ICC, SPARC64_INSN_MOVN_IMM_ICC_ICC, SPARC64_INSN_MOVN_XCC_XCC, SPARC64_INSN_MOVN_IMM_XCC_XCC
33 , SPARC64_INSN_MOVNE_ICC_ICC, SPARC64_INSN_MOVNE_IMM_ICC_ICC, SPARC64_INSN_MOVNE_XCC_XCC, SPARC64_INSN_MOVNE_IMM_XCC_XCC
34 , SPARC64_INSN_MOVE_ICC_ICC, SPARC64_INSN_MOVE_IMM_ICC_ICC, SPARC64_INSN_MOVE_XCC_XCC, SPARC64_INSN_MOVE_IMM_XCC_XCC
35 , SPARC64_INSN_MOVG_ICC_ICC, SPARC64_INSN_MOVG_IMM_ICC_ICC, SPARC64_INSN_MOVG_XCC_XCC, SPARC64_INSN_MOVG_IMM_XCC_XCC
36 , SPARC64_INSN_MOVLE_ICC_ICC, SPARC64_INSN_MOVLE_IMM_ICC_ICC, SPARC64_INSN_MOVLE_XCC_XCC, SPARC64_INSN_MOVLE_IMM_XCC_XCC
37 , SPARC64_INSN_MOVGE_ICC_ICC, SPARC64_INSN_MOVGE_IMM_ICC_ICC, SPARC64_INSN_MOVGE_XCC_XCC, SPARC64_INSN_MOVGE_IMM_XCC_XCC
38 , SPARC64_INSN_MOVL_ICC_ICC, SPARC64_INSN_MOVL_IMM_ICC_ICC, SPARC64_INSN_MOVL_XCC_XCC, SPARC64_INSN_MOVL_IMM_XCC_XCC
39 , SPARC64_INSN_MOVGU_ICC_ICC, SPARC64_INSN_MOVGU_IMM_ICC_ICC, SPARC64_INSN_MOVGU_XCC_XCC, SPARC64_INSN_MOVGU_IMM_XCC_XCC
40 , SPARC64_INSN_MOVLEU_ICC_ICC, SPARC64_INSN_MOVLEU_IMM_ICC_ICC, SPARC64_INSN_MOVLEU_XCC_XCC, SPARC64_INSN_MOVLEU_IMM_XCC_XCC
41 , SPARC64_INSN_MOVCC_ICC_ICC, SPARC64_INSN_MOVCC_IMM_ICC_ICC, SPARC64_INSN_MOVCC_XCC_XCC, SPARC64_INSN_MOVCC_IMM_XCC_XCC
42 , SPARC64_INSN_MOVCS_ICC_ICC, SPARC64_INSN_MOVCS_IMM_ICC_ICC, SPARC64_INSN_MOVCS_XCC_XCC, SPARC64_INSN_MOVCS_IMM_XCC_XCC
43 , SPARC64_INSN_MOVPOS_ICC_ICC, SPARC64_INSN_MOVPOS_IMM_ICC_ICC, SPARC64_INSN_MOVPOS_XCC_XCC, SPARC64_INSN_MOVPOS_IMM_XCC_XCC
44 , SPARC64_INSN_MOVNEG_ICC_ICC, SPARC64_INSN_MOVNEG_IMM_ICC_ICC, SPARC64_INSN_MOVNEG_XCC_XCC, SPARC64_INSN_MOVNEG_IMM_XCC_XCC
45 , SPARC64_INSN_MOVVC_ICC_ICC, SPARC64_INSN_MOVVC_IMM_ICC_ICC, SPARC64_INSN_MOVVC_XCC_XCC, SPARC64_INSN_MOVVC_IMM_XCC_XCC
46 , SPARC64_INSN_MOVVS_ICC_ICC, SPARC64_INSN_MOVVS_IMM_ICC_ICC, SPARC64_INSN_MOVVS_XCC_XCC, SPARC64_INSN_MOVVS_IMM_XCC_XCC
47 , SPARC64_INSN_LDSB_REG_REG, SPARC64_INSN_LDSB_REG_IMM, SPARC64_INSN_LDSB_REG_REG_ASI, SPARC64_INSN_LDUB_REG_REG
48 , SPARC64_INSN_LDUB_REG_IMM, SPARC64_INSN_LDUB_REG_REG_ASI, SPARC64_INSN_LDSH_REG_REG, SPARC64_INSN_LDSH_REG_IMM
49 , SPARC64_INSN_LDSH_REG_REG_ASI, SPARC64_INSN_LDUH_REG_REG, SPARC64_INSN_LDUH_REG_IMM, SPARC64_INSN_LDUH_REG_REG_ASI
50 , SPARC64_INSN_LDSW_REG_REG, SPARC64_INSN_LDSW_REG_IMM, SPARC64_INSN_LDSW_REG_REG_ASI, SPARC64_INSN_LDUW_REG_REG
51 , SPARC64_INSN_LDUW_REG_IMM, SPARC64_INSN_LDUW_REG_REG_ASI, SPARC64_INSN_LDX_REG_REG, SPARC64_INSN_LDX_REG_IMM
52 , SPARC64_INSN_LDX_REG_REG_ASI, SPARC64_INSN_LDD_REG_REG, SPARC64_INSN_LDD_REG_IMM, SPARC64_INSN_LDD_REG_REG_ASI
53 , SPARC64_INSN_STB_REG_REG, SPARC64_INSN_STB_REG_IMM, SPARC64_INSN_STB_REG_REG_ASI, SPARC64_INSN_STH_REG_REG
54 , SPARC64_INSN_STH_REG_IMM, SPARC64_INSN_STH_REG_REG_ASI, SPARC64_INSN_ST_REG_REG, SPARC64_INSN_ST_REG_IMM
55 , SPARC64_INSN_ST_REG_REG_ASI, SPARC64_INSN_STX_REG_REG, SPARC64_INSN_STX_REG_IMM, SPARC64_INSN_STX_REG_REG_ASI
56 , SPARC64_INSN_STD_REG_REG, SPARC64_INSN_STD_REG_IMM, SPARC64_INSN_STD_REG_REG_ASI, SPARC64_INSN_FP_LD_REG_REG
57 , SPARC64_INSN_FP_LD_REG_IMM, SPARC64_INSN_FP_LD_REG_REG_ASI, SPARC64_INSN_SETHI, SPARC64_INSN_ADD
58 , SPARC64_INSN_ADD_IMM, SPARC64_INSN_SUB, SPARC64_INSN_SUB_IMM, SPARC64_INSN_ADDCC
59 , SPARC64_INSN_ADDCC_IMM, SPARC64_INSN_SUBCC, SPARC64_INSN_SUBCC_IMM, SPARC64_INSN_ADDC
60 , SPARC64_INSN_ADDC_IMM, SPARC64_INSN_SUBC, SPARC64_INSN_SUBC_IMM, SPARC64_INSN_ADDCCC
61 , SPARC64_INSN_ADDCCC_IMM, SPARC64_INSN_SUBCCC, SPARC64_INSN_SUBCCC_IMM, SPARC64_INSN_AND
62 , SPARC64_INSN_AND_IMM, SPARC64_INSN_ANDCC, SPARC64_INSN_ANDCC_IMM, SPARC64_INSN_OR
63 , SPARC64_INSN_OR_IMM, SPARC64_INSN_ORCC, SPARC64_INSN_ORCC_IMM, SPARC64_INSN_XOR
64 , SPARC64_INSN_XOR_IMM, SPARC64_INSN_XORCC, SPARC64_INSN_XORCC_IMM, SPARC64_INSN_ANDN
65 , SPARC64_INSN_ANDN_IMM, SPARC64_INSN_ANDNCC, SPARC64_INSN_ANDNCC_IMM, SPARC64_INSN_ORN
66 , SPARC64_INSN_ORN_IMM, SPARC64_INSN_ORNCC, SPARC64_INSN_ORNCC_IMM, SPARC64_INSN_XNOR
67 , SPARC64_INSN_XNOR_IMM, SPARC64_INSN_XNORCC, SPARC64_INSN_XNORCC_IMM, SPARC64_INSN_SLL
68 , SPARC64_INSN_SLL_IMM, SPARC64_INSN_SRL, SPARC64_INSN_SRL_IMM, SPARC64_INSN_SRA
69 , SPARC64_INSN_SRA_IMM, SPARC64_INSN_SMUL, SPARC64_INSN_SMUL_IMM, SPARC64_INSN_SMUL_CC
70 , SPARC64_INSN_SMUL_CC_IMM, SPARC64_INSN_UMUL, SPARC64_INSN_UMUL_IMM, SPARC64_INSN_UMUL_CC
71 , SPARC64_INSN_UMUL_CC_IMM, SPARC64_INSN_MULSCC, SPARC64_INSN_SAVE, SPARC64_INSN_SAVE_IMM
72 , SPARC64_INSN_RESTORE, SPARC64_INSN_RESTORE_IMM, SPARC64_INSN_RETT, SPARC64_INSN_RETT_IMM
73 , SPARC64_INSN_UNIMP, SPARC64_INSN_CALL, SPARC64_INSN_JMPL, SPARC64_INSN_JMPL_IMM
74 , SPARC64_INSN_BA, SPARC64_INSN_TA, SPARC64_INSN_TA_IMM, SPARC64_INSN_BN
75 , SPARC64_INSN_TN, SPARC64_INSN_TN_IMM, SPARC64_INSN_BNE, SPARC64_INSN_TNE
76 , SPARC64_INSN_TNE_IMM, SPARC64_INSN_BE, SPARC64_INSN_TE, SPARC64_INSN_TE_IMM
77 , SPARC64_INSN_BG, SPARC64_INSN_TG, SPARC64_INSN_TG_IMM, SPARC64_INSN_BLE
78 , SPARC64_INSN_TLE, SPARC64_INSN_TLE_IMM, SPARC64_INSN_BGE, SPARC64_INSN_TGE
79 , SPARC64_INSN_TGE_IMM, SPARC64_INSN_BL, SPARC64_INSN_TL, SPARC64_INSN_TL_IMM
80 , SPARC64_INSN_BGU, SPARC64_INSN_TGU, SPARC64_INSN_TGU_IMM, SPARC64_INSN_BLEU
81 , SPARC64_INSN_TLEU, SPARC64_INSN_TLEU_IMM, SPARC64_INSN_BCC, SPARC64_INSN_TCC
82 , SPARC64_INSN_TCC_IMM, SPARC64_INSN_BCS, SPARC64_INSN_TCS, SPARC64_INSN_TCS_IMM
83 , SPARC64_INSN_BPOS, SPARC64_INSN_TPOS, SPARC64_INSN_TPOS_IMM, SPARC64_INSN_BNEG
84 , SPARC64_INSN_TNEG, SPARC64_INSN_TNEG_IMM, SPARC64_INSN_BVC, SPARC64_INSN_TVC
85 , SPARC64_INSN_TVC_IMM, SPARC64_INSN_BVS, SPARC64_INSN_TVS, SPARC64_INSN_TVS_IMM
86 , SPARC64_INSN_LDSTUB_REG_REG, SPARC64_INSN_LDSTUB_REG_IMM, SPARC64_INSN_LDSTUB_REG_REG_ASI, SPARC64_INSN_SWAP_REG_REG
87 , SPARC64_INSN_SWAP_REG_IMM, SPARC64_INSN_SWAP_REG_REG_ASI, SPARC64_INSN_MAX
90 #if ! WITH_SEM_SWITCH_FULL
91 #define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,fn);
96 #if ! WITH_SEM_SWITCH_FAST
97 #define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (sparc64,_semf_,fn);
102 #define SEM(fn) SEMFULL (fn) SEMFAST (fn)
104 /* The function version of the before/after handlers is always needed,
105 so we always want the SEMFULL declaration of them. */
106 extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,x_before);
107 extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,x_after);
146 SEM (mova_imm_icc_icc)
148 SEM (mova_imm_xcc_xcc)
150 SEM (movn_imm_icc_icc)
152 SEM (movn_imm_xcc_xcc)
154 SEM (movne_imm_icc_icc)
156 SEM (movne_imm_xcc_xcc)
158 SEM (move_imm_icc_icc)
160 SEM (move_imm_xcc_xcc)
162 SEM (movg_imm_icc_icc)
164 SEM (movg_imm_xcc_xcc)
166 SEM (movle_imm_icc_icc)
168 SEM (movle_imm_xcc_xcc)
170 SEM (movge_imm_icc_icc)
172 SEM (movge_imm_xcc_xcc)
174 SEM (movl_imm_icc_icc)
176 SEM (movl_imm_xcc_xcc)
178 SEM (movgu_imm_icc_icc)
180 SEM (movgu_imm_xcc_xcc)
182 SEM (movleu_imm_icc_icc)
184 SEM (movleu_imm_xcc_xcc)
186 SEM (movcc_imm_icc_icc)
188 SEM (movcc_imm_xcc_xcc)
190 SEM (movcs_imm_icc_icc)
192 SEM (movcs_imm_xcc_xcc)
194 SEM (movpos_imm_icc_icc)
196 SEM (movpos_imm_xcc_xcc)
198 SEM (movneg_imm_icc_icc)
200 SEM (movneg_imm_xcc_xcc)
202 SEM (movvc_imm_icc_icc)
204 SEM (movvc_imm_xcc_xcc)
206 SEM (movvs_imm_icc_icc)
208 SEM (movvs_imm_xcc_xcc)
211 SEM (ldsb_reg_reg_asi)
214 SEM (ldub_reg_reg_asi)
217 SEM (ldsh_reg_reg_asi)
220 SEM (lduh_reg_reg_asi)
223 SEM (ldsw_reg_reg_asi)
226 SEM (lduw_reg_reg_asi)
229 SEM (ldx_reg_reg_asi)
232 SEM (ldd_reg_reg_asi)
235 SEM (stb_reg_reg_asi)
238 SEM (sth_reg_reg_asi)
244 SEM (stx_reg_reg_asi)
247 SEM (std_reg_reg_asi)
250 SEM (fp_ld_reg_reg_asi)
367 SEM (ldstub_reg_reg_asi)
370 SEM (swap_reg_reg_asi)
376 /* Function unit handlers (user written). */
378 extern int sparc64_model_sparc64_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
380 /* Profiling before/after handlers (user written) */
382 extern void sparc64_model_insn_before (SIM_CPU *, int /*first_p*/);
383 extern void sparc64_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
385 #endif /* SPARC64_DECODE_H */