1 /* SH5 simulator support code
2 Copyright (C) 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
29 #include "gdb/callback.h"
30 #include "defs-compact.h"
33 /* From include/gdb/. */
34 #include "gdb/sim-sh.h"
44 #define SYS_argnlen 173
47 IDESC * sh64_idesc_media;
48 IDESC * sh64_idesc_compact;
51 sh64_endian (SIM_CPU *current_cpu)
53 return (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN);
57 sh64_fldi0 (SIM_CPU *current_cpu)
60 sim_fpu_to32 (&result, &sim_fpu_zero);
65 sh64_fldi1 (SIM_CPU *current_cpu)
68 sim_fpu_to32 (&result, &sim_fpu_one);
73 sh64_fabsd(SIM_CPU *current_cpu, DF drgh)
78 sim_fpu_64to (&f, drgh);
79 sim_fpu_abs (&fres, &f);
80 sim_fpu_to64 (&result, &fres);
85 sh64_fabss(SIM_CPU *current_cpu, SF frgh)
90 sim_fpu_32to (&f, frgh);
91 sim_fpu_abs (&fres, &f);
92 sim_fpu_to32 (&result, &fres);
97 sh64_faddd(SIM_CPU *current_cpu, DF drg, DF drh)
100 sim_fpu f1, f2, fres;
102 sim_fpu_64to (&f1, drg);
103 sim_fpu_64to (&f2, drh);
104 sim_fpu_add (&fres, &f1, &f2);
105 sim_fpu_to64 (&result, &fres);
110 sh64_fadds(SIM_CPU *current_cpu, SF frg, SF frh)
113 sim_fpu f1, f2, fres;
115 sim_fpu_32to (&f1, frg);
116 sim_fpu_32to (&f2, frh);
117 sim_fpu_add (&fres, &f1, &f2);
118 sim_fpu_to32 (&result, &fres);
123 sh64_fcmpeqd(SIM_CPU *current_cpu, DF drg, DF drh)
127 sim_fpu_64to (&f1, drg);
128 sim_fpu_64to (&f2, drh);
129 return sim_fpu_is_eq (&f1, &f2);
133 sh64_fcmpeqs(SIM_CPU *current_cpu, SF frg, SF frh)
137 sim_fpu_32to (&f1, frg);
138 sim_fpu_32to (&f2, frh);
139 return sim_fpu_is_eq (&f1, &f2);
143 sh64_fcmpged(SIM_CPU *current_cpu, DF drg, DF drh)
147 sim_fpu_64to (&f1, drg);
148 sim_fpu_64to (&f2, drh);
149 return sim_fpu_is_ge (&f1, &f2);
153 sh64_fcmpges(SIM_CPU *current_cpu, SF frg, SF frh)
157 sim_fpu_32to (&f1, frg);
158 sim_fpu_32to (&f2, frh);
159 return sim_fpu_is_ge (&f1, &f2);
163 sh64_fcmpgtd(SIM_CPU *current_cpu, DF drg, DF drh)
167 sim_fpu_64to (&f1, drg);
168 sim_fpu_64to (&f2, drh);
169 return sim_fpu_is_gt (&f1, &f2);
173 sh64_fcmpgts(SIM_CPU *current_cpu, SF frg, SF frh)
177 sim_fpu_32to (&f1, frg);
178 sim_fpu_32to (&f2, frh);
179 return sim_fpu_is_gt (&f1, &f2);
183 sh64_fcmpund(SIM_CPU *current_cpu, DF drg, DF drh)
187 sim_fpu_64to (&f1, drg);
188 sim_fpu_64to (&f2, drh);
189 return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
193 sh64_fcmpuns(SIM_CPU *current_cpu, SF frg, SF frh)
197 sim_fpu_32to (&f1, frg);
198 sim_fpu_32to (&f2, frh);
199 return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
203 sh64_fcnvds(SIM_CPU *current_cpu, DF drgh)
206 unsigned long long ll;
222 sh64_fcnvsd(SIM_CPU *current_cpu, SF frgh)
227 sim_fpu_32to (&f, frgh);
228 sim_fpu_to64 (&result, &f);
233 sh64_fdivd(SIM_CPU *current_cpu, DF drg, DF drh)
236 sim_fpu f1, f2, fres;
238 sim_fpu_64to (&f1, drg);
239 sim_fpu_64to (&f2, drh);
240 sim_fpu_div (&fres, &f1, &f2);
241 sim_fpu_to64 (&result, &fres);
246 sh64_fdivs(SIM_CPU *current_cpu, SF frg, SF frh)
249 sim_fpu f1, f2, fres;
251 sim_fpu_32to (&f1, frg);
252 sim_fpu_32to (&f2, frh);
253 sim_fpu_div (&fres, &f1, &f2);
254 sim_fpu_to32 (&result, &fres);
259 sh64_floatld(SIM_CPU *current_cpu, SF frgh)
264 sim_fpu_i32to (&f, frgh, sim_fpu_round_default);
265 sim_fpu_to64 (&result, &f);
270 sh64_floatls(SIM_CPU *current_cpu, SF frgh)
275 sim_fpu_i32to (&f, frgh, sim_fpu_round_default);
276 sim_fpu_to32 (&result, &f);
281 sh64_floatqd(SIM_CPU *current_cpu, DF drgh)
286 sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
287 sim_fpu_to64 (&result, &f);
292 sh64_floatqs(SIM_CPU *current_cpu, DF drgh)
297 sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
298 sim_fpu_to32 (&result, &f);
303 sh64_fmacs(SIM_CPU *current_cpu, SF fr0, SF frm, SF frn)
306 sim_fpu m1, m2, a1, fres;
308 sim_fpu_32to (&m1, fr0);
309 sim_fpu_32to (&m2, frm);
310 sim_fpu_32to (&a1, frn);
312 sim_fpu_mul (&fres, &m1, &m2);
313 sim_fpu_add (&fres, &fres, &a1);
315 sim_fpu_to32 (&result, &fres);
320 sh64_fmuld(SIM_CPU *current_cpu, DF drg, DF drh)
323 sim_fpu f1, f2, fres;
325 sim_fpu_64to (&f1, drg);
326 sim_fpu_64to (&f2, drh);
327 sim_fpu_mul (&fres, &f1, &f2);
328 sim_fpu_to64 (&result, &fres);
333 sh64_fmuls(SIM_CPU *current_cpu, SF frg, SF frh)
336 sim_fpu f1, f2, fres;
338 sim_fpu_32to (&f1, frg);
339 sim_fpu_32to (&f2, frh);
340 sim_fpu_mul (&fres, &f1, &f2);
341 sim_fpu_to32 (&result, &fres);
346 sh64_fnegd(SIM_CPU *current_cpu, DF drgh)
351 sim_fpu_64to (&f1, drgh);
352 sim_fpu_neg (&f2, &f1);
353 sim_fpu_to64 (&result, &f2);
358 sh64_fnegs(SIM_CPU *current_cpu, SF frgh)
363 sim_fpu_32to (&f, frgh);
364 sim_fpu_neg (&fres, &f);
365 sim_fpu_to32 (&result, &fres);
370 sh64_fsqrtd(SIM_CPU *current_cpu, DF drgh)
375 sim_fpu_64to (&f, drgh);
376 sim_fpu_sqrt (&fres, &f);
377 sim_fpu_to64 (&result, &fres);
382 sh64_fsqrts(SIM_CPU *current_cpu, SF frgh)
387 sim_fpu_32to (&f, frgh);
388 sim_fpu_sqrt (&fres, &f);
389 sim_fpu_to32 (&result, &fres);
394 sh64_fsubd(SIM_CPU *current_cpu, DF drg, DF drh)
397 sim_fpu f1, f2, fres;
399 sim_fpu_64to (&f1, drg);
400 sim_fpu_64to (&f2, drh);
401 sim_fpu_sub (&fres, &f1, &f2);
402 sim_fpu_to64 (&result, &fres);
407 sh64_fsubs(SIM_CPU *current_cpu, SF frg, SF frh)
410 sim_fpu f1, f2, fres;
412 sim_fpu_32to (&f1, frg);
413 sim_fpu_32to (&f2, frh);
414 sim_fpu_sub (&fres, &f1, &f2);
415 sim_fpu_to32 (&result, &fres);
420 sh64_ftrcdl(SIM_CPU *current_cpu, DF drgh)
425 sim_fpu_64to (&f, drgh);
426 sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
431 sh64_ftrcsl(SIM_CPU *current_cpu, SF frgh)
436 sim_fpu_32to (&f, frgh);
437 sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
442 sh64_ftrcdq(SIM_CPU *current_cpu, DF drgh)
447 sim_fpu_64to (&f, drgh);
448 sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
453 sh64_ftrcsq(SIM_CPU *current_cpu, SF frgh)
458 sim_fpu_32to (&f, frgh);
459 sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
464 sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f)
468 for (i = 0; i < 4; i++)
472 sim_fpu_32to (&sum, 0);
474 for (j = 0; j < 4; j++)
476 sim_fpu f1, f2, temp;
477 sim_fpu_32to (&f1, sh64_h_fr_get (cpu, (g + i) + (j * 4)));
478 sim_fpu_32to (&f2, sh64_h_fr_get (cpu, h + j));
479 sim_fpu_mul (&temp, &f1, &f2);
480 sim_fpu_add (&sum, &sum, &temp);
482 sim_fpu_to32 (&result, &sum);
483 sh64_h_fr_set (cpu, f + i, result);
487 /* Count the number of arguments. */
494 if (! STATE_PROG_ARGV (CPU_STATE (cpu)))
497 while (STATE_PROG_ARGV (CPU_STATE (cpu)) [i] != NULL)
503 /* Read a null terminated string from memory, return in a buffer */
505 fetch_str (current_cpu, pc, addr)
506 SIM_CPU *current_cpu;
512 while (sim_core_read_1 (current_cpu,
513 pc, read_map, addr + nr) != 0)
515 buf = NZALLOC (char, nr + 1);
516 sim_read (CPU_STATE (current_cpu), addr, buf, nr);
521 trap_handler (SIM_CPU *current_cpu, int shmedia_abi_p, UQI trapnum, PCADDR pc)
528 sim_io_write_stdout (CPU_STATE (current_cpu), &ch, 1);
532 sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
537 int ret_reg = (shmedia_abi_p) ? 2 : 0;
539 DI PARM1 = GET_H_GR ((shmedia_abi_p) ? 3 : 5);
540 DI PARM2 = GET_H_GR ((shmedia_abi_p) ? 4 : 6);
541 DI PARM3 = GET_H_GR ((shmedia_abi_p) ? 5 : 7);
543 switch (GET_H_GR ((shmedia_abi_p) ? 2 : 4))
546 buf = zalloc (PARM3);
547 sim_read (CPU_STATE (current_cpu), PARM2, buf, PARM3);
549 sim_io_write (CPU_STATE (current_cpu),
556 sim_io_lseek (CPU_STATE (current_cpu),
557 PARM1, PARM2, PARM3));
561 sim_engine_halt (CPU_STATE (current_cpu), current_cpu,
562 NULL, pc, sim_exited, PARM1);
566 buf = zalloc (PARM3);
568 sim_io_read (CPU_STATE (current_cpu),
570 sim_write (CPU_STATE (current_cpu), PARM2, buf, PARM3);
575 buf = fetch_str (current_cpu, pc, PARM1);
577 sim_io_open (CPU_STATE (current_cpu),
584 sim_io_close (CPU_STATE (current_cpu), PARM1));
588 SET_H_GR (ret_reg, time (0));
592 SET_H_GR (ret_reg, count_argc (current_cpu));
596 if (PARM1 < count_argc (current_cpu))
598 strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]));
600 SET_H_GR (ret_reg, -1);
604 if (PARM1 < count_argc (current_cpu))
606 /* Include the NULL byte. */
607 i = strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]) + 1;
608 sim_write (CPU_STATE (current_cpu),
610 STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1],
613 /* Just for good measure. */
614 SET_H_GR (ret_reg, i);
618 SET_H_GR (ret_reg, -1);
622 SET_H_GR (ret_reg, -1);
635 sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
641 sh64_trapa (SIM_CPU *current_cpu, DI rm, PCADDR pc)
643 trap_handler (current_cpu, 1, (UQI) rm & 0xff, pc);
647 sh64_compact_trapa (SIM_CPU *current_cpu, UQI trapnum, PCADDR pc)
651 /* If this is an SH5 executable, this is SHcompact code running in
655 (bfd_get_mach (STATE_PROG_BFD (CPU_STATE (current_cpu))) == bfd_mach_sh5);
657 trap_handler (current_cpu, mach_sh5_p, trapnum, pc);
661 sh64_nsb (SIM_CPU *current_cpu, DI rm)
663 int result = 0, count;
664 UDI source = (UDI) rm;
670 for (count = 32; count; count >>= 1)
672 UDI newval = source << count;
674 if ((newval >> count) == source)
685 sh64_break (SIM_CPU *current_cpu, PCADDR pc)
687 SIM_DESC sd = CPU_STATE (current_cpu);
688 sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
692 set_isa (SIM_CPU *current_cpu, int mode)
697 /* The semantic code invokes this for invalid (unrecognized) instructions. */
700 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
702 SIM_DESC sd = CPU_STATE (current_cpu);
703 sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
709 /* Process an address exception. */
712 sh64_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
713 unsigned int map, int nr_bytes, address_word addr,
714 transfer_type transfer, sim_core_signals sig)
716 sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
721 /* Initialize cycle counting for an insn.
722 FIRST_P is non-zero if this is the first insn in a set of parallel
726 sh64_compact_model_insn_before (SIM_CPU *cpu, int first_p)
732 sh64_media_model_insn_before (SIM_CPU *cpu, int first_p)
737 /* Record the cycles computed for an insn.
738 LAST_P is non-zero if this is the last insn in a set of parallel insns,
739 and we update the total cycle count.
740 CYCLES is the cycle count of the insn. */
743 sh64_compact_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
749 sh64_media_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
755 sh64_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
757 /* Fetch general purpose registers. */
758 if (nr >= SIM_SH64_R0_REGNUM
759 && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
762 *((unsigned64*) buf) =
763 H2T_8 (sh64_h_gr_get (cpu, nr - SIM_SH64_R0_REGNUM));
768 if (nr == SIM_SH64_PC_REGNUM && len == 8)
770 *((unsigned64*) buf) = H2T_8 (sh64_h_pc_get (cpu) | sh64_h_ism_get (cpu));
774 /* Fetch status register (SR). */
775 if (nr == SIM_SH64_SR_REGNUM && len == 8)
777 *((unsigned64*) buf) = H2T_8 (sh64_h_sr_get (cpu));
781 /* Fetch saved status register (SSR) and PC (SPC). */
782 if ((nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
785 *((unsigned64*) buf) = 0;
789 /* Fetch target registers. */
790 if (nr >= SIM_SH64_TR0_REGNUM
791 && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
794 *((unsigned64*) buf) =
795 H2T_8 (sh64_h_tr_get (cpu, nr - SIM_SH64_TR0_REGNUM));
799 /* Fetch floating point registers. */
800 if (nr >= SIM_SH64_FR0_REGNUM
801 && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
804 *((unsigned32*) buf) =
805 H2T_4 (sh64_h_fr_get (cpu, nr - SIM_SH64_FR0_REGNUM));
809 /* We should never get here. */
814 sh64_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
816 /* Store general purpose registers. */
817 if (nr >= SIM_SH64_R0_REGNUM
818 && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
821 sh64_h_gr_set (cpu, nr - SIM_SH64_R0_REGNUM, T2H_8 (*((unsigned64*)buf)));
826 if (nr == SIM_SH64_PC_REGNUM && len == 8)
828 unsigned64 new_pc = T2H_8 (*((unsigned64*)buf));
829 sh64_h_pc_set (cpu, new_pc);
833 /* Store status register (SR). */
834 if (nr == SIM_SH64_SR_REGNUM && len == 8)
836 sh64_h_sr_set (cpu, T2H_8 (*((unsigned64*)buf)));
840 /* Store saved status register (SSR) and PC (SPC). */
841 if (nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
847 /* Store target registers. */
848 if (nr >= SIM_SH64_TR0_REGNUM
849 && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
852 sh64_h_tr_set (cpu, nr - SIM_SH64_TR0_REGNUM, T2H_8 (*((unsigned64*)buf)));
856 /* Store floating point registers. */
857 if (nr >= SIM_SH64_FR0_REGNUM
858 && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
861 sh64_h_fr_set (cpu, nr - SIM_SH64_FR0_REGNUM, T2H_4 (*((unsigned32*)buf)));
865 /* We should never get here. */
870 sh64_engine_run_full(SIM_CPU *cpu)
872 if (sh64_h_ism_get (cpu) == ISM_MEDIA)
874 if (!sh64_idesc_media)
876 sh64_media_init_idesc_table (cpu);
877 sh64_idesc_media = CPU_IDESC (cpu);
880 CPU_IDESC (cpu) = sh64_idesc_media;
881 sh64_media_engine_run_full (cpu);
885 if (!sh64_idesc_compact)
887 sh64_compact_init_idesc_table (cpu);
888 sh64_idesc_compact = CPU_IDESC (cpu);
891 CPU_IDESC (cpu) = sh64_idesc_compact;
892 sh64_compact_engine_run_full (cpu);
897 sh64_engine_run_fast (SIM_CPU *cpu)
899 if (sh64_h_ism_get (cpu) == ISM_MEDIA)
901 if (!sh64_idesc_media)
903 sh64_media_init_idesc_table (cpu);
904 sh64_idesc_media = CPU_IDESC (cpu);
907 CPU_IDESC (cpu) = sh64_idesc_media;
908 sh64_media_engine_run_fast (cpu);
912 if (!sh64_idesc_compact)
914 sh64_compact_init_idesc_table (cpu);
915 sh64_idesc_compact = CPU_IDESC (cpu);
918 CPU_IDESC (cpu) = sh64_idesc_compact;
919 sh64_compact_engine_run_fast (cpu);
924 sh64_prepare_run (SIM_CPU *cpu)
929 static const CGEN_INSN *
930 sh64_get_idata (SIM_CPU *cpu, int inum)
932 return CPU_IDESC (cpu) [inum].idata;
936 sh64_init_cpu (SIM_CPU *cpu)
938 CPU_REG_FETCH (cpu) = sh64_fetch_register;
939 CPU_REG_STORE (cpu) = sh64_store_register;
940 CPU_PC_FETCH (cpu) = sh64_h_pc_get;
941 CPU_PC_STORE (cpu) = sh64_h_pc_set;
942 CPU_GET_IDATA (cpu) = sh64_get_idata;
943 /* Only used by profiling. 0 disables it. */
944 CPU_MAX_INSNS (cpu) = 0;
945 CPU_INSN_NAME (cpu) = cgen_insn_name;
946 CPU_FULL_ENGINE_FN (cpu) = sh64_engine_run_full;
948 CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_fast;
950 CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_full;
955 shmedia_init_cpu (SIM_CPU *cpu)
961 shcompact_init_cpu (SIM_CPU *cpu)
972 static const MODEL sh_models [] =
974 { "sh2", & sh2_mach, MODEL_SH5, NULL, sh64_model_init },
975 { "sh3", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
976 { "sh3e", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
977 { "sh4", & sh4_mach, MODEL_SH5, NULL, sh64_model_init },
978 { "sh5", & sh5_mach, MODEL_SH5, NULL, sh64_model_init },
982 static const MACH_IMP_PROPERTIES sh5_imp_properties =
992 const MACH sh2_mach =
994 "sh2", "sh2", MACH_SH5,
995 16, 16, &sh_models[0], &sh5_imp_properties,
1000 const MACH sh3_mach =
1002 "sh3", "sh3", MACH_SH5,
1003 16, 16, &sh_models[1], &sh5_imp_properties,
1008 const MACH sh3e_mach =
1010 "sh3e", "sh3e", MACH_SH5,
1011 16, 16, &sh_models[2], &sh5_imp_properties,
1016 const MACH sh4_mach =
1018 "sh4", "sh4", MACH_SH5,
1019 16, 16, &sh_models[3], &sh5_imp_properties,
1024 const MACH sh5_mach =
1026 "sh5", "sh5", MACH_SH5,
1027 32, 32, &sh_models[4], &sh5_imp_properties,