1 /* SH5 simulator support code
2 Copyright (C) 2000-2017 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 #include "gdb/callback.h"
29 #include "defs-compact.h"
32 /* From include/gdb/. */
33 #include "gdb/sim-sh.h"
43 #define SYS_argnlen 173
46 IDESC * sh64_idesc_media;
47 IDESC * sh64_idesc_compact;
50 sh64_endian (SIM_CPU *current_cpu)
52 return (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN);
56 sh64_fldi0 (SIM_CPU *current_cpu)
59 sim_fpu_to32 (&result, &sim_fpu_zero);
64 sh64_fldi1 (SIM_CPU *current_cpu)
67 sim_fpu_to32 (&result, &sim_fpu_one);
72 sh64_fabsd(SIM_CPU *current_cpu, DF drgh)
77 sim_fpu_64to (&f, drgh);
78 sim_fpu_abs (&fres, &f);
79 sim_fpu_to64 (&result, &fres);
84 sh64_fabss(SIM_CPU *current_cpu, SF frgh)
89 sim_fpu_32to (&f, frgh);
90 sim_fpu_abs (&fres, &f);
91 sim_fpu_to32 (&result, &fres);
96 sh64_faddd(SIM_CPU *current_cpu, DF drg, DF drh)
101 sim_fpu_64to (&f1, drg);
102 sim_fpu_64to (&f2, drh);
103 sim_fpu_add (&fres, &f1, &f2);
104 sim_fpu_to64 (&result, &fres);
109 sh64_fadds(SIM_CPU *current_cpu, SF frg, SF frh)
112 sim_fpu f1, f2, fres;
114 sim_fpu_32to (&f1, frg);
115 sim_fpu_32to (&f2, frh);
116 sim_fpu_add (&fres, &f1, &f2);
117 sim_fpu_to32 (&result, &fres);
122 sh64_fcmpeqd(SIM_CPU *current_cpu, DF drg, DF drh)
126 sim_fpu_64to (&f1, drg);
127 sim_fpu_64to (&f2, drh);
128 return sim_fpu_is_eq (&f1, &f2);
132 sh64_fcmpeqs(SIM_CPU *current_cpu, SF frg, SF frh)
136 sim_fpu_32to (&f1, frg);
137 sim_fpu_32to (&f2, frh);
138 return sim_fpu_is_eq (&f1, &f2);
142 sh64_fcmpged(SIM_CPU *current_cpu, DF drg, DF drh)
146 sim_fpu_64to (&f1, drg);
147 sim_fpu_64to (&f2, drh);
148 return sim_fpu_is_ge (&f1, &f2);
152 sh64_fcmpges(SIM_CPU *current_cpu, SF frg, SF frh)
156 sim_fpu_32to (&f1, frg);
157 sim_fpu_32to (&f2, frh);
158 return sim_fpu_is_ge (&f1, &f2);
162 sh64_fcmpgtd(SIM_CPU *current_cpu, DF drg, DF drh)
166 sim_fpu_64to (&f1, drg);
167 sim_fpu_64to (&f2, drh);
168 return sim_fpu_is_gt (&f1, &f2);
172 sh64_fcmpgts(SIM_CPU *current_cpu, SF frg, SF frh)
176 sim_fpu_32to (&f1, frg);
177 sim_fpu_32to (&f2, frh);
178 return sim_fpu_is_gt (&f1, &f2);
182 sh64_fcmpund(SIM_CPU *current_cpu, DF drg, DF drh)
186 sim_fpu_64to (&f1, drg);
187 sim_fpu_64to (&f2, drh);
188 return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
192 sh64_fcmpuns(SIM_CPU *current_cpu, SF frg, SF frh)
196 sim_fpu_32to (&f1, frg);
197 sim_fpu_32to (&f2, frh);
198 return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
202 sh64_fcnvds(SIM_CPU *current_cpu, DF drgh)
205 unsigned long long ll;
221 sh64_fcnvsd(SIM_CPU *current_cpu, SF frgh)
226 sim_fpu_32to (&f, frgh);
227 sim_fpu_to64 (&result, &f);
232 sh64_fdivd(SIM_CPU *current_cpu, DF drg, DF drh)
235 sim_fpu f1, f2, fres;
237 sim_fpu_64to (&f1, drg);
238 sim_fpu_64to (&f2, drh);
239 sim_fpu_div (&fres, &f1, &f2);
240 sim_fpu_to64 (&result, &fres);
245 sh64_fdivs(SIM_CPU *current_cpu, SF frg, SF frh)
248 sim_fpu f1, f2, fres;
250 sim_fpu_32to (&f1, frg);
251 sim_fpu_32to (&f2, frh);
252 sim_fpu_div (&fres, &f1, &f2);
253 sim_fpu_to32 (&result, &fres);
258 sh64_floatld(SIM_CPU *current_cpu, SF frgh)
263 sim_fpu_i32to (&f, frgh, sim_fpu_round_default);
264 sim_fpu_to64 (&result, &f);
269 sh64_floatls(SIM_CPU *current_cpu, SF frgh)
274 sim_fpu_i32to (&f, frgh, sim_fpu_round_default);
275 sim_fpu_to32 (&result, &f);
280 sh64_floatqd(SIM_CPU *current_cpu, DF drgh)
285 sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
286 sim_fpu_to64 (&result, &f);
291 sh64_floatqs(SIM_CPU *current_cpu, DF drgh)
296 sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
297 sim_fpu_to32 (&result, &f);
302 sh64_fmacs(SIM_CPU *current_cpu, SF fr0, SF frm, SF frn)
305 sim_fpu m1, m2, a1, fres;
307 sim_fpu_32to (&m1, fr0);
308 sim_fpu_32to (&m2, frm);
309 sim_fpu_32to (&a1, frn);
311 sim_fpu_mul (&fres, &m1, &m2);
312 sim_fpu_add (&fres, &fres, &a1);
314 sim_fpu_to32 (&result, &fres);
319 sh64_fmuld(SIM_CPU *current_cpu, DF drg, DF drh)
322 sim_fpu f1, f2, fres;
324 sim_fpu_64to (&f1, drg);
325 sim_fpu_64to (&f2, drh);
326 sim_fpu_mul (&fres, &f1, &f2);
327 sim_fpu_to64 (&result, &fres);
332 sh64_fmuls(SIM_CPU *current_cpu, SF frg, SF frh)
335 sim_fpu f1, f2, fres;
337 sim_fpu_32to (&f1, frg);
338 sim_fpu_32to (&f2, frh);
339 sim_fpu_mul (&fres, &f1, &f2);
340 sim_fpu_to32 (&result, &fres);
345 sh64_fnegd(SIM_CPU *current_cpu, DF drgh)
350 sim_fpu_64to (&f1, drgh);
351 sim_fpu_neg (&f2, &f1);
352 sim_fpu_to64 (&result, &f2);
357 sh64_fnegs(SIM_CPU *current_cpu, SF frgh)
362 sim_fpu_32to (&f, frgh);
363 sim_fpu_neg (&fres, &f);
364 sim_fpu_to32 (&result, &fres);
369 sh64_fsqrtd(SIM_CPU *current_cpu, DF drgh)
374 sim_fpu_64to (&f, drgh);
375 sim_fpu_sqrt (&fres, &f);
376 sim_fpu_to64 (&result, &fres);
381 sh64_fsqrts(SIM_CPU *current_cpu, SF frgh)
386 sim_fpu_32to (&f, frgh);
387 sim_fpu_sqrt (&fres, &f);
388 sim_fpu_to32 (&result, &fres);
393 sh64_fsubd(SIM_CPU *current_cpu, DF drg, DF drh)
396 sim_fpu f1, f2, fres;
398 sim_fpu_64to (&f1, drg);
399 sim_fpu_64to (&f2, drh);
400 sim_fpu_sub (&fres, &f1, &f2);
401 sim_fpu_to64 (&result, &fres);
406 sh64_fsubs(SIM_CPU *current_cpu, SF frg, SF frh)
409 sim_fpu f1, f2, fres;
411 sim_fpu_32to (&f1, frg);
412 sim_fpu_32to (&f2, frh);
413 sim_fpu_sub (&fres, &f1, &f2);
414 sim_fpu_to32 (&result, &fres);
419 sh64_ftrcdl(SIM_CPU *current_cpu, DF drgh)
424 sim_fpu_64to (&f, drgh);
425 sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
430 sh64_ftrcsl(SIM_CPU *current_cpu, SF frgh)
435 sim_fpu_32to (&f, frgh);
436 sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
441 sh64_ftrcdq(SIM_CPU *current_cpu, DF drgh)
446 sim_fpu_64to (&f, drgh);
447 sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
452 sh64_ftrcsq(SIM_CPU *current_cpu, SF frgh)
457 sim_fpu_32to (&f, frgh);
458 sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
463 sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f)
467 for (i = 0; i < 4; i++)
471 sim_fpu_32to (&sum, 0);
473 for (j = 0; j < 4; j++)
475 sim_fpu f1, f2, temp;
476 sim_fpu_32to (&f1, sh64_h_fr_get (cpu, (g + i) + (j * 4)));
477 sim_fpu_32to (&f2, sh64_h_fr_get (cpu, h + j));
478 sim_fpu_mul (&temp, &f1, &f2);
479 sim_fpu_add (&sum, &sum, &temp);
481 sim_fpu_to32 (&result, &sum);
482 sh64_h_fr_set (cpu, f + i, result);
487 sh64_fipr (SIM_CPU *cpu, unsigned m, unsigned n)
489 SF result = sh64_fmuls (cpu, sh64_h_fvc_get (cpu, m), sh64_h_fvc_get (cpu, n));
490 result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 1), sh64_h_frc_get (cpu, n + 1)));
491 result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 2), sh64_h_frc_get (cpu, n + 2)));
492 result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 3), sh64_h_frc_get (cpu, n + 3)));
493 sh64_h_frc_set (cpu, n + 3, result);
497 sh64_fiprs (SIM_CPU *cpu, unsigned g, unsigned h)
499 SF temp = sh64_fmuls (cpu, sh64_h_fr_get (cpu, g), sh64_h_fr_get (cpu, h));
500 temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 1), sh64_h_fr_get (cpu, h + 1)));
501 temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 2), sh64_h_fr_get (cpu, h + 2)));
502 temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 3), sh64_h_fr_get (cpu, h + 3)));
507 sh64_fldp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f)
509 sh64_h_fr_set (cpu, f, GETMEMSF (cpu, pc, rm + rn));
510 sh64_h_fr_set (cpu, f + 1, GETMEMSF (cpu, pc, rm + rn + 4));
514 sh64_fstp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f)
516 SETMEMSF (cpu, pc, rm + rn, sh64_h_fr_get (cpu, f));
517 SETMEMSF (cpu, pc, rm + rn + 4, sh64_h_fr_get (cpu, f + 1));
521 sh64_ftrv (SIM_CPU *cpu, UINT ignored)
523 /* TODO: Unimplemented. */
527 sh64_pref (SIM_CPU *cpu, SI addr)
529 /* TODO: Unimplemented. */
532 /* Read a null terminated string from memory, return in a buffer */
534 fetch_str (current_cpu, pc, addr)
535 SIM_CPU *current_cpu;
541 while (sim_core_read_1 (current_cpu,
542 pc, read_map, addr + nr) != 0)
544 buf = NZALLOC (char, nr + 1);
545 sim_read (CPU_STATE (current_cpu), addr, buf, nr);
550 trap_handler (SIM_CPU *current_cpu, int shmedia_abi_p, UQI trapnum, PCADDR pc)
557 sim_io_write_stdout (CPU_STATE (current_cpu), &ch, 1);
561 sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
566 int ret_reg = (shmedia_abi_p) ? 2 : 0;
568 DI PARM1 = GET_H_GR ((shmedia_abi_p) ? 3 : 5);
569 DI PARM2 = GET_H_GR ((shmedia_abi_p) ? 4 : 6);
570 DI PARM3 = GET_H_GR ((shmedia_abi_p) ? 5 : 7);
572 switch (GET_H_GR ((shmedia_abi_p) ? 2 : 4))
575 buf = zalloc (PARM3);
576 sim_read (CPU_STATE (current_cpu), PARM2, buf, PARM3);
578 sim_io_write (CPU_STATE (current_cpu),
585 sim_io_lseek (CPU_STATE (current_cpu),
586 PARM1, PARM2, PARM3));
590 sim_engine_halt (CPU_STATE (current_cpu), current_cpu,
591 NULL, pc, sim_exited, PARM1);
595 buf = zalloc (PARM3);
597 sim_io_read (CPU_STATE (current_cpu),
599 sim_write (CPU_STATE (current_cpu), PARM2, buf, PARM3);
604 buf = fetch_str (current_cpu, pc, PARM1);
606 sim_io_open (CPU_STATE (current_cpu),
613 sim_io_close (CPU_STATE (current_cpu), PARM1));
617 SET_H_GR (ret_reg, time (0));
621 SET_H_GR (ret_reg, countargv (STATE_PROG_ARGV (CPU_STATE (current_cpu))));
625 if (PARM1 < countargv (STATE_PROG_ARGV (CPU_STATE (current_cpu))))
627 strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]));
629 SET_H_GR (ret_reg, -1);
633 if (PARM1 < countargv (STATE_PROG_ARGV (CPU_STATE (current_cpu))))
635 /* Include the NULL byte. */
636 i = strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]) + 1;
637 sim_write (CPU_STATE (current_cpu),
639 STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1],
642 /* Just for good measure. */
643 SET_H_GR (ret_reg, i);
647 SET_H_GR (ret_reg, -1);
651 SET_H_GR (ret_reg, -1);
664 sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
670 sh64_trapa (SIM_CPU *current_cpu, DI rm, PCADDR pc)
672 trap_handler (current_cpu, 1, (UQI) rm & 0xff, pc);
676 sh64_compact_trapa (SIM_CPU *current_cpu, UQI trapnum, PCADDR pc)
680 /* If this is an SH5 executable, this is SHcompact code running in
684 (bfd_get_mach (STATE_PROG_BFD (CPU_STATE (current_cpu))) == bfd_mach_sh5);
686 trap_handler (current_cpu, mach_sh5_p, trapnum, pc);
690 sh64_nsb (SIM_CPU *current_cpu, DI rm)
692 int result = 0, count;
693 UDI source = (UDI) rm;
699 for (count = 32; count; count >>= 1)
701 UDI newval = source << count;
703 if ((newval >> count) == source)
714 sh64_break (SIM_CPU *current_cpu, PCADDR pc)
716 SIM_DESC sd = CPU_STATE (current_cpu);
717 sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
721 sh64_movua (SIM_CPU *current_cpu, PCADDR pc, SI rn)
726 /* Move the data one byte at a time to avoid alignment problems.
727 Be aware of endianness. */
729 for (i = 0; i < 4; ++i)
730 v = (v << 8) | (GETMEMQI (current_cpu, pc, rn + i) & 0xff);
737 set_isa (SIM_CPU *current_cpu, int mode)
742 /* The semantic code invokes this for invalid (unrecognized) instructions. */
745 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
747 SIM_DESC sd = CPU_STATE (current_cpu);
748 sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
754 /* Process an address exception. */
757 sh64_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
758 unsigned int map, int nr_bytes, address_word addr,
759 transfer_type transfer, sim_core_signals sig)
761 sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
766 /* Initialize cycle counting for an insn.
767 FIRST_P is non-zero if this is the first insn in a set of parallel
771 sh64_compact_model_insn_before (SIM_CPU *cpu, int first_p)
777 sh64_media_model_insn_before (SIM_CPU *cpu, int first_p)
782 /* Record the cycles computed for an insn.
783 LAST_P is non-zero if this is the last insn in a set of parallel insns,
784 and we update the total cycle count.
785 CYCLES is the cycle count of the insn. */
788 sh64_compact_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
794 sh64_media_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
800 sh64_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
802 /* Fetch general purpose registers. */
803 if (nr >= SIM_SH64_R0_REGNUM
804 && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
807 *((unsigned64*) buf) =
808 H2T_8 (sh64_h_gr_get (cpu, nr - SIM_SH64_R0_REGNUM));
813 if (nr == SIM_SH64_PC_REGNUM && len == 8)
815 *((unsigned64*) buf) = H2T_8 (sh64_h_pc_get (cpu) | sh64_h_ism_get (cpu));
819 /* Fetch status register (SR). */
820 if (nr == SIM_SH64_SR_REGNUM && len == 8)
822 *((unsigned64*) buf) = H2T_8 (sh64_h_sr_get (cpu));
826 /* Fetch saved status register (SSR) and PC (SPC). */
827 if ((nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
830 *((unsigned64*) buf) = 0;
834 /* Fetch target registers. */
835 if (nr >= SIM_SH64_TR0_REGNUM
836 && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
839 *((unsigned64*) buf) =
840 H2T_8 (sh64_h_tr_get (cpu, nr - SIM_SH64_TR0_REGNUM));
844 /* Fetch floating point registers. */
845 if (nr >= SIM_SH64_FR0_REGNUM
846 && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
849 *((unsigned32*) buf) =
850 H2T_4 (sh64_h_fr_get (cpu, nr - SIM_SH64_FR0_REGNUM));
854 /* We should never get here. */
859 sh64_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
861 /* Store general purpose registers. */
862 if (nr >= SIM_SH64_R0_REGNUM
863 && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
866 sh64_h_gr_set (cpu, nr - SIM_SH64_R0_REGNUM, T2H_8 (*((unsigned64*)buf)));
871 if (nr == SIM_SH64_PC_REGNUM && len == 8)
873 unsigned64 new_pc = T2H_8 (*((unsigned64*)buf));
874 sh64_h_pc_set (cpu, new_pc);
878 /* Store status register (SR). */
879 if (nr == SIM_SH64_SR_REGNUM && len == 8)
881 sh64_h_sr_set (cpu, T2H_8 (*((unsigned64*)buf)));
885 /* Store saved status register (SSR) and PC (SPC). */
886 if (nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
892 /* Store target registers. */
893 if (nr >= SIM_SH64_TR0_REGNUM
894 && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
897 sh64_h_tr_set (cpu, nr - SIM_SH64_TR0_REGNUM, T2H_8 (*((unsigned64*)buf)));
901 /* Store floating point registers. */
902 if (nr >= SIM_SH64_FR0_REGNUM
903 && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
906 sh64_h_fr_set (cpu, nr - SIM_SH64_FR0_REGNUM, T2H_4 (*((unsigned32*)buf)));
910 /* We should never get here. */
915 sh64_engine_run_full(SIM_CPU *cpu)
917 if (sh64_h_ism_get (cpu) == ISM_MEDIA)
919 if (!sh64_idesc_media)
921 sh64_media_init_idesc_table (cpu);
922 sh64_idesc_media = CPU_IDESC (cpu);
925 CPU_IDESC (cpu) = sh64_idesc_media;
926 sh64_media_engine_run_full (cpu);
930 if (!sh64_idesc_compact)
932 sh64_compact_init_idesc_table (cpu);
933 sh64_idesc_compact = CPU_IDESC (cpu);
936 CPU_IDESC (cpu) = sh64_idesc_compact;
937 sh64_compact_engine_run_full (cpu);
942 sh64_engine_run_fast (SIM_CPU *cpu)
944 if (sh64_h_ism_get (cpu) == ISM_MEDIA)
946 if (!sh64_idesc_media)
948 sh64_media_init_idesc_table (cpu);
949 sh64_idesc_media = CPU_IDESC (cpu);
952 CPU_IDESC (cpu) = sh64_idesc_media;
953 sh64_media_engine_run_fast (cpu);
957 if (!sh64_idesc_compact)
959 sh64_compact_init_idesc_table (cpu);
960 sh64_idesc_compact = CPU_IDESC (cpu);
963 CPU_IDESC (cpu) = sh64_idesc_compact;
964 sh64_compact_engine_run_fast (cpu);
969 sh64_prepare_run (SIM_CPU *cpu)
974 static const CGEN_INSN *
975 sh64_get_idata (SIM_CPU *cpu, int inum)
977 return CPU_IDESC (cpu) [inum].idata;
981 sh64_init_cpu (SIM_CPU *cpu)
983 CPU_REG_FETCH (cpu) = sh64_fetch_register;
984 CPU_REG_STORE (cpu) = sh64_store_register;
985 CPU_PC_FETCH (cpu) = sh64_h_pc_get;
986 CPU_PC_STORE (cpu) = sh64_h_pc_set;
987 CPU_GET_IDATA (cpu) = sh64_get_idata;
988 /* Only used by profiling. 0 disables it. */
989 CPU_MAX_INSNS (cpu) = 0;
990 CPU_INSN_NAME (cpu) = cgen_insn_name;
991 CPU_FULL_ENGINE_FN (cpu) = sh64_engine_run_full;
993 CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_fast;
995 CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_full;
1000 shmedia_init_cpu (SIM_CPU *cpu)
1002 sh64_init_cpu (cpu);
1006 shcompact_init_cpu (SIM_CPU *cpu)
1008 sh64_init_cpu (cpu);
1017 static const SIM_MODEL sh_models [] =
1019 { "sh2", & sh2_mach, MODEL_SH5, NULL, sh64_model_init },
1020 { "sh2e", & sh2e_mach, MODEL_SH5, NULL, sh64_model_init },
1021 { "sh2a", & sh2a_fpu_mach, MODEL_SH5, NULL, sh64_model_init },
1022 { "sh2a_nofpu", & sh2a_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
1023 { "sh3", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
1024 { "sh3e", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
1025 { "sh4", & sh4_mach, MODEL_SH5, NULL, sh64_model_init },
1026 { "sh4_nofpu", & sh4_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
1027 { "sh4a", & sh4a_mach, MODEL_SH5, NULL, sh64_model_init },
1028 { "sh4a_nofpu", & sh4a_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
1029 { "sh4al", & sh4al_mach, MODEL_SH5, NULL, sh64_model_init },
1030 { "sh5", & sh5_mach, MODEL_SH5, NULL, sh64_model_init },
1034 static const SIM_MACH_IMP_PROPERTIES sh5_imp_properties =
1044 const SIM_MACH sh2_mach =
1046 "sh2", "sh2", MACH_SH5,
1047 16, 16, &sh_models[0], &sh5_imp_properties,
1052 const SIM_MACH sh2e_mach =
1054 "sh2e", "sh2e", MACH_SH5,
1055 16, 16, &sh_models[1], &sh5_imp_properties,
1060 const SIM_MACH sh2a_fpu_mach =
1062 "sh2a", "sh2a", MACH_SH5,
1063 16, 16, &sh_models[2], &sh5_imp_properties,
1068 const SIM_MACH sh2a_nofpu_mach =
1070 "sh2a_nofpu", "sh2a_nofpu", MACH_SH5,
1071 16, 16, &sh_models[3], &sh5_imp_properties,
1076 const SIM_MACH sh3_mach =
1078 "sh3", "sh3", MACH_SH5,
1079 16, 16, &sh_models[4], &sh5_imp_properties,
1084 const SIM_MACH sh3e_mach =
1086 "sh3e", "sh3e", MACH_SH5,
1087 16, 16, &sh_models[5], &sh5_imp_properties,
1092 const SIM_MACH sh4_mach =
1094 "sh4", "sh4", MACH_SH5,
1095 16, 16, &sh_models[6], &sh5_imp_properties,
1100 const SIM_MACH sh4_nofpu_mach =
1102 "sh4_nofpu", "sh4_nofpu", MACH_SH5,
1103 16, 16, &sh_models[7], &sh5_imp_properties,
1108 const SIM_MACH sh4a_mach =
1110 "sh4a", "sh4a", MACH_SH5,
1111 16, 16, &sh_models[8], &sh5_imp_properties,
1116 const SIM_MACH sh4a_nofpu_mach =
1118 "sh4a_nofpu", "sh4a_nofpu", MACH_SH5,
1119 16, 16, &sh_models[9], &sh5_imp_properties,
1124 const SIM_MACH sh4al_mach =
1126 "sh4al", "sh4al", MACH_SH5,
1127 16, 16, &sh_models[10], &sh5_imp_properties,
1132 const SIM_MACH sh5_mach =
1134 "sh5", "sh5", MACH_SH5,
1135 32, 32, &sh_models[11], &sh5_imp_properties,