1 /* SH5 simulator support code
2 Copyright (C) 2000, 2001, 2006 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
29 #include "gdb/callback.h"
30 #include "defs-compact.h"
33 /* From include/gdb/. */
34 #include "gdb/sim-sh.h"
44 #define SYS_argnlen 173
47 IDESC * sh64_idesc_media;
48 IDESC * sh64_idesc_compact;
51 sh64_endian (SIM_CPU *current_cpu)
53 return (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN);
57 sh64_fldi0 (SIM_CPU *current_cpu)
60 sim_fpu_to32 (&result, &sim_fpu_zero);
65 sh64_fldi1 (SIM_CPU *current_cpu)
68 sim_fpu_to32 (&result, &sim_fpu_one);
73 sh64_fabsd(SIM_CPU *current_cpu, DF drgh)
78 sim_fpu_64to (&f, drgh);
79 sim_fpu_abs (&fres, &f);
80 sim_fpu_to64 (&result, &fres);
85 sh64_fabss(SIM_CPU *current_cpu, SF frgh)
90 sim_fpu_32to (&f, frgh);
91 sim_fpu_abs (&fres, &f);
92 sim_fpu_to32 (&result, &fres);
97 sh64_faddd(SIM_CPU *current_cpu, DF drg, DF drh)
100 sim_fpu f1, f2, fres;
102 sim_fpu_64to (&f1, drg);
103 sim_fpu_64to (&f2, drh);
104 sim_fpu_add (&fres, &f1, &f2);
105 sim_fpu_to64 (&result, &fres);
110 sh64_fadds(SIM_CPU *current_cpu, SF frg, SF frh)
113 sim_fpu f1, f2, fres;
115 sim_fpu_32to (&f1, frg);
116 sim_fpu_32to (&f2, frh);
117 sim_fpu_add (&fres, &f1, &f2);
118 sim_fpu_to32 (&result, &fres);
123 sh64_fcmpeqd(SIM_CPU *current_cpu, DF drg, DF drh)
127 sim_fpu_64to (&f1, drg);
128 sim_fpu_64to (&f2, drh);
129 return sim_fpu_is_eq (&f1, &f2);
133 sh64_fcmpeqs(SIM_CPU *current_cpu, SF frg, SF frh)
137 sim_fpu_32to (&f1, frg);
138 sim_fpu_32to (&f2, frh);
139 return sim_fpu_is_eq (&f1, &f2);
143 sh64_fcmpged(SIM_CPU *current_cpu, DF drg, DF drh)
147 sim_fpu_64to (&f1, drg);
148 sim_fpu_64to (&f2, drh);
149 return sim_fpu_is_ge (&f1, &f2);
153 sh64_fcmpges(SIM_CPU *current_cpu, SF frg, SF frh)
157 sim_fpu_32to (&f1, frg);
158 sim_fpu_32to (&f2, frh);
159 return sim_fpu_is_ge (&f1, &f2);
163 sh64_fcmpgtd(SIM_CPU *current_cpu, DF drg, DF drh)
167 sim_fpu_64to (&f1, drg);
168 sim_fpu_64to (&f2, drh);
169 return sim_fpu_is_gt (&f1, &f2);
173 sh64_fcmpgts(SIM_CPU *current_cpu, SF frg, SF frh)
177 sim_fpu_32to (&f1, frg);
178 sim_fpu_32to (&f2, frh);
179 return sim_fpu_is_gt (&f1, &f2);
183 sh64_fcmpund(SIM_CPU *current_cpu, DF drg, DF drh)
187 sim_fpu_64to (&f1, drg);
188 sim_fpu_64to (&f2, drh);
189 return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
193 sh64_fcmpuns(SIM_CPU *current_cpu, SF frg, SF frh)
197 sim_fpu_32to (&f1, frg);
198 sim_fpu_32to (&f2, frh);
199 return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
203 sh64_fcnvds(SIM_CPU *current_cpu, DF drgh)
206 unsigned long long ll;
222 sh64_fcnvsd(SIM_CPU *current_cpu, SF frgh)
227 sim_fpu_32to (&f, frgh);
228 sim_fpu_to64 (&result, &f);
233 sh64_fdivd(SIM_CPU *current_cpu, DF drg, DF drh)
236 sim_fpu f1, f2, fres;
238 sim_fpu_64to (&f1, drg);
239 sim_fpu_64to (&f2, drh);
240 sim_fpu_div (&fres, &f1, &f2);
241 sim_fpu_to64 (&result, &fres);
246 sh64_fdivs(SIM_CPU *current_cpu, SF frg, SF frh)
249 sim_fpu f1, f2, fres;
251 sim_fpu_32to (&f1, frg);
252 sim_fpu_32to (&f2, frh);
253 sim_fpu_div (&fres, &f1, &f2);
254 sim_fpu_to32 (&result, &fres);
259 sh64_floatld(SIM_CPU *current_cpu, SF frgh)
264 sim_fpu_i32to (&f, frgh, sim_fpu_round_default);
265 sim_fpu_to64 (&result, &f);
270 sh64_floatls(SIM_CPU *current_cpu, SF frgh)
275 sim_fpu_i32to (&f, frgh, sim_fpu_round_default);
276 sim_fpu_to32 (&result, &f);
281 sh64_floatqd(SIM_CPU *current_cpu, DF drgh)
286 sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
287 sim_fpu_to64 (&result, &f);
292 sh64_floatqs(SIM_CPU *current_cpu, DF drgh)
297 sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
298 sim_fpu_to32 (&result, &f);
303 sh64_fmacs(SIM_CPU *current_cpu, SF fr0, SF frm, SF frn)
306 sim_fpu m1, m2, a1, fres;
308 sim_fpu_32to (&m1, fr0);
309 sim_fpu_32to (&m2, frm);
310 sim_fpu_32to (&a1, frn);
312 sim_fpu_mul (&fres, &m1, &m2);
313 sim_fpu_add (&fres, &fres, &a1);
315 sim_fpu_to32 (&result, &fres);
320 sh64_fmuld(SIM_CPU *current_cpu, DF drg, DF drh)
323 sim_fpu f1, f2, fres;
325 sim_fpu_64to (&f1, drg);
326 sim_fpu_64to (&f2, drh);
327 sim_fpu_mul (&fres, &f1, &f2);
328 sim_fpu_to64 (&result, &fres);
333 sh64_fmuls(SIM_CPU *current_cpu, SF frg, SF frh)
336 sim_fpu f1, f2, fres;
338 sim_fpu_32to (&f1, frg);
339 sim_fpu_32to (&f2, frh);
340 sim_fpu_mul (&fres, &f1, &f2);
341 sim_fpu_to32 (&result, &fres);
346 sh64_fnegd(SIM_CPU *current_cpu, DF drgh)
351 sim_fpu_64to (&f1, drgh);
352 sim_fpu_neg (&f2, &f1);
353 sim_fpu_to64 (&result, &f2);
358 sh64_fnegs(SIM_CPU *current_cpu, SF frgh)
363 sim_fpu_32to (&f, frgh);
364 sim_fpu_neg (&fres, &f);
365 sim_fpu_to32 (&result, &fres);
370 sh64_fsqrtd(SIM_CPU *current_cpu, DF drgh)
375 sim_fpu_64to (&f, drgh);
376 sim_fpu_sqrt (&fres, &f);
377 sim_fpu_to64 (&result, &fres);
382 sh64_fsqrts(SIM_CPU *current_cpu, SF frgh)
387 sim_fpu_32to (&f, frgh);
388 sim_fpu_sqrt (&fres, &f);
389 sim_fpu_to32 (&result, &fres);
394 sh64_fsubd(SIM_CPU *current_cpu, DF drg, DF drh)
397 sim_fpu f1, f2, fres;
399 sim_fpu_64to (&f1, drg);
400 sim_fpu_64to (&f2, drh);
401 sim_fpu_sub (&fres, &f1, &f2);
402 sim_fpu_to64 (&result, &fres);
407 sh64_fsubs(SIM_CPU *current_cpu, SF frg, SF frh)
410 sim_fpu f1, f2, fres;
412 sim_fpu_32to (&f1, frg);
413 sim_fpu_32to (&f2, frh);
414 sim_fpu_sub (&fres, &f1, &f2);
415 sim_fpu_to32 (&result, &fres);
420 sh64_ftrcdl(SIM_CPU *current_cpu, DF drgh)
425 sim_fpu_64to (&f, drgh);
426 sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
431 sh64_ftrcsl(SIM_CPU *current_cpu, SF frgh)
436 sim_fpu_32to (&f, frgh);
437 sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
442 sh64_ftrcdq(SIM_CPU *current_cpu, DF drgh)
447 sim_fpu_64to (&f, drgh);
448 sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
453 sh64_ftrcsq(SIM_CPU *current_cpu, SF frgh)
458 sim_fpu_32to (&f, frgh);
459 sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
464 sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f)
468 for (i = 0; i < 4; i++)
472 sim_fpu_32to (&sum, 0);
474 for (j = 0; j < 4; j++)
476 sim_fpu f1, f2, temp;
477 sim_fpu_32to (&f1, sh64_h_fr_get (cpu, (g + i) + (j * 4)));
478 sim_fpu_32to (&f2, sh64_h_fr_get (cpu, h + j));
479 sim_fpu_mul (&temp, &f1, &f2);
480 sim_fpu_add (&sum, &sum, &temp);
482 sim_fpu_to32 (&result, &sum);
483 sh64_h_fr_set (cpu, f + i, result);
488 sh64_fipr (SIM_CPU *cpu, unsigned m, unsigned n)
490 SF result = sh64_fmuls (cpu, sh64_h_fvc_get (cpu, m), sh64_h_fvc_get (cpu, n));
491 result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 1), sh64_h_frc_get (cpu, n + 1)));
492 result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 2), sh64_h_frc_get (cpu, n + 2)));
493 result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 3), sh64_h_frc_get (cpu, n + 3)));
494 sh64_h_frc_set (cpu, n + 3, result);
498 sh64_fiprs (SIM_CPU *cpu, unsigned g, unsigned h)
500 SF temp = sh64_fmuls (cpu, sh64_h_fr_get (cpu, g), sh64_h_fr_get (cpu, h));
501 temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 1), sh64_h_fr_get (cpu, h + 1)));
502 temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 2), sh64_h_fr_get (cpu, h + 2)));
503 temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 3), sh64_h_fr_get (cpu, h + 3)));
508 sh64_fldp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f)
510 sh64_h_fr_set (cpu, f, GETMEMSF (cpu, pc, rm + rn));
511 sh64_h_fr_set (cpu, f + 1, GETMEMSF (cpu, pc, rm + rn + 4));
515 sh64_fstp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f)
517 SETMEMSF (cpu, pc, rm + rn, sh64_h_fr_get (cpu, f));
518 SETMEMSF (cpu, pc, rm + rn + 4, sh64_h_fr_get (cpu, f + 1));
522 sh64_ftrv (SIM_CPU *cpu, UINT ignored)
524 /* TODO: Unimplemented. */
528 sh64_pref (SIM_CPU *cpu, SI addr)
530 /* TODO: Unimplemented. */
533 /* Count the number of arguments. */
540 if (! STATE_PROG_ARGV (CPU_STATE (cpu)))
543 while (STATE_PROG_ARGV (CPU_STATE (cpu)) [i] != NULL)
549 /* Read a null terminated string from memory, return in a buffer */
551 fetch_str (current_cpu, pc, addr)
552 SIM_CPU *current_cpu;
558 while (sim_core_read_1 (current_cpu,
559 pc, read_map, addr + nr) != 0)
561 buf = NZALLOC (char, nr + 1);
562 sim_read (CPU_STATE (current_cpu), addr, buf, nr);
567 trap_handler (SIM_CPU *current_cpu, int shmedia_abi_p, UQI trapnum, PCADDR pc)
574 sim_io_write_stdout (CPU_STATE (current_cpu), &ch, 1);
578 sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
583 int ret_reg = (shmedia_abi_p) ? 2 : 0;
585 DI PARM1 = GET_H_GR ((shmedia_abi_p) ? 3 : 5);
586 DI PARM2 = GET_H_GR ((shmedia_abi_p) ? 4 : 6);
587 DI PARM3 = GET_H_GR ((shmedia_abi_p) ? 5 : 7);
589 switch (GET_H_GR ((shmedia_abi_p) ? 2 : 4))
592 buf = zalloc (PARM3);
593 sim_read (CPU_STATE (current_cpu), PARM2, buf, PARM3);
595 sim_io_write (CPU_STATE (current_cpu),
602 sim_io_lseek (CPU_STATE (current_cpu),
603 PARM1, PARM2, PARM3));
607 sim_engine_halt (CPU_STATE (current_cpu), current_cpu,
608 NULL, pc, sim_exited, PARM1);
612 buf = zalloc (PARM3);
614 sim_io_read (CPU_STATE (current_cpu),
616 sim_write (CPU_STATE (current_cpu), PARM2, buf, PARM3);
621 buf = fetch_str (current_cpu, pc, PARM1);
623 sim_io_open (CPU_STATE (current_cpu),
630 sim_io_close (CPU_STATE (current_cpu), PARM1));
634 SET_H_GR (ret_reg, time (0));
638 SET_H_GR (ret_reg, count_argc (current_cpu));
642 if (PARM1 < count_argc (current_cpu))
644 strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]));
646 SET_H_GR (ret_reg, -1);
650 if (PARM1 < count_argc (current_cpu))
652 /* Include the NULL byte. */
653 i = strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]) + 1;
654 sim_write (CPU_STATE (current_cpu),
656 STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1],
659 /* Just for good measure. */
660 SET_H_GR (ret_reg, i);
664 SET_H_GR (ret_reg, -1);
668 SET_H_GR (ret_reg, -1);
681 sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
687 sh64_trapa (SIM_CPU *current_cpu, DI rm, PCADDR pc)
689 trap_handler (current_cpu, 1, (UQI) rm & 0xff, pc);
693 sh64_compact_trapa (SIM_CPU *current_cpu, UQI trapnum, PCADDR pc)
697 /* If this is an SH5 executable, this is SHcompact code running in
701 (bfd_get_mach (STATE_PROG_BFD (CPU_STATE (current_cpu))) == bfd_mach_sh5);
703 trap_handler (current_cpu, mach_sh5_p, trapnum, pc);
707 sh64_nsb (SIM_CPU *current_cpu, DI rm)
709 int result = 0, count;
710 UDI source = (UDI) rm;
716 for (count = 32; count; count >>= 1)
718 UDI newval = source << count;
720 if ((newval >> count) == source)
731 sh64_break (SIM_CPU *current_cpu, PCADDR pc)
733 SIM_DESC sd = CPU_STATE (current_cpu);
734 sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
738 sh64_movua (SIM_CPU *current_cpu, PCADDR pc, SI rn)
743 /* Move the data one byte at a time to avoid alignment problems.
744 Be aware of endianness. */
746 for (i = 0; i < 4; ++i)
747 v = (v << 8) | (GETMEMQI (current_cpu, pc, rn + i) & 0xff);
754 set_isa (SIM_CPU *current_cpu, int mode)
759 /* The semantic code invokes this for invalid (unrecognized) instructions. */
762 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
764 SIM_DESC sd = CPU_STATE (current_cpu);
765 sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
771 /* Process an address exception. */
774 sh64_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
775 unsigned int map, int nr_bytes, address_word addr,
776 transfer_type transfer, sim_core_signals sig)
778 sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
783 /* Initialize cycle counting for an insn.
784 FIRST_P is non-zero if this is the first insn in a set of parallel
788 sh64_compact_model_insn_before (SIM_CPU *cpu, int first_p)
794 sh64_media_model_insn_before (SIM_CPU *cpu, int first_p)
799 /* Record the cycles computed for an insn.
800 LAST_P is non-zero if this is the last insn in a set of parallel insns,
801 and we update the total cycle count.
802 CYCLES is the cycle count of the insn. */
805 sh64_compact_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
811 sh64_media_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
817 sh64_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
819 /* Fetch general purpose registers. */
820 if (nr >= SIM_SH64_R0_REGNUM
821 && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
824 *((unsigned64*) buf) =
825 H2T_8 (sh64_h_gr_get (cpu, nr - SIM_SH64_R0_REGNUM));
830 if (nr == SIM_SH64_PC_REGNUM && len == 8)
832 *((unsigned64*) buf) = H2T_8 (sh64_h_pc_get (cpu) | sh64_h_ism_get (cpu));
836 /* Fetch status register (SR). */
837 if (nr == SIM_SH64_SR_REGNUM && len == 8)
839 *((unsigned64*) buf) = H2T_8 (sh64_h_sr_get (cpu));
843 /* Fetch saved status register (SSR) and PC (SPC). */
844 if ((nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
847 *((unsigned64*) buf) = 0;
851 /* Fetch target registers. */
852 if (nr >= SIM_SH64_TR0_REGNUM
853 && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
856 *((unsigned64*) buf) =
857 H2T_8 (sh64_h_tr_get (cpu, nr - SIM_SH64_TR0_REGNUM));
861 /* Fetch floating point registers. */
862 if (nr >= SIM_SH64_FR0_REGNUM
863 && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
866 *((unsigned32*) buf) =
867 H2T_4 (sh64_h_fr_get (cpu, nr - SIM_SH64_FR0_REGNUM));
871 /* We should never get here. */
876 sh64_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
878 /* Store general purpose registers. */
879 if (nr >= SIM_SH64_R0_REGNUM
880 && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
883 sh64_h_gr_set (cpu, nr - SIM_SH64_R0_REGNUM, T2H_8 (*((unsigned64*)buf)));
888 if (nr == SIM_SH64_PC_REGNUM && len == 8)
890 unsigned64 new_pc = T2H_8 (*((unsigned64*)buf));
891 sh64_h_pc_set (cpu, new_pc);
895 /* Store status register (SR). */
896 if (nr == SIM_SH64_SR_REGNUM && len == 8)
898 sh64_h_sr_set (cpu, T2H_8 (*((unsigned64*)buf)));
902 /* Store saved status register (SSR) and PC (SPC). */
903 if (nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
909 /* Store target registers. */
910 if (nr >= SIM_SH64_TR0_REGNUM
911 && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
914 sh64_h_tr_set (cpu, nr - SIM_SH64_TR0_REGNUM, T2H_8 (*((unsigned64*)buf)));
918 /* Store floating point registers. */
919 if (nr >= SIM_SH64_FR0_REGNUM
920 && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
923 sh64_h_fr_set (cpu, nr - SIM_SH64_FR0_REGNUM, T2H_4 (*((unsigned32*)buf)));
927 /* We should never get here. */
932 sh64_engine_run_full(SIM_CPU *cpu)
934 if (sh64_h_ism_get (cpu) == ISM_MEDIA)
936 if (!sh64_idesc_media)
938 sh64_media_init_idesc_table (cpu);
939 sh64_idesc_media = CPU_IDESC (cpu);
942 CPU_IDESC (cpu) = sh64_idesc_media;
943 sh64_media_engine_run_full (cpu);
947 if (!sh64_idesc_compact)
949 sh64_compact_init_idesc_table (cpu);
950 sh64_idesc_compact = CPU_IDESC (cpu);
953 CPU_IDESC (cpu) = sh64_idesc_compact;
954 sh64_compact_engine_run_full (cpu);
959 sh64_engine_run_fast (SIM_CPU *cpu)
961 if (sh64_h_ism_get (cpu) == ISM_MEDIA)
963 if (!sh64_idesc_media)
965 sh64_media_init_idesc_table (cpu);
966 sh64_idesc_media = CPU_IDESC (cpu);
969 CPU_IDESC (cpu) = sh64_idesc_media;
970 sh64_media_engine_run_fast (cpu);
974 if (!sh64_idesc_compact)
976 sh64_compact_init_idesc_table (cpu);
977 sh64_idesc_compact = CPU_IDESC (cpu);
980 CPU_IDESC (cpu) = sh64_idesc_compact;
981 sh64_compact_engine_run_fast (cpu);
986 sh64_prepare_run (SIM_CPU *cpu)
991 static const CGEN_INSN *
992 sh64_get_idata (SIM_CPU *cpu, int inum)
994 return CPU_IDESC (cpu) [inum].idata;
998 sh64_init_cpu (SIM_CPU *cpu)
1000 CPU_REG_FETCH (cpu) = sh64_fetch_register;
1001 CPU_REG_STORE (cpu) = sh64_store_register;
1002 CPU_PC_FETCH (cpu) = sh64_h_pc_get;
1003 CPU_PC_STORE (cpu) = sh64_h_pc_set;
1004 CPU_GET_IDATA (cpu) = sh64_get_idata;
1005 /* Only used by profiling. 0 disables it. */
1006 CPU_MAX_INSNS (cpu) = 0;
1007 CPU_INSN_NAME (cpu) = cgen_insn_name;
1008 CPU_FULL_ENGINE_FN (cpu) = sh64_engine_run_full;
1010 CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_fast;
1012 CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_full;
1017 shmedia_init_cpu (SIM_CPU *cpu)
1019 sh64_init_cpu (cpu);
1023 shcompact_init_cpu (SIM_CPU *cpu)
1025 sh64_init_cpu (cpu);
1034 static const MODEL sh_models [] =
1036 { "sh2", & sh2_mach, MODEL_SH5, NULL, sh64_model_init },
1037 { "sh2e", & sh2e_mach, MODEL_SH5, NULL, sh64_model_init },
1038 { "sh2a", & sh2a_fpu_mach, MODEL_SH5, NULL, sh64_model_init },
1039 { "sh2a_nofpu", & sh2a_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
1040 { "sh3", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
1041 { "sh3e", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
1042 { "sh4", & sh4_mach, MODEL_SH5, NULL, sh64_model_init },
1043 { "sh4_nofpu", & sh4_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
1044 { "sh4a", & sh4a_mach, MODEL_SH5, NULL, sh64_model_init },
1045 { "sh4a_nofpu", & sh4a_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
1046 { "sh4al", & sh4al_mach, MODEL_SH5, NULL, sh64_model_init },
1047 { "sh5", & sh5_mach, MODEL_SH5, NULL, sh64_model_init },
1051 static const MACH_IMP_PROPERTIES sh5_imp_properties =
1061 const MACH sh2_mach =
1063 "sh2", "sh2", MACH_SH5,
1064 16, 16, &sh_models[0], &sh5_imp_properties,
1069 const MACH sh2e_mach =
1071 "sh2e", "sh2e", MACH_SH5,
1072 16, 16, &sh_models[1], &sh5_imp_properties,
1077 const MACH sh2a_fpu_mach =
1079 "sh2a", "sh2a", MACH_SH5,
1080 16, 16, &sh_models[2], &sh5_imp_properties,
1085 const MACH sh2a_nofpu_mach =
1087 "sh2a_nofpu", "sh2a_nofpu", MACH_SH5,
1088 16, 16, &sh_models[3], &sh5_imp_properties,
1093 const MACH sh3_mach =
1095 "sh3", "sh3", MACH_SH5,
1096 16, 16, &sh_models[4], &sh5_imp_properties,
1101 const MACH sh3e_mach =
1103 "sh3e", "sh3e", MACH_SH5,
1104 16, 16, &sh_models[5], &sh5_imp_properties,
1109 const MACH sh4_mach =
1111 "sh4", "sh4", MACH_SH5,
1112 16, 16, &sh_models[6], &sh5_imp_properties,
1117 const MACH sh4_nofpu_mach =
1119 "sh4_nofpu", "sh4_nofpu", MACH_SH5,
1120 16, 16, &sh_models[7], &sh5_imp_properties,
1125 const MACH sh4a_mach =
1127 "sh4a", "sh4a", MACH_SH5,
1128 16, 16, &sh_models[8], &sh5_imp_properties,
1133 const MACH sh4a_nofpu_mach =
1135 "sh4a_nofpu", "sh4a_nofpu", MACH_SH5,
1136 16, 16, &sh_models[9], &sh5_imp_properties,
1141 const MACH sh4al_mach =
1143 "sh4al", "sh4al", MACH_SH5,
1144 16, 16, &sh_models[10], &sh5_imp_properties,
1149 const MACH sh5_mach =
1151 "sh5", "sh5", MACH_SH5,
1152 32, 32, &sh_models[11], &sh5_imp_properties,