1 /* CPU data header for sh.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996-2005 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
28 #include "opcode/cgen-bitset.h"
32 /* Given symbol S, return sh_cgen_<S>. */
33 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
34 #define CGEN_SYM(s) sh##_cgen_##s
36 #define CGEN_SYM(s) sh/**/_cgen_/**/s
40 /* Selected cpu families. */
43 #define CGEN_INSN_LSB0_P 0
45 /* Minimum size of any insn (in bytes). */
46 #define CGEN_MIN_INSN_SIZE 2
48 /* Maximum size of any insn (in bytes). */
49 #define CGEN_MAX_INSN_SIZE 4
51 #define CGEN_INT_INSN_P 1
53 /* Maximum number of syntax elements in an instruction. */
54 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
56 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
57 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
58 we can't hash on everything up to the space. */
59 #define CGEN_MNEMONIC_OPERANDS
61 /* Maximum number of fields in an instruction. */
62 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
66 /* Enum declaration for . */
67 typedef enum frc_names {
68 H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3
69 , H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7
70 , H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11
71 , H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15
74 /* Enum declaration for . */
75 typedef enum drc_names {
76 H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6
77 , H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14
80 /* Enum declaration for . */
81 typedef enum xf_names {
82 H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3
83 , H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7
84 , H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11
85 , H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15
90 /* Enum declaration for machine type selection. */
91 typedef enum mach_attr {
92 MACH_BASE, MACH_SH2, MACH_SH2E, MACH_SH2A_FPU
93 , MACH_SH2A_NOFPU, MACH_SH3, MACH_SH3E, MACH_SH4_NOFPU
94 , MACH_SH4, MACH_SH4A_NOFPU, MACH_SH4A, MACH_SH4AL
98 /* Enum declaration for instruction set selection. */
99 typedef enum isa_attr {
100 ISA_COMPACT, ISA_MEDIA, ISA_MAX
103 /* Enum declaration for sh4 insn groups. */
104 typedef enum sh4_group_attr {
105 SH4_GROUP_NONE, SH4_GROUP_MT, SH4_GROUP_EX, SH4_GROUP_BR
106 , SH4_GROUP_LS, SH4_GROUP_FE, SH4_GROUP_CO, SH4_GROUP_MAX
109 /* Enum declaration for sh4a insn groups. */
110 typedef enum sh4a_group_attr {
111 SH4A_GROUP_NONE, SH4A_GROUP_MT, SH4A_GROUP_EX, SH4A_GROUP_BR
112 , SH4A_GROUP_LS, SH4A_GROUP_FE, SH4A_GROUP_CO, SH4A_GROUP_MAX
115 /* Number of architecture variants. */
116 #define MAX_ISAS ((int) ISA_MAX)
117 #define MAX_MACHS ((int) MACH_MAX)
119 /* Ifield support. */
121 /* Ifield attribute indices. */
123 /* Enum declaration for cgen_ifld attrs. */
124 typedef enum cgen_ifld_attr {
125 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
126 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
127 , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
130 /* Number of non-boolean elements in cgen_ifld_attr. */
131 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
133 /* cgen_ifld attribute accessor macros. */
134 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
135 #define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
136 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
137 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
138 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
139 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
140 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
141 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
143 /* Enum declaration for sh ifield types. */
144 typedef enum ifield_type {
145 SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8
146 , SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10
147 , SH_F_RN, SH_F_RM, SH_F_7_1, SH_F_11_1
148 , SH_F_16_4, SH_F_DISP8, SH_F_DISP12, SH_F_IMM8
149 , SH_F_IMM4, SH_F_IMM4X2, SH_F_IMM4X4, SH_F_IMM8X2
150 , SH_F_IMM8X4, SH_F_IMM12X4, SH_F_IMM12X8, SH_F_DN
151 , SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN
152 , SH_F_XM, SH_F_IMM20_HI, SH_F_IMM20_LO, SH_F_IMM20
153 , SH_F_OP, SH_F_EXT, SH_F_RSVD, SH_F_LEFT
154 , SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT, SH_F_TRA
155 , SH_F_TRB, SH_F_LIKELY, SH_F_6_3, SH_F_23_2
156 , SH_F_IMM6, SH_F_IMM10, SH_F_IMM16, SH_F_UIMM6
157 , SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32, SH_F_DISP10
158 , SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2, SH_F_DISP16
162 #define MAX_IFLD ((int) SH_F_MAX)
164 /* Hardware attribute indices. */
166 /* Enum declaration for cgen_hw attrs. */
167 typedef enum cgen_hw_attr {
168 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
169 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA
173 /* Number of non-boolean elements in cgen_hw_attr. */
174 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
176 /* cgen_hw attribute accessor macros. */
177 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
178 #define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
179 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
180 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
181 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
182 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
184 /* Enum declaration for sh hardware types. */
185 typedef enum cgen_hw_type {
186 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
187 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GRC
188 , HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT
189 , HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT
190 , HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV
191 , HW_H_FMTX, HW_H_DR, HW_H_FSD, HW_H_FMOV
192 , HW_H_TR, HW_H_ENDIAN, HW_H_ISM, HW_H_FRC
193 , HW_H_DRC, HW_H_XF, HW_H_XD, HW_H_FVC
194 , HW_H_GBR, HW_H_VBR, HW_H_PR, HW_H_MACL
195 , HW_H_MACH, HW_H_TBIT, HW_MAX
198 #define MAX_HW ((int) HW_MAX)
200 /* Operand attribute indices. */
202 /* Enum declaration for cgen_operand attrs. */
203 typedef enum cgen_operand_attr {
204 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
205 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
206 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
207 , CGEN_OPERAND_END_NBOOLS
210 /* Number of non-boolean elements in cgen_operand_attr. */
211 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
213 /* cgen_operand attribute accessor macros. */
214 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
215 #define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
216 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
217 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
218 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
219 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
220 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
221 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
222 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
223 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
225 /* Enum declaration for sh operand types. */
226 typedef enum cgen_operand_type {
227 SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM
228 , SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM
229 , SH_OPERAND_FR0, SH_OPERAND_FMOVN, SH_OPERAND_FMOVM, SH_OPERAND_FVN
230 , SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM, SH_OPERAND_IMM4
231 , SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM20, SH_OPERAND_IMM4X2
232 , SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8
233 , SH_OPERAND_DISP12, SH_OPERAND_IMM12X4, SH_OPERAND_IMM12X8, SH_OPERAND_RM64
234 , SH_OPERAND_RN64, SH_OPERAND_GBR, SH_OPERAND_VBR, SH_OPERAND_PR
235 , SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT, SH_OPERAND_MBIT
236 , SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT, SH_OPERAND_SZBIT
237 , SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH, SH_OPERAND_FSDM
238 , SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG, SH_OPERAND_FRH
239 , SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF, SH_OPERAND_FVG
240 , SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG, SH_OPERAND_DRG
241 , SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH, SH_OPERAND_CRJ
242 , SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB, SH_OPERAND_DISP6
243 , SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2, SH_OPERAND_DISP10X4
244 , SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6, SH_OPERAND_IMM10
245 , SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16, SH_OPERAND_LIKELY
249 /* Number of operands types. */
250 #define MAX_OPERANDS 79
252 /* Maximum number of operands referenced by any insn. */
253 #define MAX_OPERAND_INSTANCES 8
255 /* Insn attribute indices. */
257 /* Enum declaration for cgen_insn attrs. */
258 typedef enum cgen_insn_attr {
259 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
260 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
261 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN
262 , CGEN_INSN_32_BIT_INSN, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
263 , CGEN_INSN_ISA, CGEN_INSN_SH4_GROUP, CGEN_INSN_SH4A_GROUP, CGEN_INSN_END_NBOOLS
266 /* Number of non-boolean elements in cgen_insn_attr. */
267 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
269 /* cgen_insn attribute accessor macros. */
270 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
271 #define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
272 #define CGEN_ATTR_CGEN_INSN_SH4_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset)
273 #define CGEN_ATTR_CGEN_INSN_SH4A_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4A_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset)
274 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
275 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
276 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
277 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
278 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
279 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
280 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
281 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
282 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
283 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
284 #define CGEN_ATTR_CGEN_INSN_ILLSLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ILLSLOT)) != 0)
285 #define CGEN_ATTR_CGEN_INSN_FP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FP_INSN)) != 0)
286 #define CGEN_ATTR_CGEN_INSN_32_BIT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_32_BIT_INSN)) != 0)
288 /* cgen.h uses things we just defined. */
289 #include "opcode/cgen.h"
291 extern const struct cgen_ifld sh_cgen_ifld_table[];
294 extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[];
295 extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[];
296 extern const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[];
297 extern const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[];
299 /* Hardware decls. */
301 extern CGEN_KEYWORD sh_cgen_opval_h_gr;
302 extern CGEN_KEYWORD sh_cgen_opval_h_grc;
303 extern CGEN_KEYWORD sh_cgen_opval_h_cr;
304 extern CGEN_KEYWORD sh_cgen_opval_h_fr;
305 extern CGEN_KEYWORD sh_cgen_opval_h_fp;
306 extern CGEN_KEYWORD sh_cgen_opval_h_fv;
307 extern CGEN_KEYWORD sh_cgen_opval_h_fmtx;
308 extern CGEN_KEYWORD sh_cgen_opval_h_dr;
309 extern CGEN_KEYWORD sh_cgen_opval_h_fsd;
310 extern CGEN_KEYWORD sh_cgen_opval_h_fmov;
311 extern CGEN_KEYWORD sh_cgen_opval_h_tr;
312 extern CGEN_KEYWORD sh_cgen_opval_frc_names;
313 extern CGEN_KEYWORD sh_cgen_opval_drc_names;
314 extern CGEN_KEYWORD sh_cgen_opval_xf_names;
315 extern CGEN_KEYWORD sh_cgen_opval_frc_names;
316 extern CGEN_KEYWORD sh_cgen_opval_h_fvc;
318 extern const CGEN_HW_ENTRY sh_cgen_hw_table[];
322 #endif /* SH_CPU_H */