1 /* Simulator for the Hitachi SH architecture.
3 Written by Steve Chamberlain of Cygnus Support.
6 This file is part of SH sim
9 THIS SOFTWARE IS NOT COPYRIGHTED
11 Cygnus offers the following for use in the public domain. Cygnus
12 makes no warranty with regard to the software or it's performance
13 and the user accepts the software "AS IS" with all faults.
15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
23 #include <sys/times.h>
24 #include <sys/param.h>
26 #include "remote-sim.h"
27 #include "../../newlib/libc/sys/sh/sys/syscall.h"
28 #define O_RECOMPILE 85
31 #define DISASSEMBLER_TABLE
33 #define SBIT(x) ((x)&sbit)
34 #define R0 saved_state.asregs.regs[0]
35 #define Rn saved_state.asregs.regs[n]
36 #define Rm saved_state.asregs.regs[m]
37 #define UR0 (unsigned int)(saved_state.asregs.regs[0])
38 #define UR (unsigned int)R
39 #define UR (unsigned int)R
40 #define SR0 saved_state.asregs.regs[0]
41 #define GBR saved_state.asregs.gbr
42 #define VBR saved_state.asregs.vbr
43 #define MACH saved_state.asregs.mach
44 #define MACL saved_state.asregs.macl
45 #define M saved_state.asregs.sr.bits.m
46 #define Q saved_state.asregs.sr.bits.q
48 #define GET_SR() (saved_state.asregs.sr.bits.t = T, saved_state.asregs.sr.word)
49 #define SET_SR(x) {saved_state.asregs.sr.word = (x); T =saved_state.asregs.sr.bits.t;}
61 #define BUSERROR(addr, mask) \
62 if (addr & ~mask) { saved_state.asregs.exception = SIGBUS;}
64 /* Define this to enable register lifetime checking.
65 The compiler generates "add #0,rn" insns to mark registers as invalid,
66 the simulator uses this info to call fail if it finds a ref to an invalid
74 #define CREF(x) if(!valid[x]) fail();
75 #define CDEF(x) valid[x] = 1;
76 #define UNDEF(x) valid[x] = 0;
89 /* These variables are at file scope so that functions other than
90 sim_resume can use the fetch/store macros */
92 static int little_endian;
95 static int maskl = ~0;
96 static int maskw = ~0;
140 #define PROFILE_FREQ 1
141 #define PROFILE_SHIFT 2
143 unsigned short *profile_hist;
144 unsigned char *memory;
151 saved_state_type saved_state;
154 wlat_little (memory, x, value, maskl)
155 unsigned char *memory;
158 unsigned char *p = memory + ((x) & maskl);
167 wwat_little (memory, x, value, maskw)
168 unsigned char *memory;
171 unsigned char *p = memory + ((x) & maskw);
180 wbat_any (memory, x, value, maskb)
181 unsigned char *memory;
183 unsigned char *p = memory + (x & maskb);
194 wlat_big (memory, x, value, maskl)
195 unsigned char *memory;
198 unsigned char *p = memory + ((x) & maskl);
208 wwat_big (memory, x, value, maskw)
209 unsigned char *memory;
212 unsigned char *p = memory + ((x) & maskw);
221 wbat_big (memory, x, value, maskb)
222 unsigned char *memory;
224 unsigned char *p = memory + (x & maskb);
236 rlat_little (memory, x, maskl)
237 unsigned char *memory;
239 unsigned char *p = memory + ((x) & maskl);
242 return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0];
247 rwat_little (memory, x, maskw)
248 unsigned char *memory;
250 unsigned char *p = memory + ((x) & maskw);
253 return (p[1] << 8) | p[0];
257 rbat_any (memory, x, maskb)
258 unsigned char *memory;
260 unsigned char *p = memory + ((x) & maskb);
267 rlat_big (memory, x, maskl)
268 unsigned char *memory;
270 unsigned char *p = memory + ((x) & maskl);
273 return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3];
278 rwat_big (memory, x, maskw)
279 unsigned char *memory;
281 unsigned char *p = memory + ((x) & maskw);
284 return (p[0] << 8) | p[1];
288 #define RWAT(x) (little_endian ? rwat_little(memory, x, maskw): rwat_big(memory, x, maskw))
289 #define RLAT(x) (little_endian ? rlat_little(memory, x, maskl): rlat_big(memory, x, maskl))
290 #define RBAT(x) (rbat_any (memory, x, maskb))
291 #define WWAT(x,v) (little_endian ? wwat_little(memory, x, v, maskw): wwat_big(memory, x, v, maskw))
292 #define WLAT(x,v) (little_endian ? wlat_little(memory, x, v, maskl): wlat_big(memory, x, v, maskl))
293 #define WBAT(x,v) (wbat_any (memory, x, v, maskb))
295 #define RUWAT(x) (RWAT(x) & 0xffff)
296 #define RSWAT(x) ((short)(RWAT(x)))
297 #define RSBAT(x) (SEXT(RBAT(x)))
299 #define SEXT(x) (((x&0xff) ^ (~0x7f))+0x80)
300 #define SEXTW(y) ((int)((short)y))
302 #define SL(TEMPPC) iword= RUWAT(TEMPPC); goto top;
307 #define L(x) thislock = x;
308 #define TL(x) if ((x) == prevlock) stalls++;
309 #define TB(x,y) if ((x) == prevlock || (y)==prevlock) stalls++;
312 int sim_memory_size = 19;
314 int sim_memory_size = 24;
317 static int sim_profile_size = 17;
323 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
324 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
325 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
326 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
327 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
328 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
330 #define SCI_RDRF 0x40 /* Recieve data register full */
331 #define SCI_TDRE 0x80 /* Transmit data register empty */
334 IOMEM (addr, write, value)
342 static char lastchar;
372 return time ((long *) 0);
383 static FILE *profile_file;
387 unsigned char *memory;
394 unsigned char *memory;
408 fwrite (b, 4, 1, profile_file);
418 fwrite (b, 2, 1, profile_file);
422 /* Turn a pointer in a register into a pointer into real memory. */
428 return (char *) (x + saved_state.asregs.memory);
432 /* Simulate a monitor trap, put the result into r0 and errno into r1 */
434 trap (i, regs, memory, maskl, maskw, little_endian)
437 unsigned char *memory;
442 printf ("%c", regs[0]);
445 saved_state.asregs.exception = SIGQUIT;
449 trap8 (ptr (regs[4]));
452 trap9 (ptr (regs[4]));
479 regs[0] = execve (ptr (regs[5]), ptr (regs[6]), ptr (regs[7]));
482 regs[0] = execv (ptr (regs[5]), ptr (regs[6]));
491 regs[0] = pipe (host_fd);
493 WLAT (buf, host_fd[0]);
495 WLAT (buf, host_fd[1]);
500 regs[0] = wait (ptr (regs[5]));
505 regs[0] = read (regs[5], ptr (regs[6]), regs[7]);
508 regs[0] = write (regs[5], ptr (regs[6]), regs[7]);
511 regs[0] = lseek (regs[5], regs[6], regs[7]);
514 regs[0] = close (regs[5]);
517 regs[0] = open (ptr (regs[5]), regs[6]);
520 /* EXIT - caller can look in r5 to work out the
522 saved_state.asregs.exception = SIGQUIT;
525 case SYS_stat: /* added at hmsi */
526 /* stat system call */
528 struct stat host_stat;
531 regs[0] = stat (ptr (regs[5]), &host_stat);
535 WWAT (buf, host_stat.st_dev);
537 WWAT (buf, host_stat.st_ino);
539 WLAT (buf, host_stat.st_mode);
541 WWAT (buf, host_stat.st_nlink);
543 WWAT (buf, host_stat.st_uid);
545 WWAT (buf, host_stat.st_gid);
547 WWAT (buf, host_stat.st_rdev);
549 WLAT (buf, host_stat.st_size);
551 WLAT (buf, host_stat.st_atime);
555 WLAT (buf, host_stat.st_mtime);
559 WLAT (buf, host_stat.st_ctime);
571 regs[0] = chown (ptr (regs[5]), regs[6], regs[7]);
574 regs[0] = chmod (ptr (regs[5]), regs[6]);
577 regs[0] = utime (ptr (regs[5]), ptr (regs[6]));
590 saved_state.asregs.exception = SIGTRAP;
596 control_c (sig, code, scp, addr)
602 saved_state.asregs.exception = SIGINT;
607 div1 (R, iRn2, iRn1, T)
614 unsigned char old_q, tmp1;
617 Q = (unsigned char) ((0x80000000 & R[iRn1]) != 0);
619 R[iRn1] |= (unsigned long) T;
629 tmp1 = (R[iRn1] > tmp0);
636 Q = (unsigned char) (tmp1 == 0);
643 tmp1 = (R[iRn1] < tmp0);
647 Q = (unsigned char) (tmp1 == 0);
662 tmp1 = (R[iRn1] < tmp0);
669 Q = (unsigned char) (tmp1 == 0);
676 tmp1 = (R[iRn1] > tmp0);
680 Q = (unsigned char) (tmp1 == 0);
701 unsigned long RnL, RnH;
702 unsigned long RmL, RmH;
703 unsigned long temp0, temp1, temp2, temp3;
704 unsigned long Res2, Res1, Res0;
711 RnH = (rn >> 16) & 0xffff;
713 RmH = (rm >> 16) & 0xffff;
719 Res1 = temp1 + temp2;
722 temp1 = (Res1 << 16) & 0xffff0000;
723 Res0 = temp0 + temp1;
726 Res2 += ((Res1 >> 16) & 0xffff) + temp3;
740 MACL = res & 0xffffffff;
749 /* Set the memory size to the power of two provided. */
756 saved_state.asregs.msize = 1 << power;
758 sim_memory_size = power;
761 if (saved_state.asregs.memory)
763 free (saved_state.asregs.memory);
766 saved_state.asregs.memory =
767 (unsigned char *) calloc (64, saved_state.asregs.msize / 64);
769 if (!saved_state.asregs.memory)
772 "Not enough VM for simulation of %d bytes of RAM\n",
773 saved_state.asregs.msize);
775 saved_state.asregs.msize = 1;
776 saved_state.asregs.memory = (unsigned char *) calloc (1, 1);
781 extern int target_byte_order;
784 set_static_little_endian(x)
794 register int little_endian = target_byte_order == 1234;
795 set_static_little_endian (little_endian);
796 if (saved_state.asregs.msize != 1 << sim_memory_size)
798 sim_size (sim_memory_size);
801 if (saved_state.asregs.profile && !profile_file)
803 profile_file = fopen ("gmon.out", "wb");
804 /* Seek to where to put the call arc data */
805 nsamples = (1 << sim_profile_size);
807 fseek (profile_file, nsamples * 2 + 12, 0);
811 fprintf (stderr, "Can't open gmon.out\n");
815 saved_state.asregs.profile_hist =
816 (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64));
830 unsigned short *first;
833 p = saved_state.asregs.profile_hist;
835 maxpc = (1 << sim_profile_size);
837 fseek (profile_file, 0L, 0);
838 swapout (minpc << PROFILE_SHIFT);
839 swapout (maxpc << PROFILE_SHIFT);
840 swapout (nsamples * 2 + 12);
841 for (i = 0; i < nsamples; i++)
842 swapout16 (saved_state.asregs.profile_hist[i]);
856 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
860 sim_resume (step, siggnal)
863 register unsigned int pc;
864 register int cycles = 0;
865 register int stalls = 0;
866 register int insts = 0;
867 register int prevlock;
868 register int thislock;
869 register unsigned int doprofile;
871 register int pollcount = 0;
873 register int little_endian = target_byte_order == 1234;
876 int tick_start = get_now ();
878 extern unsigned char sh_jump_table0[];
880 register unsigned char *jump_table = sh_jump_table0;
882 register int *R = &(saved_state.asregs.regs[0]);
886 register int maskb = ((saved_state.asregs.msize - 1) & ~0);
887 register int maskw = ((saved_state.asregs.msize - 1) & ~1);
888 register int maskl = ((saved_state.asregs.msize - 1) & ~3);
889 register unsigned char *memory;
890 register unsigned int sbit = (1 << 31);
892 prev = signal (SIGINT, control_c);
896 memory = saved_state.asregs.memory;
900 saved_state.asregs.exception = SIGTRAP;
904 saved_state.asregs.exception = 0;
907 pc = saved_state.asregs.pc;
908 PR = saved_state.asregs.pr;
909 T = saved_state.asregs.sr.bits.t;
910 prevlock = saved_state.asregs.prevlock;
911 thislock = saved_state.asregs.thislock;
912 doprofile = saved_state.asregs.profile;
914 /* If profiling not enabled, disable it by asking for
915 profiles infrequently. */
921 register unsigned int iword = RUWAT (pc);
922 register unsigned int ult;
935 if (pollcount > 1000)
941 saved_state.asregs.exception = SIGINT;
952 if (cycles >= doprofile)
955 saved_state.asregs.cycles += doprofile;
957 if (saved_state.asregs.profile_hist)
959 int n = pc >> PROFILE_SHIFT;
962 int i = saved_state.asregs.profile_hist[n];
964 saved_state.asregs.profile_hist[n] = i + 1;
971 while (!saved_state.asregs.exception);
973 if (saved_state.asregs.exception == SIGILL
974 || saved_state.asregs.exception == SIGBUS
975 || (saved_state.asregs.exception == SIGTRAP && !step))
980 saved_state.asregs.ticks += get_now () - tick_start;
981 saved_state.asregs.cycles += cycles;
982 saved_state.asregs.stalls += stalls;
983 saved_state.asregs.insts += insts;
984 saved_state.asregs.pc = pc;
985 saved_state.asregs.sr.bits.t = T;
986 saved_state.asregs.pr = PR;
988 saved_state.asregs.prevlock = prevlock;
989 saved_state.asregs.thislock = thislock;
997 signal (SIGINT, prev);
1004 sim_write (addr, buffer, size)
1006 unsigned char *buffer;
1012 for (i = 0; i < size; i++)
1014 saved_state.asregs.memory[MMASKB & (addr + i)] = buffer[i];
1020 sim_read (addr, buffer, size)
1022 unsigned char *buffer;
1029 for (i = 0; i < size; i++)
1031 buffer[i] = saved_state.asregs.memory[MMASKB & (addr + i)];
1038 sim_store_register (rn, memory)
1040 unsigned char *memory;
1043 saved_state.asregs.regs[rn]=RLAT(0);
1047 sim_fetch_register (rn, memory)
1049 unsigned char *memory;
1052 WLAT (0, saved_state.asregs.regs[rn]);
1063 sim_stop_reason (reason, sigrc)
1064 enum sim_stop *reason;
1067 *reason = sim_stopped;
1068 *sigrc = saved_state.asregs.exception;
1076 double timetaken = (double) saved_state.asregs.ticks / (double) now_persec ();
1077 double virttime = saved_state.asregs.cycles / 36.0e6;
1079 printf_filtered ("\n\n# instructions executed %10d\n", saved_state.asregs.insts);
1080 printf_filtered ("# cycles %10d\n", saved_state.asregs.cycles);
1081 printf_filtered ("# pipeline stalls %10d\n", saved_state.asregs.stalls);
1082 printf_filtered ("# real time taken %10.4f\n", timetaken);
1083 printf_filtered ("# virtual time taken %10.4f\n", virttime);
1084 printf_filtered ("# profiling size %10d\n", sim_profile_size);
1085 printf_filtered ("# profiling frequency %10d\n", saved_state.asregs.profile);
1086 printf_filtered ("# profile maxpc %10x\n", (1 << sim_profile_size) << PROFILE_SHIFT);
1090 printf_filtered ("# cycles/second %10d\n", (int) (saved_state.asregs.cycles / timetaken));
1091 printf_filtered ("# simulation ratio %10.4f\n", virttime / timetaken);
1100 saved_state.asregs.profile = n;
1104 sim_set_profile_size (n)
1107 sim_profile_size = n;
1119 sim_close (quitting)
1126 sim_load (prog, from_tty)
1130 /* Return nonzero so GDB will handle it. */
1135 sim_create_inferior (start_address, argv, env)
1136 SIM_ADDR start_address;
1140 saved_state.asregs.pc = start_address;