1 /* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture.
3 Written by Steve Chamberlain of Cygnus Support.
6 This file is part of SH sim
9 THIS SOFTWARE IS NOT COPYRIGHTED
11 Cygnus offers the following for use in the public domain. Cygnus
12 makes no warranty with regard to the software or it's performance
13 and the user accepts the software "AS IS" with all faults.
15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
33 # define MAP_FAILED -1
35 # if !defined (MAP_ANONYMOUS) && defined (MAP_ANON)
36 # define MAP_ANONYMOUS MAP_ANON
52 #ifdef HAVE_SYS_STAT_H
58 #ifdef HAVE_SYS_TIME_H
67 #include "gdb/callback.h"
68 #include "gdb/remote-sim.h"
69 #include "gdb/sim-sh.h"
73 #include "sim-options.h"
75 /* This file is local - if newlib changes, then so should this. */
81 #include <float.h> /* Needed for _isnan() */
86 #define SIGBUS SIGSEGV
90 #define SIGQUIT SIGTERM
97 /* TODO: Stop using these names. */
101 extern unsigned short sh_jump_table[], sh_dsp_table[0x1000], ppi_table[];
103 #define O_RECOMPILE 85
105 #define DISASSEMBLER_TABLE
107 /* Define the rate at which the simulator should poll the host
109 #define POLL_QUIT_INTERVAL 0x60000
111 /* TODO: Move into sim_cpu. */
112 saved_state_type saved_state;
114 struct loop_bounds { unsigned char *start, *end; };
116 /* These variables are at file scope so that functions other than
117 sim_resume can use the fetch/store macros */
119 #define target_little_endian (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
120 static int global_endianw, endianb;
121 static int target_dsp;
122 #define host_little_endian (HOST_BYTE_ORDER == BFD_ENDIAN_LITTLE)
124 static int maskw = 0;
125 static int maskl = 0;
127 /* Short hand definitions of the registers */
129 #define SBIT(x) ((x)&sbit)
130 #define R0 saved_state.asregs.regs[0]
131 #define Rn saved_state.asregs.regs[n]
132 #define Rm saved_state.asregs.regs[m]
133 #define UR0 (unsigned int) (saved_state.asregs.regs[0])
134 #define UR (unsigned int) R
135 #define UR (unsigned int) R
136 #define SR0 saved_state.asregs.regs[0]
137 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
138 #define GBR saved_state.asregs.cregs.named.gbr
139 #define VBR saved_state.asregs.cregs.named.vbr
140 #define DBR saved_state.asregs.cregs.named.dbr
141 #define TBR saved_state.asregs.cregs.named.tbr
142 #define IBCR saved_state.asregs.cregs.named.ibcr
143 #define IBNR saved_state.asregs.cregs.named.ibnr
144 #define BANKN (saved_state.asregs.cregs.named.ibnr & 0x1ff)
145 #define ME ((saved_state.asregs.cregs.named.ibnr >> 14) & 0x3)
146 #define SSR saved_state.asregs.cregs.named.ssr
147 #define SPC saved_state.asregs.cregs.named.spc
148 #define SGR saved_state.asregs.cregs.named.sgr
149 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
150 #define MACH saved_state.asregs.sregs.named.mach
151 #define MACL saved_state.asregs.sregs.named.macl
152 #define PR saved_state.asregs.sregs.named.pr
153 #define FPUL saved_state.asregs.sregs.named.fpul
159 /* Alternate bank of registers r0-r7 */
161 /* Note: code controling SR handles flips between BANK0 and BANK1 */
162 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
163 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
168 #define SR_MASK_BO (1 << 14)
169 #define SR_MASK_CS (1 << 13)
170 #define SR_MASK_DMY (1 << 11)
171 #define SR_MASK_DMX (1 << 10)
172 #define SR_MASK_M (1 << 9)
173 #define SR_MASK_Q (1 << 8)
174 #define SR_MASK_I (0xf << 4)
175 #define SR_MASK_S (1 << 1)
176 #define SR_MASK_T (1 << 0)
178 #define SR_MASK_BL (1 << 28)
179 #define SR_MASK_RB (1 << 29)
180 #define SR_MASK_MD (1 << 30)
181 #define SR_MASK_RC 0x0fff0000
182 #define SR_RC_INCREMENT -0x00010000
184 #define BO ((saved_state.asregs.cregs.named.sr & SR_MASK_BO) != 0)
185 #define CS ((saved_state.asregs.cregs.named.sr & SR_MASK_CS) != 0)
186 #define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
187 #define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
188 #define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
189 #define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
190 #define LDST ((saved_state.asregs.cregs.named.ldst) != 0)
192 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
193 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
194 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
195 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
196 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
197 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
199 /* Note: don't use this for privileged bits */
200 #define SET_SR_BIT(EXP, BIT) \
203 saved_state.asregs.cregs.named.sr |= (BIT); \
205 saved_state.asregs.cregs.named.sr &= ~(BIT); \
208 #define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO)
209 #define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
210 #define SET_BANKN(EXP) \
212 IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \
214 #define SET_ME(EXP) \
216 IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \
218 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
219 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
220 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
221 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
222 #define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0))
224 /* stc currently relies on being able to read SR without modifications. */
225 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
227 #define SET_SR(x) set_sr (x)
230 (saved_state.asregs.cregs.named.sr \
231 = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
233 /* Manipulate FPSCR */
235 #define FPSCR_MASK_FR (1 << 21)
236 #define FPSCR_MASK_SZ (1 << 20)
237 #define FPSCR_MASK_PR (1 << 19)
239 #define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0)
240 #define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0)
241 #define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0)
246 int old = saved_state.asregs.sregs.named.fpscr;
247 saved_state.asregs.sregs.named.fpscr = (x);
248 /* swap the floating point register banks */
249 if ((saved_state.asregs.sregs.named.fpscr ^ old) & FPSCR_MASK_FR
250 /* Ignore bit change if simulating sh-dsp. */
253 union fregs_u tmpf = saved_state.asregs.fregs[0];
254 saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1];
255 saved_state.asregs.fregs[1] = tmpf;
259 /* sts relies on being able to read fpscr directly. */
260 #define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr)
261 #define SET_FPSCR(x) \
266 #define DSR (saved_state.asregs.sregs.named.fpscr)
268 #define RAISE_EXCEPTION(x) \
269 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
271 #define RAISE_EXCEPTION_IF_IN_DELAY_SLOT() \
272 if (in_delay_slot) RAISE_EXCEPTION (SIGILL)
274 /* This function exists mainly for the purpose of setting a breakpoint to
275 catch simulated bus errors when running the simulator under GDB. */
278 raise_exception (int x)
284 raise_buserror (void)
286 raise_exception (SIGBUS);
289 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
290 forbidden_addr_bits, data, retval) \
292 if (addr & forbidden_addr_bits) \
297 else if ((addr & saved_state.asregs.xyram_select) \
298 == saved_state.asregs.xram_start) \
299 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
300 else if ((addr & saved_state.asregs.xyram_select) \
301 == saved_state.asregs.yram_start) \
302 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
303 else if ((unsigned) addr >> 24 == 0xf0 \
304 && bits_written == 32 && (data & 1) == 0) \
305 /* This invalidates (if not associative) or might invalidate \
306 (if associative) an instruction cache line. This is used for \
307 trampolines. Since we don't simulate the cache, this is a no-op \
308 as far as the simulator is concerned. */ \
312 if (bits_written == 8 && addr > 0x5000000) \
313 IOMEM (addr, 1, data); \
314 /* We can't do anything useful with the other stuff, so fail. */ \
320 /* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
321 being implemented by ../common/sim_resume.c and the below should
322 make a call to sim_engine_halt */
324 #define BUSERROR(addr, mask) ((addr) & (mask))
326 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
331 addr_func (addr, data); \
337 #define READ_BUSERROR(addr, mask, addr_func) \
341 return addr_func (addr); \
345 /* Define this to enable register lifetime checking.
346 The compiler generates "add #0,rn" insns to mark registers as invalid,
347 the simulator uses this info to call fail if it finds a ref to an invalid
348 register before a def
355 #define CREF(x) if (!valid[x]) fail ();
356 #define CDEF(x) valid[x] = 1;
357 #define UNDEF(x) valid[x] = 0;
364 static void parse_and_set_memory_size (SIM_DESC sd, const char *str);
365 static int IOMEM (int addr, int write, int value);
366 static struct loop_bounds get_loop_bounds (int, int, unsigned char *,
367 unsigned char *, int, int);
368 static void process_wlat_addr (int, int);
369 static void process_wwat_addr (int, int);
370 static void process_wbat_addr (int, int);
371 static int process_rlat_addr (int);
372 static int process_rwat_addr (int);
373 static int process_rbat_addr (int);
375 /* Floating point registers */
377 #define DR(n) (get_dr (n))
382 if (host_little_endian)
389 dr.i[1] = saved_state.asregs.fregs[0].i[n + 0];
390 dr.i[0] = saved_state.asregs.fregs[0].i[n + 1];
394 return (saved_state.asregs.fregs[0].d[n >> 1]);
397 #define SET_DR(n, EXP) set_dr ((n), (EXP))
399 set_dr (int n, double exp)
402 if (host_little_endian)
410 saved_state.asregs.fregs[0].i[n + 0] = dr.i[1];
411 saved_state.asregs.fregs[0].i[n + 1] = dr.i[0];
414 saved_state.asregs.fregs[0].d[n >> 1] = exp;
417 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
418 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
420 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
421 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
423 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
424 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
425 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
427 #define RS saved_state.asregs.cregs.named.rs
428 #define RE saved_state.asregs.cregs.named.re
429 #define MOD (saved_state.asregs.cregs.named.mod)
432 MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
433 MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
435 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
436 #define DSP_GRD(n) DSP_R ((n) + 8)
437 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
442 #define Y0 DSP_R (10)
443 #define Y1 DSP_R (11)
444 #define M0 DSP_R (12)
445 #define A1G DSP_R (13)
446 #define M1 DSP_R (14)
447 #define A0G DSP_R (15)
448 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */
449 #define MOD_ME DSP_GRD (17)
450 #define MOD_DELTA DSP_GRD (18)
452 #define FP_OP(n, OP, m) \
456 if (((n) & 1) || ((m) & 1)) \
457 RAISE_EXCEPTION (SIGILL); \
459 SET_DR (n, (DR (n) OP DR (m))); \
462 SET_FR (n, (FR (n) OP FR (m))); \
465 #define FP_UNARY(n, OP) \
470 RAISE_EXCEPTION (SIGILL); \
472 SET_DR (n, (OP (DR (n)))); \
475 SET_FR (n, (OP (FR (n)))); \
478 #define FP_CMP(n, OP, m) \
482 if (((n) & 1) || ((m) & 1)) \
483 RAISE_EXCEPTION (SIGILL); \
485 SET_SR_T (DR (n) OP DR (m)); \
488 SET_SR_T (FR (n) OP FR (m)); \
494 /* do we need to swap banks */
495 int old_gpr = SR_MD && SR_RB;
496 int new_gpr = (new_sr & SR_MASK_MD) && (new_sr & SR_MASK_RB);
497 if (old_gpr != new_gpr)
500 for (i = 0; i < 8; i++)
502 tmp = saved_state.asregs.cregs.named.bank[i];
503 saved_state.asregs.cregs.named.bank[i] = saved_state.asregs.regs[i];
504 saved_state.asregs.regs[i] = tmp;
507 saved_state.asregs.cregs.named.sr = new_sr;
512 wlat_fast (unsigned char *memory, int x, int value, int maskl)
515 unsigned int *p = (unsigned int *) (memory + x);
516 WRITE_BUSERROR (x, maskl, v, process_wlat_addr);
521 wwat_fast (unsigned char *memory, int x, int value, int maskw, int endianw)
524 unsigned short *p = (unsigned short *) (memory + (x ^ endianw));
525 WRITE_BUSERROR (x, maskw, v, process_wwat_addr);
530 wbat_fast (unsigned char *memory, int x, int value, int maskb)
532 unsigned char *p = memory + (x ^ endianb);
533 WRITE_BUSERROR (x, maskb, value, process_wbat_addr);
541 rlat_fast (unsigned char *memory, int x, int maskl)
543 unsigned int *p = (unsigned int *) (memory + x);
544 READ_BUSERROR (x, maskl, process_rlat_addr);
550 rwat_fast (unsigned char *memory, int x, int maskw, int endianw)
552 unsigned short *p = (unsigned short *) (memory + (x ^ endianw));
553 READ_BUSERROR (x, maskw, process_rwat_addr);
559 riat_fast (unsigned char *insn_ptr, int endianw)
561 unsigned short *p = (unsigned short *) ((size_t) insn_ptr ^ endianw);
567 rbat_fast (unsigned char *memory, int x, int maskb)
569 unsigned char *p = memory + (x ^ endianb);
570 READ_BUSERROR (x, maskb, process_rbat_addr);
575 #define RWAT(x) (rwat_fast (memory, x, maskw, endianw))
576 #define RLAT(x) (rlat_fast (memory, x, maskl))
577 #define RBAT(x) (rbat_fast (memory, x, maskb))
578 #define RIAT(p) (riat_fast ((p), endianw))
579 #define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw))
580 #define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
581 #define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
583 #define RUWAT(x) (RWAT (x) & 0xffff)
584 #define RSWAT(x) ((short) (RWAT (x)))
585 #define RSLAT(x) ((long) (RLAT (x)))
586 #define RSBAT(x) (SEXT (RBAT (x)))
588 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
590 do_rdat (unsigned char *memory, int x, int n, int maskl)
596 f0 = rlat_fast (memory, x + 0, maskl);
597 f1 = rlat_fast (memory, x + 4, maskl);
598 saved_state.asregs.fregs[i].i[(j + 0)] = f0;
599 saved_state.asregs.fregs[i].i[(j + 1)] = f1;
603 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
605 do_wdat (unsigned char *memory, int x, int n, int maskl)
611 f0 = saved_state.asregs.fregs[i].i[(j + 0)];
612 f1 = saved_state.asregs.fregs[i].i[(j + 1)];
613 wlat_fast (memory, (x + 0), f0, maskl);
614 wlat_fast (memory, (x + 4), f1, maskl);
619 process_wlat_addr (int addr, int value)
623 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 32, 3, value, );
628 process_wwat_addr (int addr, int value)
632 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 16, 1, value, );
637 process_wbat_addr (int addr, int value)
641 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 8, 0, value, );
646 process_rlat_addr (int addr)
650 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -32, 3, -1, 0);
655 process_rwat_addr (int addr)
659 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -16, 1, -1, 0);
664 process_rbat_addr (int addr)
668 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -8, 0, -1, 0);
672 #define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
673 #define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
674 #define SEXTW(y) ((int) ((short) y))
676 #define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
678 #define SEXT32(x) ((int) (x))
680 #define SIGN32(x) (SEXT32 (x) >> 31)
682 /* convert pointer from target to host value. */
683 #define PT2H(x) ((x) + memory)
684 /* convert pointer from host to target value. */
685 #define PH2T(x) ((x) - memory)
687 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
689 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
691 static int in_delay_slot = 0;
692 #define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); in_delay_slot = 1; goto top;
694 #define CHECK_INSN_PTR(p) \
696 if (saved_state.asregs.exception || PH2T (p) & maskw) \
697 saved_state.asregs.insn_end = 0; \
698 else if (p < loop.end) \
699 saved_state.asregs.insn_end = loop.end; \
701 saved_state.asregs.insn_end = mem_end; \
714 do { memstalls += ((((long) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
716 #define L(x) thislock = x;
717 #define TL(x) if ((x) == prevlock) stalls++;
718 #define TB(x,y) if ((x) == prevlock || (y) == prevlock) stalls++;
722 #if defined(__GO32__)
723 int sim_memory_size = 19;
725 int sim_memory_size = 24;
728 static int sim_profile_size = 17;
734 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
735 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
736 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
737 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
738 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
739 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
741 #define SCI_RDRF 0x40 /* Recieve data register full */
742 #define SCI_TDRE 0x80 /* Transmit data register empty */
745 IOMEM (int addr, int write, int value)
774 return time ((long *) 0);
783 static FILE *profile_file;
785 static INLINE unsigned
789 n = (n << 24 | (n & 0xff00) << 8
790 | (n & 0xff0000) >> 8 | (n & 0xff000000) >> 24);
794 static INLINE unsigned short
795 swap16 (unsigned short n)
798 n = n << 8 | (n & 0xff00) >> 8;
807 union { char b[4]; int n; } u;
809 fwrite (u.b, 4, 1, profile_file);
816 union { char b[4]; int n; } u;
818 fwrite (u.b, 2, 1, profile_file);
821 /* Turn a pointer in a register into a pointer into real memory. */
826 return (char *) (x + saved_state.asregs.memory);
829 /* STR points to a zero-terminated string in target byte order. Return
830 the number of bytes that need to be converted to host byte order in order
831 to use this string as a zero-terminated string on the host.
832 (Not counting the rounding up needed to operate on entire words.) */
836 unsigned char *memory = saved_state.asregs.memory;
838 int endian = endianb;
843 for (end = str; memory[end ^ endian]; end++) ;
844 return end - str + 1;
848 strnswap (int str, int len)
852 if (! endianb || ! len)
854 start = (int *) ptr (str & ~3);
855 end = (int *) ptr (str + len);
859 *start = (old << 24 | (old & 0xff00) << 8
860 | (old & 0xff0000) >> 8 | (old & 0xff000000) >> 24);
866 /* Simulate a monitor trap, put the result into r0 and errno into r1
867 return offset by which to adjust pc. */
870 trap (SIM_DESC sd, int i, int *regs, unsigned char *insn_ptr,
871 unsigned char *memory, int maskl, int maskw, int endianw)
873 host_callback *callback = STATE_CALLBACK (sd);
874 char **prog_argv = STATE_PROG_ARGV (sd);
879 printf ("%c", regs[0]);
882 raise_exception (SIGQUIT);
884 case 3: /* FIXME: for backwards compat, should be removed */
887 unsigned int countp = * (unsigned int *) (insn_ptr + 4);
889 WLAT (countp, RLAT (countp) + 1);
901 #if !defined(__GO32__) && !defined(_WIN32)
905 /* This would work only if endianness matched between host and target.
906 Besides, it's quite dangerous. */
909 regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]),
910 (char **) ptr (regs[7]));
913 regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]), 0);
918 regs[0] = (BUSERROR (regs[5], maskl)
920 : pipe ((int *) ptr (regs[5])));
925 regs[0] = wait ((int *) ptr (regs[5]));
927 #endif /* !defined(__GO32__) && !defined(_WIN32) */
930 strnswap (regs[6], regs[7]);
932 = callback->read (callback, regs[5], ptr (regs[6]), regs[7]);
933 strnswap (regs[6], regs[7]);
936 strnswap (regs[6], regs[7]);
938 regs[0] = (int) callback->write_stdout (callback,
939 ptr (regs[6]), regs[7]);
941 regs[0] = (int) callback->write (callback, regs[5],
942 ptr (regs[6]), regs[7]);
943 strnswap (regs[6], regs[7]);
946 regs[0] = callback->lseek (callback,regs[5], regs[6], regs[7]);
949 regs[0] = callback->close (callback,regs[5]);
953 int len = strswaplen (regs[5]);
954 strnswap (regs[5], len);
955 regs[0] = callback->open (callback, ptr (regs[5]), regs[6]);
956 strnswap (regs[5], len);
960 /* EXIT - caller can look in r5 to work out the reason */
961 raise_exception (SIGQUIT);
965 case SYS_stat: /* added at hmsi */
966 /* stat system call */
968 struct stat host_stat;
970 int len = strswaplen (regs[5]);
972 strnswap (regs[5], len);
973 regs[0] = stat (ptr (regs[5]), &host_stat);
974 strnswap (regs[5], len);
978 WWAT (buf, host_stat.st_dev);
980 WWAT (buf, host_stat.st_ino);
982 WLAT (buf, host_stat.st_mode);
984 WWAT (buf, host_stat.st_nlink);
986 WWAT (buf, host_stat.st_uid);
988 WWAT (buf, host_stat.st_gid);
990 WWAT (buf, host_stat.st_rdev);
992 WLAT (buf, host_stat.st_size);
994 WLAT (buf, host_stat.st_atime);
998 WLAT (buf, host_stat.st_mtime);
1002 WLAT (buf, host_stat.st_ctime);
1016 int len = strswaplen (regs[5]);
1018 strnswap (regs[5], len);
1019 regs[0] = chown (ptr (regs[5]), regs[6], regs[7]);
1020 strnswap (regs[5], len);
1026 int len = strswaplen (regs[5]);
1028 strnswap (regs[5], len);
1029 regs[0] = chmod (ptr (regs[5]), regs[6]);
1030 strnswap (regs[5], len);
1035 /* Cast the second argument to void *, to avoid type mismatch
1036 if a prototype is present. */
1037 int len = strswaplen (regs[5]);
1039 strnswap (regs[5], len);
1040 regs[0] = utime (ptr (regs[5]), (void *) ptr (regs[6]));
1041 strnswap (regs[5], len);
1045 regs[0] = countargv (prog_argv);
1048 if (regs[5] < countargv (prog_argv))
1049 regs[0] = strlen (prog_argv[regs[5]]);
1054 if (regs[5] < countargv (prog_argv))
1056 /* Include the termination byte. */
1057 int i = strlen (prog_argv[regs[5]]) + 1;
1058 regs[0] = sim_write (0, regs[6], (void *) prog_argv[regs[5]], i);
1064 regs[0] = get_now ();
1067 regs[0] = callback->ftruncate (callback, regs[5], regs[6]);
1071 int len = strswaplen (regs[5]);
1072 strnswap (regs[5], len);
1073 regs[0] = callback->truncate (callback, ptr (regs[5]), regs[6]);
1074 strnswap (regs[5], len);
1081 regs[1] = callback->get_errno (callback);
1086 case 13: /* Set IBNR */
1087 IBNR = regs[0] & 0xffff;
1089 case 14: /* Set IBCR */
1090 IBCR = regs[0] & 0xffff;
1094 raise_exception (SIGTRAP);
1103 div1 (int *R, int iRn2, int iRn1/*, int T*/)
1106 unsigned char old_q, tmp1;
1109 SET_SR_Q ((unsigned char) ((0x80000000 & R[iRn1]) != 0));
1111 R[iRn1] |= (unsigned long) T;
1121 tmp1 = (R[iRn1] > tmp0);
1128 SET_SR_Q ((unsigned char) (tmp1 == 0));
1135 tmp1 = (R[iRn1] < tmp0);
1139 SET_SR_Q ((unsigned char) (tmp1 == 0));
1154 tmp1 = (R[iRn1] < tmp0);
1161 SET_SR_Q ((unsigned char) (tmp1 == 0));
1168 tmp1 = (R[iRn1] > tmp0);
1172 SET_SR_Q ((unsigned char) (tmp1 == 0));
1188 dmul (int sign, unsigned int rm, unsigned int rn)
1190 unsigned long RnL, RnH;
1191 unsigned long RmL, RmH;
1192 unsigned long temp0, temp1, temp2, temp3;
1193 unsigned long Res2, Res1, Res0;
1196 RnH = (rn >> 16) & 0xffff;
1198 RmH = (rm >> 16) & 0xffff;
1204 Res1 = temp1 + temp2;
1207 temp1 = (Res1 << 16) & 0xffff0000;
1208 Res0 = temp0 + temp1;
1211 Res2 += ((Res1 >> 16) & 0xffff) + temp3;
1215 if (rn & 0x80000000)
1217 if (rm & 0x80000000)
1226 macw (int *regs, unsigned char *memory, int n, int m, int endianw)
1229 long prod, macl, sum;
1231 tempm=RSWAT (regs[m]); regs[m]+=2;
1232 tempn=RSWAT (regs[n]); regs[n]+=2;
1235 prod = (long) (short) tempm * (long) (short) tempn;
1239 if ((~(prod ^ macl) & (sum ^ prod)) < 0)
1241 /* MACH's lsb is a sticky overflow bit. */
1243 /* Store the smallest negative number in MACL if prod is
1244 negative, and the largest positive number otherwise. */
1245 sum = 0x7fffffff + (prod < 0);
1251 /* Add to MACH the sign extended product, and carry from low sum. */
1252 mach = MACH + (-(prod < 0)) + ((unsigned long) sum < prod);
1253 /* Sign extend at 10:th bit in MACH. */
1254 MACH = (mach & 0x1ff) | -(mach & 0x200);
1260 macl (int *regs, unsigned char *memory, int n, int m)
1267 tempm = RSLAT (regs[m]);
1270 tempn = RSLAT (regs[n]);
1276 mac64 = ((long long) macl & 0xffffffff) |
1277 ((long long) mach & 0xffffffff) << 32;
1279 ans = (long long) tempm * (long long) tempn; /* Multiply 32bit * 32bit */
1281 mac64 += ans; /* Accumulate 64bit + 64 bit */
1283 macl = (long) (mac64 & 0xffffffff);
1284 mach = (long) ((mac64 >> 32) & 0xffffffff);
1286 if (S) /* Store only 48 bits of the result */
1288 if (mach < 0) /* Result is negative */
1290 mach = mach & 0x0000ffff; /* Mask higher 16 bits */
1291 mach |= 0xffff8000; /* Sign extend higher 16 bits */
1294 mach = mach & 0x00007fff; /* Postive Result */
1325 /* Do extended displacement move instructions. */
1327 do_long_move_insn (int op, int disp12, int m, int n, int *thatlock)
1330 int thislock = *thatlock;
1331 int endianw = global_endianw;
1332 int *R = &(saved_state.asregs.regs[0]);
1333 unsigned char *memory = saved_state.asregs.memory;
1334 int maskb = ~((saved_state.asregs.msize - 1) & ~0);
1335 unsigned char *insn_ptr = PT2H (saved_state.asregs.pc);
1338 case MOVB_RM: /* signed */
1339 WBAT (disp12 * 1 + R[n], R[m]);
1342 WWAT (disp12 * 2 + R[n], R[m]);
1345 WLAT (disp12 * 4 + R[n], R[m]);
1347 case FMOV_RM: /* floating point */
1351 WDAT (R[n] + 8 * disp12, m);
1354 WLAT (R[n] + 4 * disp12, FI (m));
1357 R[n] = RSBAT (disp12 * 1 + R[m]);
1361 R[n] = RSWAT (disp12 * 2 + R[m]);
1365 R[n] = RLAT (disp12 * 4 + R[m]);
1371 RDAT (R[m] + 8 * disp12, n);
1374 SET_FI (n, RLAT (R[m] + 4 * disp12));
1376 case MOVU_BMR: /* unsigned */
1377 R[n] = RBAT (disp12 * 1 + R[m]);
1381 R[n] = RWAT (disp12 * 2 + R[m]);
1385 RAISE_EXCEPTION (SIGINT);
1388 saved_state.asregs.memstalls += memstalls;
1389 *thatlock = thislock;
1392 /* Do binary logical bit-manipulation insns. */
1394 do_blog_insn (int imm, int addr, int binop,
1395 unsigned char *memory, int maskb)
1397 int oldval = RBAT (addr);
1400 case B_BCLR: /* bclr.b */
1401 WBAT (addr, oldval & ~imm);
1403 case B_BSET: /* bset.b */
1404 WBAT (addr, oldval | imm);
1406 case B_BST: /* bst.b */
1408 WBAT (addr, oldval | imm);
1410 WBAT (addr, oldval & ~imm);
1412 case B_BLD: /* bld.b */
1413 SET_SR_T ((oldval & imm) != 0);
1415 case B_BAND: /* band.b */
1416 SET_SR_T (T && ((oldval & imm) != 0));
1418 case B_BOR: /* bor.b */
1419 SET_SR_T (T || ((oldval & imm) != 0));
1421 case B_BXOR: /* bxor.b */
1422 SET_SR_T (T ^ ((oldval & imm) != 0));
1424 case B_BLDNOT: /* bldnot.b */
1425 SET_SR_T ((oldval & imm) == 0);
1427 case B_BANDNOT: /* bandnot.b */
1428 SET_SR_T (T && ((oldval & imm) == 0));
1430 case B_BORNOT: /* bornot.b */
1431 SET_SR_T (T || ((oldval & imm) == 0));
1437 fsca_s (int in, double (*f) (double))
1439 double rad = ldexp ((in & 0xffff), -15) * 3.141592653589793238462643383;
1440 double result = (*f) (rad);
1441 double error, upper, lower, frac;
1444 /* Search the value with the maximum error that is still within the
1445 architectural spec. */
1446 error = ldexp (1., -21);
1447 /* compensate for calculation inaccuracy by reducing error. */
1448 error = error - ldexp (1., -50);
1449 upper = result + error;
1450 frac = frexp (upper, &exp);
1451 upper = ldexp (floor (ldexp (frac, 24)), exp - 24);
1452 lower = result - error;
1453 frac = frexp (lower, &exp);
1454 lower = ldexp (ceil (ldexp (frac, 24)), exp - 24);
1455 return abs (upper - result) >= abs (lower - result) ? upper : lower;
1461 double result = 1. / sqrt (in);
1463 double frac, upper, lower, error, eps;
1466 result = result - (result * result * in - 1) * 0.5 * result;
1467 /* Search the value with the maximum error that is still within the
1468 architectural spec. */
1469 frac = frexp (result, &exp);
1470 frac = ldexp (frac, 24);
1471 error = 4.0; /* 1 << 24-1-21 */
1472 /* use eps to compensate for possible 1 ulp error in our 'exact' result. */
1473 eps = ldexp (1., -29);
1474 upper = floor (frac + error - eps);
1475 if (upper > 16777216.)
1476 upper = floor ((frac + error - eps) * 0.5) * 2.;
1477 lower = ceil ((frac - error + eps) * 2) * .5;
1478 if (lower > 8388608.)
1479 lower = ceil (frac - error + eps);
1480 upper = ldexp (upper, exp - 24);
1481 lower = ldexp (lower, exp - 24);
1482 return upper - result >= result - lower ? upper : lower;
1486 /* GET_LOOP_BOUNDS {EXTENDED}
1487 These two functions compute the actual starting and ending point
1488 of the repeat loop, based on the RS and RE registers (repeat start,
1489 repeat stop). The extended version is called for LDRC, and the
1490 regular version is called for SETRC. The difference is that for
1491 LDRC, the loop start and end instructions are literally the ones
1492 pointed to by RS and RE -- for SETRC, they're not (see docs). */
1494 static struct loop_bounds
1495 get_loop_bounds_ext (int rs, int re, unsigned char *memory,
1496 unsigned char *mem_end, int maskw, int endianw)
1498 struct loop_bounds loop;
1500 /* FIXME: should I verify RS < RE? */
1501 loop.start = PT2H (RS); /* FIXME not using the params? */
1502 loop.end = PT2H (RE & ~1); /* Ignore bit 0 of RE. */
1503 SKIP_INSN (loop.end);
1504 if (loop.end >= mem_end)
1505 loop.end = PT2H (0);
1509 static struct loop_bounds
1510 get_loop_bounds (int rs, int re, unsigned char *memory, unsigned char *mem_end,
1511 int maskw, int endianw)
1513 struct loop_bounds loop;
1519 loop.start = PT2H (RE - 4);
1520 SKIP_INSN (loop.start);
1521 loop.end = loop.start;
1523 SKIP_INSN (loop.end);
1525 SKIP_INSN (loop.end);
1526 SKIP_INSN (loop.end);
1530 loop.start = PT2H (RS);
1531 loop.end = PT2H (RE - 4);
1532 SKIP_INSN (loop.end);
1533 SKIP_INSN (loop.end);
1534 SKIP_INSN (loop.end);
1535 SKIP_INSN (loop.end);
1537 if (loop.end >= mem_end)
1538 loop.end = PT2H (0);
1541 loop.end = PT2H (0);
1546 static void ppi_insn ();
1550 /* Provide calloc / free versions that use an anonymous mmap. This can
1551 significantly cut the start-up time when a large simulator memory is
1552 required, because pages are only zeroed on demand. */
1553 #ifdef MAP_ANONYMOUS
1555 mcalloc (size_t nmemb, size_t size)
1561 return mmap (0, size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS,
1565 #define mfree(start,length) munmap ((start), (length))
1567 #define mcalloc calloc
1568 #define mfree(start,length) free(start)
1571 /* Set the memory size to the power of two provided. */
1574 sim_size (int power)
1576 sim_memory_size = power;
1578 if (saved_state.asregs.memory)
1580 mfree (saved_state.asregs.memory, saved_state.asregs.msize);
1583 saved_state.asregs.msize = 1 << power;
1585 saved_state.asregs.memory =
1586 (unsigned char *) mcalloc (1, saved_state.asregs.msize);
1588 if (!saved_state.asregs.memory)
1591 "Not enough VM for simulation of %d bytes of RAM\n",
1592 saved_state.asregs.msize);
1594 saved_state.asregs.msize = 1;
1595 saved_state.asregs.memory = (unsigned char *) mcalloc (1, 1);
1600 init_dsp (struct bfd *abfd)
1602 int was_dsp = target_dsp;
1603 unsigned long mach = bfd_get_mach (abfd);
1605 if (mach == bfd_mach_sh_dsp ||
1606 mach == bfd_mach_sh4al_dsp ||
1607 mach == bfd_mach_sh3_dsp)
1609 int ram_area_size, xram_start, yram_start;
1613 if (mach == bfd_mach_sh_dsp)
1615 /* SH7410 (orig. sh-sdp):
1616 4KB each for X & Y memory;
1617 On-chip X RAM 0x0800f000-0x0800ffff
1618 On-chip Y RAM 0x0801f000-0x0801ffff */
1619 xram_start = 0x0800f000;
1620 ram_area_size = 0x1000;
1622 if (mach == bfd_mach_sh3_dsp || mach == bfd_mach_sh4al_dsp)
1625 8KB each for X & Y memory;
1626 On-chip X RAM 0x1000e000-0x1000ffff
1627 On-chip Y RAM 0x1001e000-0x1001ffff */
1628 xram_start = 0x1000e000;
1629 ram_area_size = 0x2000;
1631 yram_start = xram_start + 0x10000;
1632 new_select = ~(ram_area_size - 1);
1633 if (saved_state.asregs.xyram_select != new_select)
1635 saved_state.asregs.xyram_select = new_select;
1636 free (saved_state.asregs.xmem);
1637 free (saved_state.asregs.ymem);
1638 saved_state.asregs.xmem =
1639 (unsigned char *) calloc (1, ram_area_size);
1640 saved_state.asregs.ymem =
1641 (unsigned char *) calloc (1, ram_area_size);
1643 /* Disable use of X / Y mmeory if not allocated. */
1644 if (! saved_state.asregs.xmem || ! saved_state.asregs.ymem)
1646 saved_state.asregs.xyram_select = 0;
1647 if (saved_state.asregs.xmem)
1648 free (saved_state.asregs.xmem);
1649 if (saved_state.asregs.ymem)
1650 free (saved_state.asregs.ymem);
1653 saved_state.asregs.xram_start = xram_start;
1654 saved_state.asregs.yram_start = yram_start;
1655 saved_state.asregs.xmem_offset = saved_state.asregs.xmem - xram_start;
1656 saved_state.asregs.ymem_offset = saved_state.asregs.ymem - yram_start;
1661 if (saved_state.asregs.xyram_select)
1663 saved_state.asregs.xyram_select = 0;
1664 free (saved_state.asregs.xmem);
1665 free (saved_state.asregs.ymem);
1669 if (! saved_state.asregs.xyram_select)
1671 saved_state.asregs.xram_start = 1;
1672 saved_state.asregs.yram_start = 1;
1675 if (saved_state.asregs.regstack == NULL)
1676 saved_state.asregs.regstack =
1677 calloc (512, sizeof *saved_state.asregs.regstack);
1679 if (target_dsp != was_dsp)
1683 for (i = (sizeof sh_dsp_table / sizeof sh_dsp_table[0]) - 1; i >= 0; i--)
1685 tmp = sh_jump_table[0xf000 + i];
1686 sh_jump_table[0xf000 + i] = sh_dsp_table[i];
1687 sh_dsp_table[i] = tmp;
1693 init_pointers (void)
1695 if (saved_state.asregs.msize != 1 << sim_memory_size)
1697 sim_size (sim_memory_size);
1700 if (saved_state.asregs.profile && !profile_file)
1702 profile_file = fopen ("gmon.out", "wb");
1703 /* Seek to where to put the call arc data */
1704 nsamples = (1 << sim_profile_size);
1706 fseek (profile_file, nsamples * 2 + 12, 0);
1710 fprintf (stderr, "Can't open gmon.out\n");
1714 saved_state.asregs.profile_hist =
1715 (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64));
1728 p = saved_state.asregs.profile_hist;
1730 maxpc = (1 << sim_profile_size);
1732 fseek (profile_file, 0L, 0);
1733 swapout (minpc << PROFILE_SHIFT);
1734 swapout (maxpc << PROFILE_SHIFT);
1735 swapout (nsamples * 2 + 12);
1736 for (i = 0; i < nsamples; i++)
1737 swapout16 (saved_state.asregs.profile_hist[i]);
1742 gotcall (int from, int to)
1749 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1752 sim_resume (SIM_DESC sd, int step, int siggnal)
1754 register unsigned char *insn_ptr;
1755 unsigned char *mem_end;
1756 struct loop_bounds loop;
1757 register int cycles = 0;
1758 register int stalls = 0;
1759 register int memstalls = 0;
1760 register int insts = 0;
1761 register int prevlock;
1765 register int thislock;
1767 register unsigned int doprofile;
1768 register int pollcount = 0;
1769 /* endianw is used for every insn fetch, hence it makes sense to cache it.
1770 endianb is used less often. */
1771 register int endianw = global_endianw;
1773 int tick_start = get_now ();
1774 void (*prev_fpe) ();
1776 register unsigned short *jump_table = sh_jump_table;
1778 register int *R = &(saved_state.asregs.regs[0]);
1784 register int maskb = ~((saved_state.asregs.msize - 1) & ~0);
1785 register int maskw = ~((saved_state.asregs.msize - 1) & ~1);
1786 register int maskl = ~((saved_state.asregs.msize - 1) & ~3);
1787 register unsigned char *memory;
1788 register unsigned int sbit = ((unsigned int) 1 << 31);
1790 prev_fpe = signal (SIGFPE, SIG_IGN);
1793 saved_state.asregs.exception = 0;
1795 memory = saved_state.asregs.memory;
1796 mem_end = memory + saved_state.asregs.msize;
1799 loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);
1801 loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);
1803 insn_ptr = PT2H (saved_state.asregs.pc);
1804 CHECK_INSN_PTR (insn_ptr);
1807 PR = saved_state.asregs.sregs.named.pr;
1809 /*T = GET_SR () & SR_MASK_T;*/
1810 prevlock = saved_state.asregs.prevlock;
1811 thislock = saved_state.asregs.thislock;
1812 doprofile = saved_state.asregs.profile;
1814 /* If profiling not enabled, disable it by asking for
1815 profiles infrequently. */
1820 if (step && insn_ptr < saved_state.asregs.insn_end)
1822 if (saved_state.asregs.exception)
1823 /* This can happen if we've already been single-stepping and
1824 encountered a loop end. */
1825 saved_state.asregs.insn_end = insn_ptr;
1828 saved_state.asregs.exception = SIGTRAP;
1829 saved_state.asregs.insn_end = insn_ptr + 2;
1833 while (insn_ptr < saved_state.asregs.insn_end)
1835 register unsigned int iword = RIAT (insn_ptr);
1836 register unsigned int ult;
1837 register unsigned char *nip = insn_ptr + 2;
1850 if (--pollcount < 0)
1852 host_callback *callback = STATE_CALLBACK (sd);
1854 pollcount = POLL_QUIT_INTERVAL;
1855 if ((*callback->poll_quit) != NULL
1856 && (*callback->poll_quit) (callback))
1863 prevlock = thislock;
1867 if (cycles >= doprofile)
1870 saved_state.asregs.cycles += doprofile;
1871 cycles -= doprofile;
1872 if (saved_state.asregs.profile_hist)
1874 int n = PH2T (insn_ptr) >> PROFILE_SHIFT;
1877 int i = saved_state.asregs.profile_hist[n];
1879 saved_state.asregs.profile_hist[n] = i + 1;
1886 if (saved_state.asregs.insn_end == loop.end)
1888 saved_state.asregs.cregs.named.sr += SR_RC_INCREMENT;
1890 insn_ptr = loop.start;
1893 saved_state.asregs.insn_end = mem_end;
1894 loop.end = PT2H (0);
1899 if (saved_state.asregs.exception == SIGILL
1900 || saved_state.asregs.exception == SIGBUS)
1904 /* Check for SIGBUS due to insn fetch. */
1905 else if (! saved_state.asregs.exception)
1906 saved_state.asregs.exception = SIGBUS;
1908 saved_state.asregs.ticks += get_now () - tick_start;
1909 saved_state.asregs.cycles += cycles;
1910 saved_state.asregs.stalls += stalls;
1911 saved_state.asregs.memstalls += memstalls;
1912 saved_state.asregs.insts += insts;
1913 saved_state.asregs.pc = PH2T (insn_ptr);
1915 saved_state.asregs.sregs.named.pr = PR;
1918 saved_state.asregs.prevlock = prevlock;
1919 saved_state.asregs.thislock = thislock;
1926 signal (SIGFPE, prev_fpe);
1930 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
1936 for (i = 0; i < size; i++)
1938 saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb] = buffer[i];
1944 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
1950 for (i = 0; i < size; i++)
1952 buffer[i] = saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb];
1957 static int gdb_bank_number;
1967 sh_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
1972 val = swap (* (int *) memory);
1975 case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
1976 case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
1977 case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
1978 case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
1979 case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
1980 case SIM_SH_R15_REGNUM:
1981 saved_state.asregs.regs[rn] = val;
1983 case SIM_SH_PC_REGNUM:
1984 saved_state.asregs.pc = val;
1986 case SIM_SH_PR_REGNUM:
1989 case SIM_SH_GBR_REGNUM:
1992 case SIM_SH_VBR_REGNUM:
1995 case SIM_SH_MACH_REGNUM:
1998 case SIM_SH_MACL_REGNUM:
2001 case SIM_SH_SR_REGNUM:
2004 case SIM_SH_FPUL_REGNUM:
2007 case SIM_SH_FPSCR_REGNUM:
2010 case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM:
2011 case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM:
2012 case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
2013 case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
2014 case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
2015 case SIM_SH_FR15_REGNUM:
2016 SET_FI (rn - SIM_SH_FR0_REGNUM, val);
2018 case SIM_SH_DSR_REGNUM:
2021 case SIM_SH_A0G_REGNUM:
2024 case SIM_SH_A0_REGNUM:
2027 case SIM_SH_A1G_REGNUM:
2030 case SIM_SH_A1_REGNUM:
2033 case SIM_SH_M0_REGNUM:
2036 case SIM_SH_M1_REGNUM:
2039 case SIM_SH_X0_REGNUM:
2042 case SIM_SH_X1_REGNUM:
2045 case SIM_SH_Y0_REGNUM:
2048 case SIM_SH_Y1_REGNUM:
2051 case SIM_SH_MOD_REGNUM:
2054 case SIM_SH_RS_REGNUM:
2057 case SIM_SH_RE_REGNUM:
2060 case SIM_SH_SSR_REGNUM:
2063 case SIM_SH_SPC_REGNUM:
2066 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2067 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2068 case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
2069 case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
2070 case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
2071 case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
2072 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2074 rn -= SIM_SH_R0_BANK0_REGNUM;
2075 saved_state.asregs.regstack[gdb_bank_number].regs[rn] = val;
2079 Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val;
2081 saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val;
2083 case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
2084 case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
2085 case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
2086 case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
2087 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2089 rn -= SIM_SH_R0_BANK1_REGNUM;
2090 saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8] = val;
2094 saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val;
2096 Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) = val;
2098 case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
2099 case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
2100 case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
2101 case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
2102 SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val);
2104 case SIM_SH_TBR_REGNUM:
2107 case SIM_SH_IBNR_REGNUM:
2110 case SIM_SH_IBCR_REGNUM:
2113 case SIM_SH_BANK_REGNUM:
2114 /* This is a pseudo-register maintained just for gdb.
2115 It tells us what register bank gdb would like to read/write. */
2116 gdb_bank_number = val;
2118 case SIM_SH_BANK_MACL_REGNUM:
2119 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL] = val;
2121 case SIM_SH_BANK_GBR_REGNUM:
2122 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR] = val;
2124 case SIM_SH_BANK_PR_REGNUM:
2125 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR] = val;
2127 case SIM_SH_BANK_IVN_REGNUM:
2128 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN] = val;
2130 case SIM_SH_BANK_MACH_REGNUM:
2131 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH] = val;
2140 sh_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
2147 case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
2148 case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
2149 case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
2150 case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
2151 case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
2152 case SIM_SH_R15_REGNUM:
2153 val = saved_state.asregs.regs[rn];
2155 case SIM_SH_PC_REGNUM:
2156 val = saved_state.asregs.pc;
2158 case SIM_SH_PR_REGNUM:
2161 case SIM_SH_GBR_REGNUM:
2164 case SIM_SH_VBR_REGNUM:
2167 case SIM_SH_MACH_REGNUM:
2170 case SIM_SH_MACL_REGNUM:
2173 case SIM_SH_SR_REGNUM:
2176 case SIM_SH_FPUL_REGNUM:
2179 case SIM_SH_FPSCR_REGNUM:
2182 case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM:
2183 case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM:
2184 case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
2185 case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
2186 case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
2187 case SIM_SH_FR15_REGNUM:
2188 val = FI (rn - SIM_SH_FR0_REGNUM);
2190 case SIM_SH_DSR_REGNUM:
2193 case SIM_SH_A0G_REGNUM:
2196 case SIM_SH_A0_REGNUM:
2199 case SIM_SH_A1G_REGNUM:
2202 case SIM_SH_A1_REGNUM:
2205 case SIM_SH_M0_REGNUM:
2208 case SIM_SH_M1_REGNUM:
2211 case SIM_SH_X0_REGNUM:
2214 case SIM_SH_X1_REGNUM:
2217 case SIM_SH_Y0_REGNUM:
2220 case SIM_SH_Y1_REGNUM:
2223 case SIM_SH_MOD_REGNUM:
2226 case SIM_SH_RS_REGNUM:
2229 case SIM_SH_RE_REGNUM:
2232 case SIM_SH_SSR_REGNUM:
2235 case SIM_SH_SPC_REGNUM:
2238 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2239 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2240 case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
2241 case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
2242 case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
2243 case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
2244 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2246 rn -= SIM_SH_R0_BANK0_REGNUM;
2247 val = saved_state.asregs.regstack[gdb_bank_number].regs[rn];
2250 val = (SR_MD && SR_RB
2251 ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM)
2252 : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]);
2254 case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
2255 case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
2256 case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
2257 case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
2258 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2260 rn -= SIM_SH_R0_BANK1_REGNUM;
2261 val = saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8];
2264 val = (! SR_MD || ! SR_RB
2265 ? Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM)
2266 : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]);
2268 case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
2269 case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
2270 case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
2271 case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
2272 val = Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM);
2274 case SIM_SH_TBR_REGNUM:
2277 case SIM_SH_IBNR_REGNUM:
2280 case SIM_SH_IBCR_REGNUM:
2283 case SIM_SH_BANK_REGNUM:
2284 /* This is a pseudo-register maintained just for gdb.
2285 It tells us what register bank gdb would like to read/write. */
2286 val = gdb_bank_number;
2288 case SIM_SH_BANK_MACL_REGNUM:
2289 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL];
2291 case SIM_SH_BANK_GBR_REGNUM:
2292 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR];
2294 case SIM_SH_BANK_PR_REGNUM:
2295 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR];
2297 case SIM_SH_BANK_IVN_REGNUM:
2298 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN];
2300 case SIM_SH_BANK_MACH_REGNUM:
2301 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH];
2306 * (int *) memory = swap (val);
2311 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
2313 /* The SH simulator uses SIGQUIT to indicate that the program has
2314 exited, so we must check for it here and translate it to exit. */
2315 if (saved_state.asregs.exception == SIGQUIT)
2317 *reason = sim_exited;
2318 *sigrc = saved_state.asregs.regs[5];
2322 *reason = sim_stopped;
2323 *sigrc = saved_state.asregs.exception;
2328 sim_info (SIM_DESC sd, int verbose)
2331 (double) saved_state.asregs.ticks / (double) now_persec ();
2332 double virttime = saved_state.asregs.cycles / 36.0e6;
2334 sim_io_printf (sd, "\n\n# instructions executed %10d\n",
2335 saved_state.asregs.insts);
2336 sim_io_printf (sd, "# cycles %10d\n",
2337 saved_state.asregs.cycles);
2338 sim_io_printf (sd, "# pipeline stalls %10d\n",
2339 saved_state.asregs.stalls);
2340 sim_io_printf (sd, "# misaligned load/store %10d\n",
2341 saved_state.asregs.memstalls);
2342 sim_io_printf (sd, "# real time taken %10.4f\n", timetaken);
2343 sim_io_printf (sd, "# virtual time taken %10.4f\n", virttime);
2344 sim_io_printf (sd, "# profiling size %10d\n", sim_profile_size);
2345 sim_io_printf (sd, "# profiling frequency %10d\n",
2346 saved_state.asregs.profile);
2347 sim_io_printf (sd, "# profile maxpc %10x\n",
2348 (1 << sim_profile_size) << PROFILE_SHIFT);
2352 sim_io_printf (sd, "# cycles/second %10d\n",
2353 (int) (saved_state.asregs.cycles / timetaken));
2354 sim_io_printf (sd, "# simulation ratio %10.4f\n",
2355 virttime / timetaken);
2360 sh_pc_get (sim_cpu *cpu)
2362 return saved_state.asregs.pc;
2366 sh_pc_set (sim_cpu *cpu, sim_cia pc)
2368 saved_state.asregs.pc = pc;
2372 free_state (SIM_DESC sd)
2374 if (STATE_MODULES (sd) != NULL)
2375 sim_module_uninstall (sd);
2376 sim_cpu_free_all (sd);
2377 sim_state_free (sd);
2381 sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
2393 SIM_DESC sd = sim_state_alloc (kind, cb);
2394 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
2396 /* The cpu data is kept in a separately allocated chunk of memory. */
2397 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
2403 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
2409 /* getopt will print the error message so we just have to exit if this fails.
2410 FIXME: Hmmm... in the case of gdb we need getopt to call
2412 if (sim_parse_args (sd, argv) != SIM_RC_OK)
2418 /* Check for/establish the a reference program image. */
2419 if (sim_analyze_program (sd,
2420 (STATE_PROG_ARGV (sd) != NULL
2421 ? *STATE_PROG_ARGV (sd)
2422 : NULL), abfd) != SIM_RC_OK)
2428 /* Configure/verify the target byte order and other runtime
2429 configuration options. */
2430 if (sim_config (sd) != SIM_RC_OK)
2432 sim_module_uninstall (sd);
2436 if (sim_post_argv_init (sd) != SIM_RC_OK)
2438 /* Uninstall the modules to avoid memory leaks,
2439 file descriptor leaks, etc. */
2440 sim_module_uninstall (sd);
2444 /* CPU specific initialization. */
2445 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
2447 SIM_CPU *cpu = STATE_CPU (sd, i);
2449 CPU_REG_FETCH (cpu) = sh_reg_fetch;
2450 CPU_REG_STORE (cpu) = sh_reg_store;
2451 CPU_PC_FETCH (cpu) = sh_pc_get;
2452 CPU_PC_STORE (cpu) = sh_pc_set;
2455 for (p = argv + 1; *p != NULL; ++p)
2458 parse_and_set_memory_size (sd, *p);
2464 for (i = 4; (i -= 2) >= 0; )
2465 mem_word.s[i >> 1] = i;
2466 global_endianw = mem_word.i >> (target_little_endian ? 0 : 16) & 0xffff;
2468 for (i = 4; --i >= 0; )
2470 endianb = mem_word.i >> (target_little_endian ? 0 : 24) & 0xff;
2476 parse_and_set_memory_size (SIM_DESC sd, const char *str)
2480 n = strtol (str, NULL, 10);
2481 if (n > 0 && n <= 24)
2482 sim_memory_size = n;
2484 sim_io_printf (sd, "Bad memory size %d; must be 1 to 24, inclusive\n", n);
2488 sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
2490 /* Clear the registers. */
2491 memset (&saved_state, 0,
2492 (char*) &saved_state.asregs.end_of_registers - (char*) &saved_state);
2495 if (prog_bfd != NULL)
2496 saved_state.asregs.pc = bfd_get_start_address (prog_bfd);
2498 /* Set the bfd machine type. */
2499 if (prog_bfd != NULL)
2500 saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd);
2502 if (prog_bfd != NULL)
2503 init_dsp (prog_bfd);
2509 sim_do_command (SIM_DESC sd, const char *cmd)
2511 const char *sms_cmd = "set-memory-size";
2514 if (cmd == NULL || *cmd == '\0')
2519 cmdsize = strlen (sms_cmd);
2520 if (strncmp (cmd, sms_cmd, cmdsize) == 0
2521 && strchr (" \t", cmd[cmdsize]) != NULL)
2523 parse_and_set_memory_size (sd, cmd + cmdsize + 1);
2525 else if (strcmp (cmd, "help") == 0)
2527 sim_io_printf (sd, "List of SH simulator commands:\n\n");
2528 sim_io_printf (sd, "set-memory-size <n> -- Set the number of address bits to use\n");
2529 sim_io_printf (sd, "\n");
2533 sim_io_printf (sd, "Error: \"%s\" is not a valid SH simulator command.\n", cmd);