1 /* OpenRISC simulator support code header
2 Copyright (C) 2017-2018 Free Software Foundation, Inc.
4 This file is part of GDB, the GNU debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 /* GDB register numbers. */
29 /* Misc. profile data. */
34 /* Nop codes used in nop simulation. */
37 #define NOP_REPORT 0x2
39 #define NOP_CNT_RESET 0x5
40 #define NOP_GET_TICKS 0x6
41 #define NOP_GET_PS 0x7
42 #define NOP_TRACE_ON 0x8
43 #define NOP_TRACE_OFF 0x9
44 #define NOP_RANDOM 0xa
45 #define NOP_OR1KSIM 0xb
46 #define NOP_EXIT_SILENT 0xc
48 #define NUM_SPR 0x20000
49 #define SPR_GROUP_SHIFT 11
50 #define SPR_GROUP_FIRST(group) (((UWI) SPR_GROUP_##group) << SPR_GROUP_SHIFT)
51 #define SPR_ADDR(group,index) \
52 (SPR_GROUP_FIRST(group) | ((UWI) SPR_INDEX_##group##_##index))
54 /* Define word getters and setter helpers based on those from
55 sim/common/cgen-mem.h. */
59 void or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
60 const USI or1k_upr, const USI or1k_cpucfgr);
62 void or1k32bf_insn_before (sim_cpu* current_cpu, SEM_PC vpc, const IDESC *idesc);
63 void or1k32bf_insn_after (sim_cpu* current_cpu, SEM_PC vpc, const IDESC *idesc);
64 void or1k32bf_fpu_error (CGEN_FPU* fpu, int status);
65 void or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum);
66 void or1k32bf_rfe (sim_cpu *current_cpu);
67 void or1k32bf_nop (sim_cpu *current_cpu, USI uimm16);
68 USI or1k32bf_mfspr (sim_cpu *current_cpu, USI addr);
69 void or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val);
71 int or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, unsigned char *buf,
73 int or1k32bf_store_register (sim_cpu *current_cpu, int rn, unsigned char *buf,
75 int or1k32bf_model_or1200_u_exec (sim_cpu *current_cpu, const IDESC *idesc,
76 int unit_num, int referenced);
77 int or1k32bf_model_or1200nd_u_exec (sim_cpu *current_cpu, const IDESC *idesc,
78 int unit_num, int referenced);
79 void or1k32bf_model_insn_before (sim_cpu *current_cpu, int first_p);
80 void or1k32bf_model_insn_after (sim_cpu *current_cpu, int last_p, int cycles);
81 USI or1k32bf_h_spr_get_raw (sim_cpu *current_cpu, USI addr);
82 void or1k32bf_h_spr_set_raw (sim_cpu *current_cpu, USI addr, USI val);
83 USI or1k32bf_h_spr_field_get_raw (sim_cpu *current_cpu, USI addr, int msb,
85 void or1k32bf_h_spr_field_set_raw (sim_cpu *current_cpu, USI addr, int msb,
87 USI or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset,
90 USI or1k32bf_ff1 (sim_cpu *current_cpu, USI val);
91 USI or1k32bf_fl1 (sim_cpu *current_cpu, USI val);
93 #endif /* OR1K_SIM_H */