1 /* Simulator for the moxie processor
2 Copyright (C) 2008-2014 Free Software Foundation, Inc.
3 Contributed by Anthony Green
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include <sys/times.h>
26 #include <sys/param.h>
27 #include <netinet/in.h> /* for byte ordering macros */
29 #include "gdb/callback.h"
30 #include "libiberty.h"
31 #include "gdb/remote-sim.h"
37 typedef unsigned int uword;
39 host_callback * callback;
43 /* Extract the signed 10-bit offset from a 16-bit branch
45 #define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1)
47 #define EXTRACT_WORD(addr) \
48 ((sim_core_read_aligned_1 (scpu, cia, read_map, addr) << 24) \
49 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+1) << 16) \
50 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+2) << 8) \
51 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+3)))
54 moxie_extract_unsigned_integer (addr, len)
60 unsigned char * startaddr = (unsigned char *)addr;
61 unsigned char * endaddr = startaddr + len;
63 if (len > (int) sizeof (unsigned long))
64 printf ("That operation is not available on integers of more than %d bytes.",
65 sizeof (unsigned long));
67 /* Start at the most significant end of the integer, and work towards
68 the least significant. */
71 for (p = endaddr; p > startaddr;)
72 retval = (retval << 8) | * -- p;
78 moxie_store_unsigned_integer (addr, len, val)
84 unsigned char * startaddr = (unsigned char *)addr;
85 unsigned char * endaddr = startaddr + len;
87 for (p = endaddr; p > startaddr;)
94 /* moxie register names. */
95 static const char *reg_names[16] =
96 { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5",
97 "$r6", "$r7", "$r8", "$r9", "$r10", "$r11", "$r12", "$r13" };
101 This state is maintained in host byte order. The fetch/store
102 register functions must translate between host byte order and the
103 target processor byte order. Keeping this data in target byte
104 order simplifies the register read/write functions. Keeping this
105 data in native order improves the performance of the simulator.
106 Simulation speed is deemed more important. */
108 #define NUM_MOXIE_REGS 17 /* Including PC */
109 #define NUM_MOXIE_SREGS 256 /* The special registers */
112 /* The ordering of the moxie_regset structure is matched in the
113 gdb/config/moxie/tm-moxie.h file in the REGISTER_NAMES macro. */
116 word regs[NUM_MOXIE_REGS + 1]; /* primary registers */
117 word sregs[256]; /* special registers */
118 word cc; /* the condition code reg */
120 unsigned long long insts; /* instruction counter */
131 struct moxie_regset asregs;
132 word asints [1]; /* but accessed larger... */
136 static SIM_OPEN_KIND sim_kind;
137 static int issue_messages = 0;
150 /* Set up machine just out of reset. */
151 cpu.asregs.regs[PC_REGNO] = 0;
153 /* Clean out the register contents. */
154 for (i = 0; i < NUM_MOXIE_REGS; i++)
155 cpu.asregs.regs[i] = 0;
156 for (i = 0; i < NUM_MOXIE_SREGS; i++)
157 cpu.asregs.sregs[i] = 0;
160 /* Write a 1 byte value to memory. */
163 wbat (sim_cpu *scpu, word pc, word x, word v)
165 address_word cia = CIA_GET (scpu);
167 sim_core_write_aligned_1 (scpu, cia, write_map, x, v);
170 /* Write a 2 byte value to memory. */
173 wsat (sim_cpu *scpu, word pc, word x, word v)
175 address_word cia = CIA_GET (scpu);
177 sim_core_write_aligned_2 (scpu, cia, write_map, x, v);
180 /* Write a 4 byte value to memory. */
183 wlat (sim_cpu *scpu, word pc, word x, word v)
185 address_word cia = CIA_GET (scpu);
187 sim_core_write_aligned_4 (scpu, cia, write_map, x, v);
190 /* Read 2 bytes from memory. */
193 rsat (sim_cpu *scpu, word pc, word x)
195 address_word cia = CIA_GET (scpu);
197 return (sim_core_read_aligned_2 (scpu, cia, read_map, x));
200 /* Read 1 byte from memory. */
203 rbat (sim_cpu *scpu, word pc, word x)
205 address_word cia = CIA_GET (scpu);
207 return (sim_core_read_aligned_1 (scpu, cia, read_map, x));
210 /* Read 4 bytes from memory. */
213 rlat (sim_cpu *scpu, word pc, word x)
215 address_word cia = CIA_GET (scpu);
217 return (sim_core_read_aligned_4 (scpu, cia, read_map, x));
220 #define CHECK_FLAG(T,H) if (tflags & T) { hflags |= H; tflags ^= T; }
223 convert_target_flags (unsigned int tflags)
225 unsigned int hflags = 0x0;
227 CHECK_FLAG(0x0001, O_WRONLY);
228 CHECK_FLAG(0x0002, O_RDWR);
229 CHECK_FLAG(0x0008, O_APPEND);
230 CHECK_FLAG(0x0200, O_CREAT);
231 CHECK_FLAG(0x0400, O_TRUNC);
232 CHECK_FLAG(0x0800, O_EXCL);
233 CHECK_FLAG(0x2000, O_SYNC);
237 "Simulator Error: problem converting target open flags for host. 0x%x\n",
243 #define TRACE(str) if (tracing) fprintf(tracefile,"0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", opc, str, cpu.asregs.regs[0], cpu.asregs.regs[1], cpu.asregs.regs[2], cpu.asregs.regs[3], cpu.asregs.regs[4], cpu.asregs.regs[5], cpu.asregs.regs[6], cpu.asregs.regs[7], cpu.asregs.regs[8], cpu.asregs.regs[9], cpu.asregs.regs[10], cpu.asregs.regs[11], cpu.asregs.regs[12], cpu.asregs.regs[13], cpu.asregs.regs[14], cpu.asregs.regs[15]);
245 static int tracing = 0;
248 sim_resume (sd, step, siggnal)
253 unsigned long long insts;
255 sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
256 address_word cia = CIA_GET (scpu);
258 cpu.asregs.exception = step ? SIGTRAP: 0;
259 pc = cpu.asregs.regs[PC_REGNO];
260 insts = cpu.asregs.insts;
262 /* Run instructions here. */
267 /* Fetch the instruction at pc. */
268 inst = (sim_core_read_aligned_1 (scpu, cia, read_map, pc) << 8)
269 + sim_core_read_aligned_1 (scpu, cia, read_map, pc+1);
271 /* Decode instruction. */
272 if (inst & (1 << 15))
274 if (inst & (1 << 14))
276 /* This is a Form 3 instruction. */
277 int opcode = (inst >> 10 & 0xf);
284 if (cpu.asregs.cc & CC_EQ)
285 pc += INST2OFFSET(inst);
291 if (! (cpu.asregs.cc & CC_EQ))
292 pc += INST2OFFSET(inst);
298 if (cpu.asregs.cc & CC_LT)
299 pc += INST2OFFSET(inst);
304 if (cpu.asregs.cc & CC_GT)
305 pc += INST2OFFSET(inst);
308 case 0x04: /* bltu */
311 if (cpu.asregs.cc & CC_LTU)
312 pc += INST2OFFSET(inst);
315 case 0x05: /* bgtu */
318 if (cpu.asregs.cc & CC_GTU)
319 pc += INST2OFFSET(inst);
325 if (cpu.asregs.cc & (CC_GT | CC_EQ))
326 pc += INST2OFFSET(inst);
332 if (cpu.asregs.cc & (CC_LT | CC_EQ))
333 pc += INST2OFFSET(inst);
336 case 0x08: /* bgeu */
339 if (cpu.asregs.cc & (CC_GTU | CC_EQ))
340 pc += INST2OFFSET(inst);
343 case 0x09: /* bleu */
346 if (cpu.asregs.cc & (CC_LTU | CC_EQ))
347 pc += INST2OFFSET(inst);
353 cpu.asregs.exception = SIGILL;
360 /* This is a Form 2 instruction. */
361 int opcode = (inst >> 12 & 0x3);
366 int a = (inst >> 8) & 0xf;
367 unsigned av = cpu.asregs.regs[a];
368 unsigned v = (inst & 0xff);
370 cpu.asregs.regs[a] = av + v;
375 int a = (inst >> 8) & 0xf;
376 unsigned av = cpu.asregs.regs[a];
377 unsigned v = (inst & 0xff);
379 cpu.asregs.regs[a] = av - v;
384 int a = (inst >> 8) & 0xf;
385 unsigned v = (inst & 0xff);
387 cpu.asregs.regs[a] = cpu.asregs.sregs[v];
392 int a = (inst >> 8) & 0xf;
393 unsigned v = (inst & 0xff);
395 cpu.asregs.sregs[v] = cpu.asregs.regs[a];
400 cpu.asregs.exception = SIGILL;
407 /* This is a Form 1 instruction. */
408 int opcode = inst >> 8;
414 cpu.asregs.exception = SIGILL;
416 case 0x01: /* ldi.l (immediate) */
418 int reg = (inst >> 4) & 0xf;
420 unsigned int val = EXTRACT_WORD(pc+2);
421 cpu.asregs.regs[reg] = val;
425 case 0x02: /* mov (register-to-register) */
427 int dest = (inst >> 4) & 0xf;
428 int src = (inst ) & 0xf;
430 cpu.asregs.regs[dest] = cpu.asregs.regs[src];
433 case 0x03: /* jsra */
435 unsigned int fn = EXTRACT_WORD(pc+2);
436 unsigned int sp = cpu.asregs.regs[1];
438 /* Save a slot for the static chain. */
441 /* Push the return address. */
443 wlat (scpu, opc, sp, pc + 6);
445 /* Push the current frame pointer. */
447 wlat (scpu, opc, sp, cpu.asregs.regs[0]);
449 /* Uncache the stack pointer and set the pc and $fp. */
450 cpu.asregs.regs[1] = sp;
451 cpu.asregs.regs[0] = sp;
457 unsigned int sp = cpu.asregs.regs[0];
461 /* Pop the frame pointer. */
462 cpu.asregs.regs[0] = rlat (scpu, opc, sp);
465 /* Pop the return address. */
466 pc = rlat (scpu, opc, sp) - 2;
469 /* Skip over the static chain slot. */
472 /* Uncache the stack pointer. */
473 cpu.asregs.regs[1] = sp;
476 case 0x05: /* add.l */
478 int a = (inst >> 4) & 0xf;
480 unsigned av = cpu.asregs.regs[a];
481 unsigned bv = cpu.asregs.regs[b];
483 cpu.asregs.regs[a] = av + bv;
486 case 0x06: /* push */
488 int a = (inst >> 4) & 0xf;
490 int sp = cpu.asregs.regs[a] - 4;
492 wlat (scpu, opc, sp, cpu.asregs.regs[b]);
493 cpu.asregs.regs[a] = sp;
498 int a = (inst >> 4) & 0xf;
500 int sp = cpu.asregs.regs[a];
502 cpu.asregs.regs[b] = rlat (scpu, opc, sp);
503 cpu.asregs.regs[a] = sp + 4;
506 case 0x08: /* lda.l */
508 int reg = (inst >> 4) & 0xf;
509 unsigned int addr = EXTRACT_WORD(pc+2);
511 cpu.asregs.regs[reg] = rlat (scpu, opc, addr);
515 case 0x09: /* sta.l */
517 int reg = (inst >> 4) & 0xf;
518 unsigned int addr = EXTRACT_WORD(pc+2);
520 wlat (scpu, opc, addr, cpu.asregs.regs[reg]);
524 case 0x0a: /* ld.l (register indirect) */
526 int src = inst & 0xf;
527 int dest = (inst >> 4) & 0xf;
530 xv = cpu.asregs.regs[src];
531 cpu.asregs.regs[dest] = rlat (scpu, opc, xv);
534 case 0x0b: /* st.l */
536 int dest = (inst >> 4) & 0xf;
537 int val = inst & 0xf;
539 wlat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
542 case 0x0c: /* ldo.l */
544 unsigned int addr = EXTRACT_WORD(pc+2);
545 int a = (inst >> 4) & 0xf;
548 addr += cpu.asregs.regs[b];
549 cpu.asregs.regs[a] = rlat (scpu, opc, addr);
553 case 0x0d: /* sto.l */
555 unsigned int addr = EXTRACT_WORD(pc+2);
556 int a = (inst >> 4) & 0xf;
559 addr += cpu.asregs.regs[a];
560 wlat (scpu, opc, addr, cpu.asregs.regs[b]);
566 int a = (inst >> 4) & 0xf;
569 int va = cpu.asregs.regs[a];
570 int vb = cpu.asregs.regs[b];
578 cc |= (va < vb ? CC_LT : 0);
579 cc |= (va > vb ? CC_GT : 0);
580 cc |= ((unsigned int) va < (unsigned int) vb ? CC_LTU : 0);
581 cc |= ((unsigned int) va > (unsigned int) vb ? CC_GTU : 0);
589 case 0x10: /* sex.b */
591 int a = (inst >> 4) & 0xf;
593 signed char bv = cpu.asregs.regs[b];
595 cpu.asregs.regs[a] = (int) bv;
598 case 0x11: /* sex.s */
600 int a = (inst >> 4) & 0xf;
602 signed short bv = cpu.asregs.regs[b];
604 cpu.asregs.regs[a] = (int) bv;
607 case 0x12: /* zex.b */
609 int a = (inst >> 4) & 0xf;
611 signed char bv = cpu.asregs.regs[b];
613 cpu.asregs.regs[a] = (int) bv & 0xff;
616 case 0x13: /* zex.s */
618 int a = (inst >> 4) & 0xf;
620 signed short bv = cpu.asregs.regs[b];
622 cpu.asregs.regs[a] = (int) bv & 0xffff;
625 case 0x14: /* mul.x */
627 int a = (inst >> 4) & 0xf;
629 unsigned av = cpu.asregs.regs[a];
630 unsigned bv = cpu.asregs.regs[b];
633 (signed long long) av * (signed long long) bv;
634 cpu.asregs.regs[a] = r >> 32;
637 case 0x15: /* umul.x */
639 int a = (inst >> 4) & 0xf;
641 unsigned av = cpu.asregs.regs[a];
642 unsigned bv = cpu.asregs.regs[b];
644 unsigned long long r =
645 (unsigned long long) av * (unsigned long long) bv;
646 cpu.asregs.regs[a] = r >> 32;
655 cpu.asregs.exception = SIGILL;
660 unsigned int fn = cpu.asregs.regs[(inst >> 4) & 0xf];
661 unsigned int sp = cpu.asregs.regs[1];
665 /* Save a slot for the static chain. */
668 /* Push the return address. */
670 wlat (scpu, opc, sp, pc + 2);
672 /* Push the current frame pointer. */
674 wlat (scpu, opc, sp, cpu.asregs.regs[0]);
676 /* Uncache the stack pointer and set the fp & pc. */
677 cpu.asregs.regs[1] = sp;
678 cpu.asregs.regs[0] = sp;
682 case 0x1a: /* jmpa */
684 unsigned int tgt = EXTRACT_WORD(pc+2);
689 case 0x1b: /* ldi.b (immediate) */
691 int reg = (inst >> 4) & 0xf;
693 unsigned int val = EXTRACT_WORD(pc+2);
695 cpu.asregs.regs[reg] = val;
699 case 0x1c: /* ld.b (register indirect) */
701 int src = inst & 0xf;
702 int dest = (inst >> 4) & 0xf;
705 xv = cpu.asregs.regs[src];
706 cpu.asregs.regs[dest] = rbat (scpu, opc, xv);
709 case 0x1d: /* lda.b */
711 int reg = (inst >> 4) & 0xf;
712 unsigned int addr = EXTRACT_WORD(pc+2);
714 cpu.asregs.regs[reg] = rbat (scpu, opc, addr);
718 case 0x1e: /* st.b */
720 int dest = (inst >> 4) & 0xf;
721 int val = inst & 0xf;
723 wbat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
726 case 0x1f: /* sta.b */
728 int reg = (inst >> 4) & 0xf;
729 unsigned int addr = EXTRACT_WORD(pc+2);
731 wbat (scpu, opc, addr, cpu.asregs.regs[reg]);
735 case 0x20: /* ldi.s (immediate) */
737 int reg = (inst >> 4) & 0xf;
739 unsigned int val = EXTRACT_WORD(pc+2);
741 cpu.asregs.regs[reg] = val;
745 case 0x21: /* ld.s (register indirect) */
747 int src = inst & 0xf;
748 int dest = (inst >> 4) & 0xf;
751 xv = cpu.asregs.regs[src];
752 cpu.asregs.regs[dest] = rsat (scpu, opc, xv);
755 case 0x22: /* lda.s */
757 int reg = (inst >> 4) & 0xf;
758 unsigned int addr = EXTRACT_WORD(pc+2);
760 cpu.asregs.regs[reg] = rsat (scpu, opc, addr);
764 case 0x23: /* st.s */
766 int dest = (inst >> 4) & 0xf;
767 int val = inst & 0xf;
769 wsat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
772 case 0x24: /* sta.s */
774 int reg = (inst >> 4) & 0xf;
775 unsigned int addr = EXTRACT_WORD(pc+2);
777 wsat (scpu, opc, addr, cpu.asregs.regs[reg]);
783 int reg = (inst >> 4) & 0xf;
785 pc = cpu.asregs.regs[reg] - 2;
790 int a = (inst >> 4) & 0xf;
794 av = cpu.asregs.regs[a];
795 bv = cpu.asregs.regs[b];
796 cpu.asregs.regs[a] = av & bv;
799 case 0x27: /* lshr */
801 int a = (inst >> 4) & 0xf;
803 int av = cpu.asregs.regs[a];
804 int bv = cpu.asregs.regs[b];
806 cpu.asregs.regs[a] = (unsigned) ((unsigned) av >> bv);
809 case 0x28: /* ashl */
811 int a = (inst >> 4) & 0xf;
813 int av = cpu.asregs.regs[a];
814 int bv = cpu.asregs.regs[b];
816 cpu.asregs.regs[a] = av << bv;
819 case 0x29: /* sub.l */
821 int a = (inst >> 4) & 0xf;
823 unsigned av = cpu.asregs.regs[a];
824 unsigned bv = cpu.asregs.regs[b];
826 cpu.asregs.regs[a] = av - bv;
831 int a = (inst >> 4) & 0xf;
833 int bv = cpu.asregs.regs[b];
835 cpu.asregs.regs[a] = - bv;
840 int a = (inst >> 4) & 0xf;
844 av = cpu.asregs.regs[a];
845 bv = cpu.asregs.regs[b];
846 cpu.asregs.regs[a] = av | bv;
851 int a = (inst >> 4) & 0xf;
853 int bv = cpu.asregs.regs[b];
855 cpu.asregs.regs[a] = 0xffffffff ^ bv;
858 case 0x2d: /* ashr */
860 int a = (inst >> 4) & 0xf;
862 int av = cpu.asregs.regs[a];
863 int bv = cpu.asregs.regs[b];
865 cpu.asregs.regs[a] = av >> bv;
870 int a = (inst >> 4) & 0xf;
874 av = cpu.asregs.regs[a];
875 bv = cpu.asregs.regs[b];
876 cpu.asregs.regs[a] = av ^ bv;
879 case 0x2f: /* mul.l */
881 int a = (inst >> 4) & 0xf;
883 unsigned av = cpu.asregs.regs[a];
884 unsigned bv = cpu.asregs.regs[b];
886 cpu.asregs.regs[a] = av * bv;
891 unsigned int inum = EXTRACT_WORD(pc+2);
893 /* Set the special registers appropriately. */
894 cpu.asregs.sregs[2] = 3; /* MOXIE_EX_SWI */
895 cpu.asregs.sregs[3] = inum;
898 case 0x1: /* SYS_exit */
900 cpu.asregs.exception = SIGQUIT;
903 case 0x2: /* SYS_open */
906 int mode = (int) convert_target_flags ((unsigned) cpu.asregs.regs[3]);
907 int perm = (int) cpu.asregs.regs[4];
908 int fd = open (fname, mode, perm);
909 sim_core_read_buffer (sd, scpu, read_map, fname,
910 cpu.asregs.regs[2], 1024);
911 /* FIXME - set errno */
912 cpu.asregs.regs[2] = fd;
915 case 0x4: /* SYS_read */
917 int fd = cpu.asregs.regs[2];
918 unsigned len = (unsigned) cpu.asregs.regs[4];
919 char *buf = malloc (len);
920 cpu.asregs.regs[2] = read (fd, buf, len);
921 sim_core_write_buffer (sd, scpu, write_map, buf,
922 cpu.asregs.regs[3], len);
926 case 0x5: /* SYS_write */
929 /* String length is at 0x12($fp) */
930 unsigned count, len = (unsigned) cpu.asregs.regs[4];
932 sim_core_read_buffer (sd, scpu, read_map, str,
933 cpu.asregs.regs[3], len);
934 count = write (cpu.asregs.regs[2], str, len);
936 cpu.asregs.regs[2] = count;
939 case 0xffffffff: /* Linux System Call */
941 unsigned int handler = cpu.asregs.sregs[1];
942 unsigned int sp = cpu.asregs.regs[1];
944 /* Save a slot for the static chain. */
947 /* Push the return address. */
949 wlat (scpu, opc, sp, pc + 6);
951 /* Push the current frame pointer. */
953 wlat (scpu, opc, sp, cpu.asregs.regs[0]);
955 /* Uncache the stack pointer and set the fp & pc. */
956 cpu.asregs.regs[1] = sp;
957 cpu.asregs.regs[0] = sp;
966 case 0x31: /* div.l */
968 int a = (inst >> 4) & 0xf;
970 int av = cpu.asregs.regs[a];
971 int bv = cpu.asregs.regs[b];
973 cpu.asregs.regs[a] = av / bv;
976 case 0x32: /* udiv.l */
978 int a = (inst >> 4) & 0xf;
980 unsigned int av = cpu.asregs.regs[a];
981 unsigned int bv = cpu.asregs.regs[b];
983 cpu.asregs.regs[a] = (av / bv);
986 case 0x33: /* mod.l */
988 int a = (inst >> 4) & 0xf;
990 int av = cpu.asregs.regs[a];
991 int bv = cpu.asregs.regs[b];
993 cpu.asregs.regs[a] = av % bv;
996 case 0x34: /* umod.l */
998 int a = (inst >> 4) & 0xf;
1000 unsigned int av = cpu.asregs.regs[a];
1001 unsigned int bv = cpu.asregs.regs[b];
1003 cpu.asregs.regs[a] = (av % bv);
1006 case 0x35: /* brk */
1008 cpu.asregs.exception = SIGTRAP;
1009 pc -= 2; /* Adjust pc */
1011 case 0x36: /* ldo.b */
1013 unsigned int addr = EXTRACT_WORD(pc+2);
1014 int a = (inst >> 4) & 0xf;
1017 addr += cpu.asregs.regs[b];
1018 cpu.asregs.regs[a] = rbat (scpu, opc, addr);
1022 case 0x37: /* sto.b */
1024 unsigned int addr = EXTRACT_WORD(pc+2);
1025 int a = (inst >> 4) & 0xf;
1028 addr += cpu.asregs.regs[a];
1029 wbat (scpu, opc, addr, cpu.asregs.regs[b]);
1033 case 0x38: /* ldo.s */
1035 unsigned int addr = EXTRACT_WORD(pc+2);
1036 int a = (inst >> 4) & 0xf;
1039 addr += cpu.asregs.regs[b];
1040 cpu.asregs.regs[a] = rsat (scpu, opc, addr);
1044 case 0x39: /* sto.s */
1046 unsigned int addr = EXTRACT_WORD(pc+2);
1047 int a = (inst >> 4) & 0xf;
1050 addr += cpu.asregs.regs[a];
1051 wsat (scpu, opc, addr, cpu.asregs.regs[b]);
1058 cpu.asregs.exception = SIGILL;
1066 } while (!cpu.asregs.exception);
1068 /* Hide away the things we've cached while executing. */
1069 cpu.asregs.regs[PC_REGNO] = pc;
1070 cpu.asregs.insts += insts; /* instructions done ... */
1074 sim_write (sd, addr, buffer, size)
1077 const unsigned char * buffer;
1080 sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
1082 sim_core_write_buffer (sd, scpu, write_map, buffer, addr, size);
1088 sim_read (sd, addr, buffer, size)
1091 unsigned char * buffer;
1094 sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
1096 sim_core_read_buffer (sd, scpu, read_map, buffer, addr, size);
1103 sim_store_register (sd, rn, memory, length)
1106 unsigned char * memory;
1109 if (rn < NUM_MOXIE_REGS && rn >= 0)
1115 /* misalignment safe */
1116 ival = moxie_extract_unsigned_integer (memory, 4);
1117 cpu.asints[rn] = ival;
1127 sim_fetch_register (sd, rn, memory, length)
1130 unsigned char * memory;
1133 if (rn < NUM_MOXIE_REGS && rn >= 0)
1137 long ival = cpu.asints[rn];
1139 /* misalignment-safe */
1140 moxie_store_unsigned_integer (memory, 4, ival);
1155 tracefile = fopen("trace.csv", "wb");
1159 sim_resume (sd, 0, 0);
1167 sim_stop_reason (sd, reason, sigrc)
1169 enum sim_stop * reason;
1172 if (cpu.asregs.exception == SIGQUIT)
1174 * reason = sim_exited;
1175 * sigrc = cpu.asregs.regs[2];
1179 * reason = sim_stopped;
1180 * sigrc = cpu.asregs.exception;
1189 cpu.asregs.exception = SIGINT;
1195 sim_info (sd, verbose)
1199 callback->printf_filtered (callback, "\n\n# instructions executed %llu\n",
1205 sim_open (kind, cb, abfd, argv)
1211 SIM_DESC sd = sim_state_alloc (kind, cb);
1212 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1214 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
1217 sim_do_command(sd," memory region 0x00000000,0x4000000") ;
1218 sim_do_command(sd," memory region 0xE0000000,0x10000") ;
1223 if (kind == SIM_OPEN_STANDALONE)
1226 set_initial_gprs (); /* Reset the GPR registers. */
1228 /* Configure/verify the target byte order and other runtime
1229 configuration options. */
1230 if (sim_config (sd) != SIM_RC_OK)
1232 sim_module_uninstall (sd);
1236 if (sim_post_argv_init (sd) != SIM_RC_OK)
1238 /* Uninstall the modules to avoid memory leaks,
1239 file descriptor leaks, etc. */
1240 sim_module_uninstall (sd);
1248 sim_close (sd, quitting)
1256 /* Load the device tree blob. */
1259 load_dtb (SIM_DESC sd, const char *filename)
1262 FILE *f = fopen (filename, "rb");
1264 sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
1267 printf ("WARNING: ``%s'' could not be opened.\n", filename);
1270 fseek (f, 0, SEEK_END);
1272 fseek (f, 0, SEEK_SET);
1273 buf = alloca (size);
1274 if (size != fread (buf, 1, size, f))
1276 printf ("ERROR: error reading ``%s''.\n", filename);
1279 sim_core_write_buffer (sd, scpu, write_map, buf, 0xE0000000, size);
1280 cpu.asregs.sregs[9] = 0xE0000000;
1285 sim_load (sd, prog, abfd, from_tty)
1292 /* Do the right thing for ELF executables; this turns out to be
1293 just about the right thing for any object format that:
1294 - we crack using BFD routines
1295 - follows the traditional UNIX text/data/bss layout
1296 - calls the bss section ".bss". */
1298 extern bfd * sim_load_file (); /* ??? Don't know where this should live. */
1303 handle = bfd_openr (prog, 0); /* could be "moxie" */
1307 printf("``%s'' could not be opened.\n", prog);
1311 /* Makes sure that we have an object file, also cleans gets the
1312 section headers in place. */
1313 if (!bfd_check_format (handle, bfd_object))
1315 /* wasn't an object file */
1317 printf ("``%s'' is not appropriate object file.\n", prog);
1321 /* Clean up after ourselves. */
1325 /* from sh -- dac */
1326 prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
1327 sim_kind == SIM_OPEN_DEBUG,
1329 if (prog_bfd == NULL)
1333 bfd_close (prog_bfd);
1339 sim_create_inferior (sd, prog_bfd, argv, env)
1341 struct bfd * prog_bfd;
1347 sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
1349 /* Set the initial register set. */
1352 set_initial_gprs ();
1355 if (prog_bfd != NULL)
1356 cpu.asregs.regs[PC_REGNO] = bfd_get_start_address (prog_bfd);
1358 /* Copy args into target memory. */
1360 for (argc = 0; avp && *avp; avp++)
1363 /* Target memory looks like this:
1364 0x00000000 zero word
1365 0x00000004 argc word
1366 0x00000008 start of argv
1368 0x0000???? end of argv
1369 0x0000???? zero word
1370 0x0000???? start of data pointed to by argv */
1372 wlat (scpu, 0, 0, 0);
1373 wlat (scpu, 0, 4, argc);
1375 /* tp is the offset of our first argv data. */
1376 tp = 4 + 4 + argc * 4 + 4;
1378 for (i = 0; i < argc; i++)
1380 /* Set the argv value. */
1381 wlat (scpu, 0, 4 + 4 + i * 4, tp);
1383 /* Store the string. */
1384 sim_core_write_buffer (sd, scpu, write_map, argv[i],
1385 tp, strlen(argv[i])+1);
1386 tp += strlen (argv[i]) + 1;
1389 wlat (scpu, 0, 4 + 4 + i * 4, 0);
1405 sim_do_command (sd, cmd)
1409 if (sim_args_command (sd, cmd) != SIM_RC_OK)
1411 "Error: \"%s\" is not a valid moxie simulator command.\n",
1416 sim_set_callbacks (ptr)
1417 host_callback * ptr;