2 #include "sim-syscall.h"
25 #include <sys/times.h>
30 #define REG0(X) ((X) & 0x3)
31 #define REG1(X) (((X) & 0xc) >> 2)
32 #define REG0_4(X) (((X) & 0x30) >> 4)
33 #define REG0_8(X) (((X) & 0x300) >> 8)
34 #define REG1_8(X) (((X) & 0xc00) >> 10)
35 #define REG0_16(X) (((X) & 0x30000) >> 16)
36 #define REG1_16(X) (((X) & 0xc0000) >> 18)
39 INLINE_SIM_MAIN (void)
40 genericAdd(unsigned32 source, unsigned32 destReg)
45 dest = State.regs[destReg];
47 State.regs[destReg] = sum;
50 n = (sum & 0x80000000);
51 c = (sum < source) || (sum < dest);
52 v = ((dest & 0x80000000) == (source & 0x80000000)
53 && (dest & 0x80000000) != (sum & 0x80000000));
55 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
56 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
57 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
63 INLINE_SIM_MAIN (void)
64 genericSub(unsigned32 source, unsigned32 destReg)
67 unsigned32 dest, difference;
69 dest = State.regs[destReg];
70 difference = dest - source;
71 State.regs[destReg] = difference;
73 z = (difference == 0);
74 n = (difference & 0x80000000);
76 v = ((dest & 0x80000000) != (source & 0x80000000)
77 && (dest & 0x80000000) != (difference & 0x80000000));
79 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
80 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
81 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
84 INLINE_SIM_MAIN (void)
85 genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd)
90 value = rightOpnd - leftOpnd;
93 n = (value & 0x80000000);
94 c = (leftOpnd > rightOpnd);
95 v = ((rightOpnd & 0x80000000) != (leftOpnd & 0x80000000)
96 && (rightOpnd & 0x80000000) != (value & 0x80000000));
98 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
99 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
100 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
104 INLINE_SIM_MAIN (void)
105 genericOr(unsigned32 source, unsigned32 destReg)
109 State.regs[destReg] |= source;
110 z = (State.regs[destReg] == 0);
111 n = (State.regs[destReg] & 0x80000000) != 0;
112 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
113 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
117 INLINE_SIM_MAIN (void)
118 genericXor(unsigned32 source, unsigned32 destReg)
122 State.regs[destReg] ^= source;
123 z = (State.regs[destReg] == 0);
124 n = (State.regs[destReg] & 0x80000000) != 0;
125 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
126 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
130 INLINE_SIM_MAIN (void)
131 genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd)
138 n = (temp & 0x80000000) != 0;
140 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
141 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
145 INLINE_SIM_MAIN (void)
148 /* Registers passed to trap 0. */
150 /* Function number. */
151 reg_t func = State.regs[0];
153 reg_t parm1 = State.regs[1];
154 reg_t parm2 = load_word (State.regs[REG_SP] + 12);
155 reg_t parm3 = load_word (State.regs[REG_SP] + 16);
156 reg_t parm4 = load_word (State.regs[REG_SP] + 20);
158 /* We use this for simulated system calls; we may need to change
159 it to a reserved instruction if we conflict with uses at
161 int save_errno = errno;
164 if (func == TARGET_SYS_exit)
166 /* EXIT - caller can look in parm1 to work out the reason */
167 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
168 (parm1 == 0xdead ? SIM_SIGABRT : sim_exited), parm1);
172 long result, result2;
175 sim_syscall_multi (STATE_CPU (simulator, 0), func, parm1, parm2,
176 parm3, parm4, &result, &result2, &errcode);
178 /* Registers set by trap 0. */
179 State.regs[0] = errcode;
180 State.regs[1] = result;