5 #include "opcode/mn10300.h"
7 #include "remote-sim.h"
18 extern host_callback *mn10300_callback;
19 extern SIM_DESC simulator;
21 #define DEBUG_TRACE 0x00000001
22 #define DEBUG_VALUES 0x00000002
24 extern int mn10300_debug;
27 typedef unsigned char uint8;
28 typedef signed char int8;
30 #error "Char is not an 8-bit type"
34 typedef unsigned short uint16;
35 typedef signed short int16;
37 #error "Short is not a 16-bit type"
40 #if INT_MAX == 2147483647
42 typedef unsigned int uint32;
43 typedef signed int int32;
46 # if LONG_MAX == 2147483647
48 typedef unsigned long uint32;
49 typedef signed long int32;
52 # error "Neither int nor long is a 32-bit type"
69 /* The current state of the processor; registers, memory, etc. */
73 reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
74 lir, lar, mdrq, plus some room for processor
76 uint8 *mem; /* main memory */
82 extern struct simops Simops[];
84 #define PC (State.regs[REG_PC])
85 #define SP (State.regs[REG_SP])
87 #define PSW (State.regs[11])
92 #define PSW_IE LSBIT (11)
93 #define PSW_LM LSMASK (10, 8)
95 #define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
96 #define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
107 /* start-sanitize-am33 */
109 /* end-sanitize-am33 */
112 /* These definitions conflict with similar macros in common. */
114 #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
116 /* sign-extend a 4-bit number */
117 #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
119 /* sign-extend a 5-bit number */
120 #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
122 /* sign-extend an 8-bit number */
123 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
125 /* sign-extend a 9-bit number */
126 #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
128 /* sign-extend a 16-bit number */
129 #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
131 /* sign-extend a 22-bit number */
132 #define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
134 #define MAX32 0x7fffffffLL
135 #define MIN32 0xff80000000LL
136 #define MASK32 0xffffffffLL
137 #define MASK40 0xffffffffffLL
138 #endif /* not WITH_COMMON */
147 #define FETCH32(a,b,c,d) \
148 ((a)+((b)<<8)+((c)<<16)+((d)<<24))
150 #define FETCH16(a,b) ((a)+((b)<<8))
152 #define load_byte(ADDR) \
153 sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
155 #define load_half(ADDR) \
156 sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
158 #define load_word(ADDR) \
159 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
161 #define store_byte(ADDR, DATA) \
162 sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
163 PC, write_map, (ADDR), (DATA))
166 #define store_half(ADDR, DATA) \
167 sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
168 PC, write_map, (ADDR), (DATA))
171 #define store_word(ADDR, DATA) \
172 sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
173 PC, write_map, (ADDR), (DATA))
174 #endif /* WITH_COMMON */
178 #define load_mem_big(addr,len) \
179 (len == 1 ? *((addr) + State.mem) : \
180 len == 2 ? ((*((addr) + State.mem) << 8) \
181 | *(((addr) + 1) + State.mem)) : \
182 len == 3 ? ((*((addr) + State.mem) << 16) \
183 | (*(((addr) + 1) + State.mem) << 8) \
184 | *(((addr) + 2) + State.mem)) : \
185 ((*((addr) + State.mem) << 24) \
186 | (*(((addr) + 1) + State.mem) << 16) \
187 | (*(((addr) + 2) + State.mem) << 8) \
188 | *(((addr) + 3) + State.mem)))
194 uint8 *p = (addr & 0xffffff) + State.mem;
197 if ((addr & 0xffffff) > max_mem)
208 uint8 *p = (addr & 0xffffff) + State.mem;
211 if ((addr & 0xffffff) > max_mem)
215 return p[1] << 8 | p[0];
222 uint8 *p = (addr & 0xffffff) + State.mem;
225 if ((addr & 0xffffff) > max_mem)
229 return p[2] << 16 | p[1] << 8 | p[0];
236 uint8 *p = (addr & 0xffffff) + State.mem;
239 if ((addr & 0xffffff) > max_mem)
243 return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
251 uint8 *p = (addr & 0xffffff) + State.mem;
254 if ((addr & 0xffffff) > max_mem)
263 return p[1] << 8 | p[0];
265 return p[2] << 16 | p[1] << 8 | p[0];
267 return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
274 store_byte (addr, data)
278 uint8 *p = (addr & 0xffffff) + State.mem;
281 if ((addr & 0xffffff) > max_mem)
289 store_half (addr, data)
293 uint8 *p = (addr & 0xffffff) + State.mem;
296 if ((addr & 0xffffff) > max_mem)
305 store_3_byte (addr, data)
309 uint8 *p = (addr & 0xffffff) + State.mem;
312 if ((addr & 0xffffff) > max_mem)
322 store_word (addr, data)
326 uint8 *p = (addr & 0xffffff) + State.mem;
329 if ((addr & 0xffffff) > max_mem)
338 #endif /* not WITH_COMMON */
340 /* Function declarations. */
342 uint32 get_word PARAMS ((uint8 *));
343 uint16 get_half PARAMS ((uint8 *));
344 uint8 get_byte PARAMS ((uint8 *));
345 void put_word PARAMS ((uint8 *, uint32));
346 void put_half PARAMS ((uint8 *, uint16));
347 void put_byte PARAMS ((uint8 *, uint8));
349 extern uint8 *map PARAMS ((SIM_ADDR addr));
351 INLINE_SIM_MAIN (void) genericAdd PARAMS ((unsigned long source, unsigned long destReg));
352 INLINE_SIM_MAIN (void) genericSub PARAMS ((unsigned long source, unsigned long destReg));
353 INLINE_SIM_MAIN (void) genericCmp PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd));
354 INLINE_SIM_MAIN (void) genericOr PARAMS ((unsigned long source, unsigned long destReg));
355 INLINE_SIM_MAIN (void) genericXor PARAMS ((unsigned long source, unsigned long destReg));
356 INLINE_SIM_MAIN (void) genericBtst PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd));
357 INLINE_SIM_MAIN (void) do_syscall PARAMS ((void));