4 #include "gdb/callback.h"
5 #include "opcode/mn10300.h"
7 #include "gdb/remote-sim.h"
11 extern host_callback *mn10300_callback;
12 extern SIM_DESC simulator;
14 #define DEBUG_TRACE 0x00000001
15 #define DEBUG_VALUES 0x00000002
17 extern int mn10300_debug;
20 typedef unsigned char uint8;
21 typedef signed char int8;
23 #error "Char is not an 8-bit type"
27 typedef unsigned short uint16;
28 typedef signed short int16;
30 #error "Short is not a 16-bit type"
33 #if INT_MAX == 2147483647
35 typedef unsigned int uint32;
36 typedef signed int int32;
39 # if LONG_MAX == 2147483647
41 typedef unsigned long uint32;
42 typedef signed long int32;
45 # error "Neither int nor long is a 32-bit type"
66 /* The current state of the processor; registers, memory, etc. */
70 reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
71 lir, lar, mdrq, plus some room for processor
75 reg_t fs[32]; /* FS0-31 */
76 dword fd[16]; /* FD0,2,...,30 */
78 uint8 *mem; /* main memory */
82 /* All internal state modified by signal_exception() that may need to be
83 rolled back for passing moment-of-exception image back to gdb. */
84 reg_t exc_trigger_regs[32];
85 reg_t exc_suspend_regs[32];
88 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
89 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
90 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
93 extern struct _state State;
95 extern struct simops Simops[];
97 #define PC (State.regs[REG_PC])
98 #define SP (State.regs[REG_SP])
100 #define PSW (State.regs[11])
105 #define PSW_IE LSBIT (11)
106 #define PSW_LM LSMASK (10, 8)
108 #define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
109 #define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
130 #define FPCR (State.regs[REG_FPCR])
132 #define FCC_MASK LSMASK (21, 18)
133 #define RM_MASK LSMASK (17, 16) /* Must always be zero. */
134 #define EC_MASK LSMASK (14, 10)
135 #define EE_MASK LSMASK ( 9, 5)
136 #define EF_MASK LSMASK ( 4, 0)
137 #define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
139 #define FCC_L LSBIT (21)
140 #define FCC_G LSBIT (20)
141 #define FCC_E LSBIT (19)
142 #define FCC_U LSBIT (18)
144 #define EC_V LSBIT (14)
145 #define EC_Z LSBIT (13)
146 #define EC_O LSBIT (12)
147 #define EC_U LSBIT (11)
148 #define EC_I LSBIT (10)
150 #define EE_V LSBIT (9)
151 #define EE_Z LSBIT (8)
152 #define EE_O LSBIT (7)
153 #define EE_U LSBIT (6)
154 #define EE_I LSBIT (5)
156 #define EF_V LSBIT (4)
157 #define EF_Z LSBIT (3)
158 #define EF_O LSBIT (2)
159 #define EF_U LSBIT (1)
160 #define EF_I LSBIT (0)
162 #define PSW_FE LSBIT(20)
163 #define FPU_DISABLED !(PSW & PSW_FE)
165 #define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
166 #define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
167 #define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
169 #define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
170 #define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
171 #define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
172 #define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
179 #define FETCH32(a,b,c,d) \
180 ((a)+((b)<<8)+((c)<<16)+((d)<<24))
182 #define FETCH24(a,b,c) \
183 ((a)+((b)<<8)+((c)<<16))
185 #define FETCH16(a,b) ((a)+((b)<<8))
187 #define load_byte(ADDR) \
188 sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
190 #define load_half(ADDR) \
191 sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
193 #define load_word(ADDR) \
194 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
196 #define load_dword(ADDR) \
197 u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
198 PC, read_map, (ADDR)))
201 u642dw (unsigned64 dw)
205 r.low = (unsigned32)dw;
206 r.high = (unsigned32)(dw >> 32);
210 #define store_byte(ADDR, DATA) \
211 sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
212 PC, write_map, (ADDR), (DATA))
215 #define store_half(ADDR, DATA) \
216 sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
217 PC, write_map, (ADDR), (DATA))
220 #define store_word(ADDR, DATA) \
221 sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
222 PC, write_map, (ADDR), (DATA))
223 #define store_dword(ADDR, DATA) \
224 sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
225 PC, write_map, (ADDR), dw2u64 (DATA))
227 static INLINE unsigned64
230 return data.low | (((unsigned64)data.high) << 32);
233 /* Function declarations. */
235 uint32 get_word (uint8 *);
236 uint16 get_half (uint8 *);
237 uint8 get_byte (uint8 *);
238 void put_word (uint8 *, uint32);
239 void put_half (uint8 *, uint16);
240 void put_byte (uint8 *, uint8);
242 extern uint8 *map (SIM_ADDR addr);
244 INLINE_SIM_MAIN (void) genericAdd (unsigned32 source, unsigned32 destReg);
245 INLINE_SIM_MAIN (void) genericSub (unsigned32 source, unsigned32 destReg);
246 INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd, unsigned32 rightOpnd);
247 INLINE_SIM_MAIN (void) genericOr (unsigned32 source, unsigned32 destReg);
248 INLINE_SIM_MAIN (void) genericXor (unsigned32 source, unsigned32 destReg);
249 INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd, unsigned32 rightOpnd);
250 INLINE_SIM_MAIN (int) syscall_read_mem (host_callback *cb,
251 struct cb_syscall *sc,
255 INLINE_SIM_MAIN (int) syscall_write_mem (host_callback *cb,
256 struct cb_syscall *sc,
260 INLINE_SIM_MAIN (void) do_syscall (void);
261 void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
263 void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
264 void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
265 void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
267 void fpu_disabled_exception (SIM_DESC, sim_cpu *, address_word);
268 void fpu_unimp_exception (SIM_DESC, sim_cpu *, address_word);
269 void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
271 extern const struct fp_prec_t
273 void (* reg2val) (const void *, sim_fpu *);
274 int (* round) (sim_fpu *);
275 void (* val2reg) (const sim_fpu *, void *);
276 } fp_single_prec, fp_double_prec;
278 #define FP_SINGLE (&fp_single_prec)
279 #define FP_DOUBLE (&fp_double_prec)
281 void fpu_rsqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
282 void fpu_sqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
283 void fpu_cmp (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
284 void fpu_add (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
285 void fpu_sub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
286 void fpu_mul (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
287 void fpu_div (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
288 void fpu_fmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
289 void fpu_fmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
290 void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
291 void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);