5 #include "opcode/mn10300.h"
7 #include "remote-sim.h"
18 extern host_callback *mn10300_callback;
19 extern SIM_DESC simulator;
21 #define DEBUG_TRACE 0x00000001
22 #define DEBUG_VALUES 0x00000002
24 extern int mn10300_debug;
27 typedef unsigned char uint8;
28 typedef signed char int8;
30 #error "Char is not an 8-bit type"
34 typedef unsigned short uint16;
35 typedef signed short int16;
37 #error "Short is not a 16-bit type"
40 #if INT_MAX == 2147483647
42 typedef unsigned int uint32;
43 typedef signed int int32;
46 # if LONG_MAX == 2147483647
48 typedef unsigned long uint32;
49 typedef signed long int32;
52 # error "Neither int nor long is a 32-bit type"
69 /* The current state of the processor; registers, memory, etc. */
73 reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
74 lir, lar, mdrq, plus some room for processor
76 uint8 *mem; /* main memory */
80 /* All internal state modified by signal_exception() that may need to be
81 rolled back for passing moment-of-exception image back to gdb. */
82 reg_t exc_trigger_regs[32];
83 reg_t exc_suspend_regs[32];
86 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
87 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
88 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
91 extern struct _state State;
93 extern struct simops Simops[];
95 #define PC (State.regs[REG_PC])
96 #define SP (State.regs[REG_SP])
98 #define PSW (State.regs[11])
103 #define PSW_IE LSBIT (11)
104 #define PSW_LM LSMASK (10, 8)
106 #define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
107 #define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
120 /* These definitions conflict with similar macros in common. */
122 #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
124 /* sign-extend a 4-bit number */
125 #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
127 /* sign-extend a 5-bit number */
128 #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
130 /* sign-extend an 8-bit number */
131 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
133 /* sign-extend a 9-bit number */
134 #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
136 /* sign-extend a 16-bit number */
137 #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
139 /* sign-extend a 22-bit number */
140 #define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
142 #define MAX32 0x7fffffffLL
143 #define MIN32 0xff80000000LL
144 #define MASK32 0xffffffffLL
145 #define MASK40 0xffffffffffLL
146 #endif /* not WITH_COMMON */
155 #define FETCH32(a,b,c,d) \
156 ((a)+((b)<<8)+((c)<<16)+((d)<<24))
158 #define FETCH24(a,b,c) \
159 ((a)+((b)<<8)+((c)<<16))
161 #define FETCH16(a,b) ((a)+((b)<<8))
163 #define load_byte(ADDR) \
164 sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
166 #define load_half(ADDR) \
167 sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
169 #define load_word(ADDR) \
170 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
172 #define store_byte(ADDR, DATA) \
173 sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
174 PC, write_map, (ADDR), (DATA))
177 #define store_half(ADDR, DATA) \
178 sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
179 PC, write_map, (ADDR), (DATA))
182 #define store_word(ADDR, DATA) \
183 sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
184 PC, write_map, (ADDR), (DATA))
185 #endif /* WITH_COMMON */
189 #define load_mem_big(addr,len) \
190 (len == 1 ? *((addr) + State.mem) : \
191 len == 2 ? ((*((addr) + State.mem) << 8) \
192 | *(((addr) + 1) + State.mem)) : \
193 len == 3 ? ((*((addr) + State.mem) << 16) \
194 | (*(((addr) + 1) + State.mem) << 8) \
195 | *(((addr) + 2) + State.mem)) : \
196 ((*((addr) + State.mem) << 24) \
197 | (*(((addr) + 1) + State.mem) << 16) \
198 | (*(((addr) + 2) + State.mem) << 8) \
199 | *(((addr) + 3) + State.mem)))
205 uint8 *p = (addr & 0xffffff) + State.mem;
208 if ((addr & 0xffffff) > max_mem)
219 uint8 *p = (addr & 0xffffff) + State.mem;
222 if ((addr & 0xffffff) > max_mem)
226 return p[1] << 8 | p[0];
233 uint8 *p = (addr & 0xffffff) + State.mem;
236 if ((addr & 0xffffff) > max_mem)
240 return p[2] << 16 | p[1] << 8 | p[0];
247 uint8 *p = (addr & 0xffffff) + State.mem;
250 if ((addr & 0xffffff) > max_mem)
254 return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
262 uint8 *p = (addr & 0xffffff) + State.mem;
265 if ((addr & 0xffffff) > max_mem)
274 return p[1] << 8 | p[0];
276 return p[2] << 16 | p[1] << 8 | p[0];
278 return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
285 store_byte (addr, data)
289 uint8 *p = (addr & 0xffffff) + State.mem;
292 if ((addr & 0xffffff) > max_mem)
300 store_half (addr, data)
304 uint8 *p = (addr & 0xffffff) + State.mem;
307 if ((addr & 0xffffff) > max_mem)
316 store_3_byte (addr, data)
320 uint8 *p = (addr & 0xffffff) + State.mem;
323 if ((addr & 0xffffff) > max_mem)
333 store_word (addr, data)
337 uint8 *p = (addr & 0xffffff) + State.mem;
340 if ((addr & 0xffffff) > max_mem)
349 #endif /* not WITH_COMMON */
351 /* Function declarations. */
353 uint32 get_word PARAMS ((uint8 *));
354 uint16 get_half PARAMS ((uint8 *));
355 uint8 get_byte PARAMS ((uint8 *));
356 void put_word PARAMS ((uint8 *, uint32));
357 void put_half PARAMS ((uint8 *, uint16));
358 void put_byte PARAMS ((uint8 *, uint8));
360 extern uint8 *map PARAMS ((SIM_ADDR addr));
362 INLINE_SIM_MAIN (void) genericAdd PARAMS ((unsigned long source, unsigned long destReg));
363 INLINE_SIM_MAIN (void) genericSub PARAMS ((unsigned long source, unsigned long destReg));
364 INLINE_SIM_MAIN (void) genericCmp PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd));
365 INLINE_SIM_MAIN (void) genericOr PARAMS ((unsigned long source, unsigned long destReg));
366 INLINE_SIM_MAIN (void) genericXor PARAMS ((unsigned long source, unsigned long destReg));
367 INLINE_SIM_MAIN (void) genericBtst PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd));
368 INLINE_SIM_MAIN (int) syscall_read_mem PARAMS ((host_callback *cb,
369 struct cb_syscall *sc,
373 INLINE_SIM_MAIN (int) syscall_write_mem PARAMS ((host_callback *cb,
374 struct cb_syscall *sc,
378 INLINE_SIM_MAIN (void) do_syscall PARAMS ((void));
379 void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
381 void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
382 void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
383 void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);