2 :option:::insn-bit-size:8
3 :option:::insn-specifying-widths:true
5 :model:::mn10300:mn10300:
8 // What do we do with an illegal instruction?
11 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
13 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
16 // 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended)
17 4.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov
20 // start-sanitize-am33
25 signed32 immed = EXTEND8 (IMM8);
26 State.regs[REG_D0+DN0] = immed;
30 // 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn)
31 4.0x8,2.DM1,2.DN0!DM1:S0:::mov
34 // start-sanitize-am33
40 State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
44 // 1111 0001 1110 DmAn; mov Dm,An
45 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
48 // start-sanitize-am33
54 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
58 // 1111 0001 1101 AmDn; mov Am,Dn
59 8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
62 // start-sanitize-am33
68 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
72 // 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended)
73 4.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov
76 // start-sanitize-am33
82 State.regs[REG_A0+AN0] = IMM8;
86 // 1001 AmAn; mov Am,An (Am != An, save above when Am == An)
87 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
90 // start-sanitize-am33
96 State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
100 // 0011 11An; mov SP,An
101 4.0x3,11,2.AN0:S0b:::mov
104 // start-sanitize-am33
110 State.regs[REG_A0 + AN0] = State.regs[REG_SP];
114 // 1111 0010 1111 Am00; mov Am,SP
115 8.0xf2+4.0xf,2.AM1,00:D0b:::mov
118 // start-sanitize-am33
124 State.regs[REG_SP] = State.regs[REG_A0 + AM1];
128 // 1111 0010 1110 01Dn; mov PSW,Dn
129 8.0xf2+4.0xe,01,2.DN0:D0c:::mov
132 // start-sanitize-am33
138 State.regs[REG_D0 + DN0] = PSW;
142 // 1111 0010 1111 Dm11; mov Dm,PSW
143 8.0xf2+4.0xf,2.DM1,11:D0d:::mov
146 // start-sanitize-am33
152 PSW = State.regs[REG_D0 + DM1];
156 // 1111 0010 1110 00Dn; mov MDR,Dn
157 8.0xf2+4.0xe,00,2.DN0:D0e:::mov
160 // start-sanitize-am33
166 State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
170 // 1111 0010 1111 Dm10; mov Dm,MDR
171 8.0xf2+4.0xf,2.DM1,10:D0f:::mov
174 // start-sanitize-am33
180 State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
184 // 0111 DnAm; mov (Am),Dn
185 4.0x7,2.DN1,2.AM0:S0c:::mov
188 // start-sanitize-am33
194 State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
198 // 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended)
199 8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
202 // start-sanitize-am33
208 State.regs[REG_D0 + DN1]
209 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
213 // 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.)
214 8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
217 // start-sanitize-am33
221 /* OP_FA000000 (); */
223 State.regs[REG_D0 + DN1]
224 = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
228 // 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn
229 8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
232 // start-sanitize-am33
236 /* OP_FC000000 (); */
238 State.regs[REG_D0 + DN1]
239 = load_word ((State.regs[REG_A0 + AM0]
240 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
244 // 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended)
245 4.0x5,10,2.DN0+8.D8:S1:::mov
248 // start-sanitize-am33
254 State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
258 // 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.)
259 8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
262 // start-sanitize-am33
266 /* OP_FAB40000 (); */
268 State.regs[REG_D0 + DN0]
269 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
273 // 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn
274 8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
277 // start-sanitize-am33
281 /* OP_FCB40000 (); */
283 State.regs[REG_D0 + DN0]
284 = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
288 // 1111 0011 00Dn DiAm; mov (Di,Am),Dn
289 8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
292 // start-sanitize-am33
298 State.regs[REG_D0 + DN2]
299 = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
303 // 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended)
304 4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
307 // start-sanitize-am33
313 State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
316 // 1111 1100 1010 01Dn abs32...; mov (abs32),Dn
317 8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
320 // start-sanitize-am33
324 /* OP_FCA40000 (); */
326 State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
330 // 1111 0000 0000 AnAm; mov (Am),An
331 8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
334 // start-sanitize-am33
340 State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
344 // 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended)
345 8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
348 // start-sanitize-am33
354 State.regs[REG_A0 + AN1]
355 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
359 // 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.)
360 8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
363 // start-sanitize-am33
367 /* OP_FA200000 (); */
369 State.regs[REG_A0 + AN1]
370 = load_word ((State.regs[REG_A0 + AM0]
371 + EXTEND16 (FETCH16(D16A, D16B))));
375 // 1111 1100 0010 AnAm d32.....; mov (d32,Am),An
376 8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
379 // start-sanitize-am33
383 /* OP_FC200000 (); */
385 State.regs[REG_A0 + AN1]
386 = load_word ((State.regs[REG_A0 + AM0]
387 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
391 // 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended)
392 4.0x5,11,2.AN0+8.D8:S1a:::mov
395 // start-sanitize-am33
401 State.regs[REG_A0 + AN0]
402 = load_word (State.regs[REG_SP] + D8);
406 // 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.)
407 8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
410 // start-sanitize-am33
414 /* OP_FAB00000 (); */
416 State.regs[REG_A0 + AN0]
417 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
421 // 1111 1100 1011 00An d32.....; mov (d32,SP),An
422 8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
425 // start-sanitize-am33
429 /* OP_FCB00000 (); */
431 State.regs[REG_A0 + AN0]
432 = load_word (State.regs[REG_SP]
433 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
437 // 1111 0011 10An DiAm; mov (Di,Am),An
438 8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
441 // start-sanitize-am33
447 State.regs[REG_A0 + AN2]
448 = load_word ((State.regs[REG_A0 + AM0]
449 + State.regs[REG_D0 + DI]));
453 // 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended)
454 8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
457 // start-sanitize-am33
461 /* OP_FAA00000 (); */
463 State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
467 // 1111 1100 1010 00An abs32...; mov (abs32),An
468 8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
471 // start-sanitize-am33
475 /* OP_FCA00000 (); */
477 State.regs[REG_A0 + AN0]
478 = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
482 // 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended)
483 8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
486 // start-sanitize-am33
493 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
497 // 0110 DmAn; mov Dm,(An)
498 4.0x6,2.DM1,2.AN0:S0d:::mov
501 // start-sanitize-am33
507 store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
511 // 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended)
512 8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
515 // start-sanitize-am33
521 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
522 State.regs[REG_D0 + DM1]);
526 // 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.)
527 8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
530 // start-sanitize-am33
534 /* OP_FA100000 (); */
536 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
537 State.regs[REG_D0 + DM1]);
541 // 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An)
542 8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
545 // start-sanitize-am33
549 /* OP_FC100000 (); */
551 store_word ((State.regs[REG_A0 + AN0]
552 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
553 State.regs[REG_D0 + DM1]);
557 // 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended)
558 4.0x4,2.DM1,10+8.D8:S1b:::mov
561 // start-sanitize-am33
567 store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
571 // 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.)
572 8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
575 // start-sanitize-am33
579 /* OP_FA910000 (); */
581 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
582 State.regs[REG_D0 + DM1]);
586 // 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP)
587 8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
590 // start-sanitize-am33
594 /* OP_FC910000 (); */
596 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
597 State.regs[REG_D0 + DM1]);
601 // 1111 0011 01Dm DiAn; mov Dm,(Di,An)
602 8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
605 // start-sanitize-am33
611 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
612 State.regs[REG_D0 + DM2]);
616 // 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended).
617 4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
620 // start-sanitize-am33
626 store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
630 // 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32)
631 8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
634 // start-sanitize-am33
638 /* OP_FC810000 (); */
640 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
641 State.regs[REG_D0 + DM1]);
645 // 1111 0000 0001 AmAn; mov Am,(An)
646 8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
649 // start-sanitize-am33
655 store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
659 // 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended)
660 8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
663 // start-sanitize-am33
669 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
670 State.regs[REG_A0 + AM1]);
674 // 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.)
675 8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
678 // start-sanitize-am33
682 /* OP_FA300000 (); */
684 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
685 State.regs[REG_A0 + AM1]);
689 // 1111 1100 0011 AmAn d32.....; mov Am,(d32,An)
690 8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
693 // start-sanitize-am33
697 /* OP_FC300000 (); */
699 store_word ((State.regs[REG_A0 + AN0]
700 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
701 State.regs[REG_A0 + AM1]);
705 // 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended)
706 4.0x4,2.AM1,11+8.D8:S1c:::mov
709 // start-sanitize-am33
715 store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
719 // 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.)
720 8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
723 // start-sanitize-am33
727 /* OP_FA900000 (); */
729 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
730 State.regs[REG_A0 + AM1]);
734 // 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP)
735 8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
738 // start-sanitize-am33
742 /* OP_FC900000 (); */
744 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
745 State.regs[REG_A0 + AM1]);
749 // 1111 0011 11Am DiAn; mov Am,(Di,An)
750 8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
753 // start-sanitize-am33
759 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
760 State.regs[REG_A0 + AM2]);
764 // 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended)
765 8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
768 // start-sanitize-am33
772 /* OP_FA800000 (); */
774 store_word (FETCH16(IMM16A, IMM16B),
775 State.regs[REG_A0 + AM1]);
779 // 1111 1100 1000 Am00 abs32...; mov Am,(abs32)
780 8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
783 // start-sanitize-am33
787 /* OP_FC800000 (); */
789 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
790 State.regs[REG_A0 + AM1]);
794 // 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended)
795 8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
798 // start-sanitize-am33
804 store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
809 // 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended)
810 4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
813 // start-sanitize-am33
821 value = EXTEND16 (FETCH16(IMM16A, IMM16B));
822 State.regs[REG_D0 + DN0] = value;
826 // 1111 1100 1100 11Dn imm32...; mov imm32,Dn
827 8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
830 // start-sanitize-am33
834 /* OP_FCCC0000 (); */
838 value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
839 State.regs[REG_D0 + DN0] = value;
843 // 0010 01An imm16...; mov imm16,An (imm16 is zero-extended)
844 4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
847 // start-sanitize-am33
855 value = FETCH16(IMM16A, IMM16B);
856 State.regs[REG_A0 + AN0] = value;
860 // 1111 1100 1101 11An imm32...; mov imm32,An
861 8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
864 // start-sanitize-am33
868 /* OP_FCDC0000 (); */
870 State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
874 // 1111 0000 0100 DnAm; movbu (Am),Dn
875 8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
878 // start-sanitize-am33
884 State.regs[REG_D0 + DN1]
885 = load_byte (State.regs[REG_A0 + AM0]);
889 // 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended)
890 8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
893 // start-sanitize-am33
899 State.regs[REG_D0 + DN1]
900 = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
904 // 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.)
905 8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
908 // start-sanitize-am33
912 /* OP_FA400000 (); */
914 State.regs[REG_D0 + DN1]
915 = load_byte ((State.regs[REG_A0 + AM0]
916 + EXTEND16 (FETCH16(D16A, D16B))));
920 // 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn
921 8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
924 // start-sanitize-am33
928 /* OP_FC400000 (); */
930 State.regs[REG_D0 + DN1]
931 = load_byte ((State.regs[REG_A0 + AM0]
932 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
936 // 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended)
937 8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
940 // start-sanitize-am33
946 State.regs[REG_D0 + DN0]
947 = load_byte ((State.regs[REG_SP] + (D8)));
951 // 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.)
952 8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
955 // start-sanitize-am33
959 /* OP_FAB80000 (); */
961 State.regs[REG_D0 + DN0]
962 = load_byte ((State.regs[REG_SP]
963 + FETCH16(IMM16A, IMM16B)));
967 // 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn
968 8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
971 // start-sanitize-am33
975 /* OP_FCB80000 (); */
977 State.regs[REG_D0 + DN0]
978 = load_byte (State.regs[REG_SP]
979 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
983 // 1111 0100 00Dn DiAm; movbu (Di,Am),Dn
984 8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
987 // start-sanitize-am33
993 State.regs[REG_D0 + DN2]
994 = load_byte ((State.regs[REG_A0 + AM0]
995 + State.regs[REG_D0 + DI]));
999 // 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended)
1000 4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
1003 // start-sanitize-am33
1005 // end-sanitize-am33
1009 State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
1013 // 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn
1014 8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
1017 // start-sanitize-am33
1019 // end-sanitize-am33
1021 /* OP_FCA80000 (); */
1023 State.regs[REG_D0 + DN0]
1024 = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1028 // 1111 0000 0101 DmAn; movbu Dm,(An)
1029 8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
1032 // start-sanitize-am33
1034 // end-sanitize-am33
1038 store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
1042 // 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended)
1043 8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
1046 // start-sanitize-am33
1048 // end-sanitize-am33
1052 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1053 State.regs[REG_D0 + DM1]);
1057 // 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.)
1058 8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
1061 // start-sanitize-am33
1063 // end-sanitize-am33
1065 /* OP_FA500000 (); */
1067 store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1068 State.regs[REG_D0 + DM1]);
1072 // 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An)
1073 8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
1076 // start-sanitize-am33
1078 // end-sanitize-am33
1080 /* OP_FC500000 (); */
1082 store_byte ((State.regs[REG_A0 + AN0]
1083 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1084 State.regs[REG_D0 + DM1]);
1088 // 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended)
1089 8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
1092 // start-sanitize-am33
1094 // end-sanitize-am33
1098 store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
1102 // 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.)
1103 8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
1106 // start-sanitize-am33
1108 // end-sanitize-am33
1110 /* OP_FA920000 (); */
1112 store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1113 State.regs[REG_D0 + DM1]);
1117 // 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP)
1118 8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
1121 // start-sanitize-am33
1123 // end-sanitize-am33
1125 /* OP_FC920000 (); */
1127 store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1128 State.regs[REG_D0 + DM1]);
1132 // 1111 0100 01Dm DiAn; movbu Dm,(Di,An)
1133 8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
1136 // start-sanitize-am33
1138 // end-sanitize-am33
1142 store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1143 State.regs[REG_D0 + DM2]);
1147 // 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended)
1148 4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
1151 // start-sanitize-am33
1153 // end-sanitize-am33
1157 store_byte (FETCH16(IMM16A, IMM16B),
1158 State.regs[REG_D0 + DM1]);
1162 // 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32)
1163 8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
1166 // start-sanitize-am33
1168 // end-sanitize-am33
1170 /* OP_FC820000 (); */
1172 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1173 State.regs[REG_D0 + DM1]);
1177 // 1111 0000 0110 DnAm; movhu (Am),Dn
1178 8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
1181 // start-sanitize-am33
1183 // end-sanitize-am33
1187 State.regs[REG_D0 + DN1]
1188 = load_half (State.regs[REG_A0 + AM0]);
1192 // 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended)
1193 8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
1196 // start-sanitize-am33
1198 // end-sanitize-am33
1202 State.regs[REG_D0 + DN1]
1203 = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
1207 // 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.)
1208 8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
1211 // start-sanitize-am33
1213 // end-sanitize-am33
1215 /* OP_FA600000 (); */
1217 State.regs[REG_D0 + DN1]
1218 = load_half ((State.regs[REG_A0 + AM0]
1219 + EXTEND16 (FETCH16(D16A, D16B))));
1223 // 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn
1224 8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
1227 // start-sanitize-am33
1229 // end-sanitize-am33
1231 /* OP_FC600000 (); */
1233 State.regs[REG_D0 + DN1]
1234 = load_half ((State.regs[REG_A0 + AM0]
1235 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
1239 // 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended)
1240 8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
1243 // start-sanitize-am33
1245 // end-sanitize-am33
1249 State.regs[REG_D0 + DN0]
1250 = load_half ((State.regs[REG_SP] + (D8)));
1254 // 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.)
1255 8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
1258 // start-sanitize-am33
1260 // end-sanitize-am33
1262 /* OP_FABC0000 (); */
1264 State.regs[REG_D0 + DN0]
1265 = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
1269 // 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn
1270 8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
1273 // start-sanitize-am33
1275 // end-sanitize-am33
1277 /* OP_FCBC0000 (); */
1279 State.regs[REG_D0 + DN0]
1280 = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1284 // 1111 0100 10Dn DiAm; movhu (Di,Am),Dn
1285 8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
1288 // start-sanitize-am33
1290 // end-sanitize-am33
1294 State.regs[REG_D0 + DN2]
1295 = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
1299 // 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended)
1300 4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
1303 // start-sanitize-am33
1305 // end-sanitize-am33
1309 State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
1313 // 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn
1314 8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
1317 // start-sanitize-am33
1319 // end-sanitize-am33
1321 /* OP_FCAC0000 (); */
1323 State.regs[REG_D0 + DN0]
1324 = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1328 // 1111 0000 0111 DmAn; movhu Dm,(An)
1329 8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
1332 // start-sanitize-am33
1334 // end-sanitize-am33
1338 store_half (State.regs[REG_A0 + AN0],
1339 State.regs[REG_D0 + DM1]);
1343 // 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended)
1344 8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
1347 // start-sanitize-am33
1349 // end-sanitize-am33
1353 store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1354 State.regs[REG_D0 + DM1]);
1358 // 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.)
1359 8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
1362 // start-sanitize-am33
1364 // end-sanitize-am33
1366 /* OP_FA700000 (); */
1368 store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1369 State.regs[REG_D0 + DM1]);
1373 // 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An)
1374 8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
1377 // start-sanitize-am33
1379 // end-sanitize-am33
1381 /* OP_FC700000 (); */
1383 store_half ((State.regs[REG_A0 + AN0]
1384 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1385 State.regs[REG_D0 + DM1]);
1389 // 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended)
1390 8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
1393 // start-sanitize-am33
1395 // end-sanitize-am33
1399 store_half (State.regs[REG_SP] + (D8),
1400 State.regs[REG_D0 + DM1]);
1404 // 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.)
1405 8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
1408 // start-sanitize-am33
1410 // end-sanitize-am33
1412 /* OP_FA930000 (); */
1414 store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1415 State.regs[REG_D0 + DM1]);
1419 // 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP)
1420 8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
1423 // start-sanitize-am33
1425 // end-sanitize-am33
1427 /* OP_FC930000 (); */
1429 store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1430 State.regs[REG_D0 + DM1]);
1434 // 1111 0100 11Dm DiAn; movhu Dm,(Di,An)
1435 8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
1438 // start-sanitize-am33
1440 // end-sanitize-am33
1444 store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1445 State.regs[REG_D0 + DM2]);
1449 // 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended)
1450 4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
1453 // start-sanitize-am33
1455 // end-sanitize-am33
1459 store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
1463 // 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32)
1464 8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
1467 // start-sanitize-am33
1469 // end-sanitize-am33
1471 /* OP_FC830000 (); */
1473 store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1474 State.regs[REG_D0 + DM1]);
1478 // 1111 0010 1101 00Dn; ext Dn
1479 8.0xf2+4.0xd,00,2.DN0:D0:::ext
1482 // start-sanitize-am33
1484 // end-sanitize-am33
1488 if (State.regs[REG_D0 + DN0] & 0x80000000)
1489 State.regs[REG_MDR] = -1;
1491 State.regs[REG_MDR] = 0;
1495 // 0001 00Dn; extb Dn
1496 4.0x1,00,2.DN0:S0:::extb
1499 // start-sanitize-am33
1501 // end-sanitize-am33
1505 State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
1509 // 0001 01Dn; extbu Dn
1510 4.0x1,01,2.DN0:S0:::extbu
1513 // start-sanitize-am33
1515 // end-sanitize-am33
1519 State.regs[REG_D0 + DN0] &= 0xff;
1523 // 0001 10Dn; exth Dn
1524 4.0x1,10,2.DN0:S0:::exth
1527 // start-sanitize-am33
1529 // end-sanitize-am33
1533 State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
1537 // 0001 11Dn; exthu Dn
1538 4.0x1,11,2.DN0:S0:::exthu
1541 // start-sanitize-am33
1543 // end-sanitize-am33
1547 State.regs[REG_D0 + DN0] &= 0xffff;
1551 // 0000 Dn00; clr Dn
1552 4.0x0,2.DN1,00:S0:::clr
1555 // start-sanitize-am33
1557 // end-sanitize-am33
1561 State.regs[REG_D0 + DN1] = 0;
1564 PSW &= ~(PSW_V | PSW_C | PSW_N);
1568 // 1110 DmDn; add Dm,Dn
1569 4.0xe,2.DM1,2.DN0:S0:::add
1572 // start-sanitize-am33
1574 // end-sanitize-am33
1578 genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1581 // 1111 0001 0110 DmAn; add Dm,An
1582 8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
1585 // start-sanitize-am33
1587 // end-sanitize-am33
1591 genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1595 // 1111 0001 0101 AmDn; add Am,Dn
1596 8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
1599 // start-sanitize-am33
1601 // end-sanitize-am33
1605 genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1609 // 1111 0001 0111 AmAn; add Am,An
1610 8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
1613 // start-sanitize-am33
1615 // end-sanitize-am33
1619 genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1623 // 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
1624 4.0x2,10,2.DN0+8.IMM8:S1:::add
1627 // start-sanitize-am33
1629 // end-sanitize-am33
1633 genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
1637 // 1111 1010 1100 00Dn imm16...; add imm16,Dn
1638 8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
1641 // start-sanitize-am33
1643 // end-sanitize-am33
1645 /* OP_FAC00000 (); */
1647 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
1651 // 1111 1100 1100 00Dn imm32...; add imm32,Dn
1652 8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
1655 // start-sanitize-am33
1657 // end-sanitize-am33
1659 /* OP_FCC00000 (); */
1661 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1665 // 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
1666 4.0x2,00,2.AN0+8.IMM8:S1a:::add
1669 // start-sanitize-am33
1671 // end-sanitize-am33
1675 genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
1679 // 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
1680 8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
1683 // start-sanitize-am33
1685 // end-sanitize-am33
1687 /* OP_FAD00000 (); */
1689 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
1693 // 1111 1100 1101 00An imm32...; add imm32,An
1694 8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
1697 // start-sanitize-am33
1699 // end-sanitize-am33
1701 /* OP_FCD00000 (); */
1703 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1707 // 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
1708 8.0xf8+8.0xfe+8.IMM8:D1:::add
1711 // start-sanitize-am33
1713 // end-sanitize-am33
1718 /* Note: no PSW changes. */
1720 imm = EXTEND8 (IMM8);
1721 State.regs[REG_SP] += imm;
1725 // 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
1726 8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
1729 // start-sanitize-am33
1731 // end-sanitize-am33
1733 /* OP_FAFE0000 (); */
1736 /* Note: no PSW changes. */
1738 imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
1739 State.regs[REG_SP] += imm;
1743 // 1111 1100 1111 1110 imm32...; add imm32,SP
1744 8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
1747 // start-sanitize-am33
1749 // end-sanitize-am33
1751 /* OP_FCFE0000 (); */
1754 /* Note: no PSW changes. */
1756 imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1757 State.regs[REG_SP] += imm;
1761 // 1111 0001 0100 DmDn; addc Dm,Dn
1762 8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
1765 // start-sanitize-am33
1767 // end-sanitize-am33
1771 unsigned long reg1, reg2, sum;
1774 reg1 = State.regs[REG_D0 + DM1];
1775 reg2 = State.regs[REG_D0 + DN0];
1776 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
1777 State.regs[REG_D0 + DN0] = sum;
1779 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1780 n = (sum & 0x80000000);
1781 c = (sum < reg1) || (sum < reg2);
1782 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1783 && (reg2 & 0x80000000) != (sum & 0x80000000));
1785 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1786 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1787 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1791 // 1111 0001 0000 DmDn; sub Dm,Dn
1792 8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
1795 // start-sanitize-am33
1797 // end-sanitize-am33
1801 genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1804 // 1111 0001 0010 DmAn; sub DmAn
1805 8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
1808 // start-sanitize-am33
1810 // end-sanitize-am33
1814 genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1818 // 1111 0001 0001 AmDn; sub AmDn
1819 8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
1822 // start-sanitize-am33
1824 // end-sanitize-am33
1828 genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1832 // 1111 0001 0011 AmAn; sub Am,An
1833 8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
1836 // start-sanitize-am33
1838 // end-sanitize-am33
1842 genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1846 // 1111 1100 1100 01Dn imm32...; sub imm32,Dn
1847 8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
1850 // start-sanitize-am33
1852 // end-sanitize-am33
1854 /* OP_FCC40000 (); */
1856 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1860 // 1111 1100 1101 01An imm32...; sub imm32,An
1861 8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
1864 // start-sanitize-am33
1866 // end-sanitize-am33
1868 /* OP_FCD40000 (); */
1870 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1874 // 1111 0001 1000 DmDn; subc Dm,Dn
1875 8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
1878 // start-sanitize-am33
1880 // end-sanitize-am33
1884 unsigned long reg1, reg2, difference;
1887 reg1 = State.regs[REG_D0 + DM1];
1888 reg2 = State.regs[REG_D0 + DN0];
1889 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
1890 State.regs[REG_D0 + DN0] = difference;
1892 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1893 n = (difference & 0x80000000);
1895 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1896 && (reg2 & 0x80000000) != (difference & 0x80000000));
1898 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1899 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1900 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1904 // 1111 0010 0100 DmDn; mul Dm,Dn
1905 8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
1908 // start-sanitize-am33
1910 // end-sanitize-am33
1913 unsigned long long temp;
1917 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
1918 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
1919 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1920 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1921 z = (State.regs[REG_D0 + DN0] == 0);
1922 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1923 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1924 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1928 // 1111 0010 0101 DmDn; mulu Dm,Dn
1929 8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
1932 // start-sanitize-am33
1934 // end-sanitize-am33
1937 unsigned long long temp;
1941 temp = ((unsigned64)State.regs[REG_D0 + DN0]
1942 * (unsigned64)State.regs[REG_D0 + DM1]);
1943 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1944 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1945 z = (State.regs[REG_D0 + DN0] == 0);
1946 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1947 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1948 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1952 // 1111 0010 0110 DmDn; div Dm,Dn
1953 8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
1956 // start-sanitize-am33
1958 // end-sanitize-am33
1966 denom = (signed32)State.regs[REG_D0 + DM1];
1967 /* still need to check for overflow */
1968 if ( !(v = (0 == denom)) )
1970 temp = State.regs[REG_MDR];
1972 temp |= State.regs[REG_D0 + DN0];
1973 State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
1974 temp /= (signed32)State.regs[REG_D0 + DM1];
1975 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1976 z = (State.regs[REG_D0 + DN0] == 0);
1977 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1979 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1980 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
1984 // 1111 0010 0111 DmDn; divu Dm,Dn
1985 8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
1988 // start-sanitize-am33
1990 // end-sanitize-am33
1998 denom = (unsigned32)State.regs[REG_D0 + DM1];
1999 if ( !(v = (0 == denom)) )
2001 temp = State.regs[REG_MDR];
2003 temp |= State.regs[REG_D0 + DN0];
2004 State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
2005 temp /= State.regs[REG_D0 + DM1];
2006 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2007 z = (State.regs[REG_D0 + DN0] == 0);
2008 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2010 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2011 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
2015 // 0100 Dn00; inc Dn
2016 4.0x4,2.DN1,00:S0:::inc
2019 // start-sanitize-am33
2021 // end-sanitize-am33
2028 genericAdd(imm, REG_D0 + DN1);
2033 4.0x4,2.AN1,01:S0a:::inc
2036 // start-sanitize-am33
2038 // end-sanitize-am33
2042 State.regs[REG_A0 + AN1] += 1;
2046 // 0101 00An; inc4 An
2047 4.0x5,00,2.AN0:S0:::inc4
2050 // start-sanitize-am33
2052 // end-sanitize-am33
2056 State.regs[REG_A0 + AN0] += 4;
2060 // 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
2061 4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
2064 // start-sanitize-am33
2066 // end-sanitize-am33
2070 genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]);
2074 // 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
2075 4.0xa,2.DM1,2.DN0!DM1:S0:::cmp
2078 // start-sanitize-am33
2080 // end-sanitize-am33
2084 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
2088 // 1111 0001 1010 DmAn; cmp Dm,An
2089 8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
2092 // start-sanitize-am33
2094 // end-sanitize-am33
2098 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
2102 // 1111 0001 1001 AmDn; cmp Am,Dn
2103 8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
2106 // start-sanitize-am33
2108 // end-sanitize-am33
2112 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
2116 // 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
2117 4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
2120 // start-sanitize-am33
2122 // end-sanitize-am33
2127 State.regs[REG_A0 + AN0]);
2131 // 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
2132 4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
2135 // start-sanitize-am33
2137 // end-sanitize-am33
2141 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
2145 // 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
2146 8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
2149 // start-sanitize-am33
2151 // end-sanitize-am33
2153 /* OP_FAC80000 (); */
2155 genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
2156 State.regs[REG_D0 + DN0]);
2160 // 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
2161 8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
2164 // start-sanitize-am33
2166 // end-sanitize-am33
2168 /* OP_FCC80000 (); */
2170 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2171 State.regs[REG_D0 + DN0]);
2175 // 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
2176 8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
2179 // start-sanitize-am33
2181 // end-sanitize-am33
2183 /* OP_FAD80000 (); */
2185 genericCmp(FETCH16(IMM16A, IMM16B),
2186 State.regs[REG_A0 + AN0]);
2190 // 1111 1100 1101 10An imm32...; cmp imm32,An
2191 8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
2194 // start-sanitize-am33
2196 // end-sanitize-am33
2198 /* OP_FCD80000 (); */
2200 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2201 State.regs[REG_A0 + AN0]);
2205 // 1111 0010 0000 DmDn; and Dm,Dn
2206 8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
2209 // start-sanitize-am33
2211 // end-sanitize-am33
2217 State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
2218 z = (State.regs[REG_D0 + DN0] == 0);
2219 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2220 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2221 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2225 // 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
2226 8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
2229 // start-sanitize-am33
2231 // end-sanitize-am33
2237 State.regs[REG_D0 + DN0] &= IMM8;
2238 z = (State.regs[REG_D0 + DN0] == 0);
2239 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2240 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2241 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2245 // 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
2246 8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
2249 // start-sanitize-am33
2251 // end-sanitize-am33
2253 /* OP_FAE00000 (); */
2257 State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
2258 z = (State.regs[REG_D0 + DN0] == 0);
2259 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2260 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2261 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2265 // 1111 1100 1110 00Dn imm32...; and imm32,Dn
2266 8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
2269 // start-sanitize-am33
2271 // end-sanitize-am33
2273 /* OP_FCE00000 (); */
2277 State.regs[REG_D0 + DN0]
2278 &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
2279 z = (State.regs[REG_D0 + DN0] == 0);
2280 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2281 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2282 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2286 // 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
2287 8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
2290 // start-sanitize-am33
2292 // end-sanitize-am33
2294 /* OP_FAFC0000 (); */
2296 PSW &= FETCH16(IMM16A, IMM16B);
2301 // 1111 0010 0001 DmDn; or DmDn
2302 8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
2305 // start-sanitize-am33
2307 // end-sanitize-am33
2311 genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2315 // 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
2316 8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
2319 // start-sanitize-am33
2321 // end-sanitize-am33
2325 genericOr(IMM8, REG_D0 + DN0);
2329 // 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
2330 8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
2333 // start-sanitize-am33
2335 // end-sanitize-am33
2337 /* OP_FAE40000 (); */
2339 genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2343 // 1111 1100 1110 01Dn imm32...; or imm32,Dn
2344 8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
2347 // start-sanitize-am33
2349 // end-sanitize-am33
2351 /* OP_FCE40000 (); */
2353 genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2357 // 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
2358 8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
2361 // start-sanitize-am33
2363 // end-sanitize-am33
2365 /* OP_FAFD0000 (); */
2367 PSW |= FETCH16(IMM16A, IMM16B);
2371 // 1111 0010 0010 DmDn; xor Dm,Dn
2372 8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
2375 // start-sanitize-am33
2377 // end-sanitize-am33
2381 genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2385 // 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
2386 8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
2389 // start-sanitize-am33
2391 // end-sanitize-am33
2393 /* OP_FAE80000 (); */
2395 genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2399 // 1111 1100 1110 10Dn imm32...; xor imm32,Dn
2400 8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
2403 // start-sanitize-am33
2405 // end-sanitize-am33
2407 /* OP_FCE80000 (); */
2409 genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2413 // 1111 0010 0011 00Dn; not Dn
2414 8.0xf2+4.0x3,00,2.DN0:D0:::not
2417 // start-sanitize-am33
2419 // end-sanitize-am33
2425 State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
2426 z = (State.regs[REG_D0 + DN0] == 0);
2427 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2428 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2429 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2433 // 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
2434 8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
2437 // start-sanitize-am33
2439 // end-sanitize-am33
2443 genericBtst(IMM8, State.regs[REG_D0 + DN0]);
2447 // 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
2448 8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
2451 // start-sanitize-am33
2453 // end-sanitize-am33
2455 /* OP_FAEC0000 (); */
2457 genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
2461 // 1111 1100 1110 11Dn imm32...; btst imm32,Dn
2462 8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
2465 // start-sanitize-am33
2467 // end-sanitize-am33
2469 /* OP_FCEC0000 (); */
2471 genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2472 State.regs[REG_D0 + DN0]);
2476 // 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2477 8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
2480 // start-sanitize-am33
2482 // end-sanitize-am33
2484 /* OP_FE020000 (); */
2487 load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2491 // 1111 1010 1111 10An d8...... imm8....;
2492 // btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
2493 8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
2496 // start-sanitize-am33
2498 // end-sanitize-am33
2500 /* OP_FAF80000 (); */
2503 load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
2507 // 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
2508 8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
2511 // start-sanitize-am33
2513 // end-sanitize-am33
2520 temp = load_byte (State.regs[REG_A0 + AN0]);
2521 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2522 temp |= State.regs[REG_D0 + DM1];
2523 store_byte (State.regs[REG_A0 + AN0], temp);
2524 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2525 PSW |= (z ? PSW_Z : 0);
2529 // 1111 1110 0000 0000 abs32... imm8....;
2530 // bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2531 8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
2534 // start-sanitize-am33
2536 // end-sanitize-am33
2538 /* OP_FE000000 (); */
2543 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2544 z = (temp & IMM8) == 0;
2546 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2547 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2548 PSW |= (z ? PSW_Z : 0);
2552 // 1111 1010 1111 00AnAn d8...... imm8....;
2553 // bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2554 8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
2557 // start-sanitize-am33
2559 // end-sanitize-am33
2561 /* OP_FAF00000 (); */
2566 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2567 z = (temp & (IMM8)) == 0;
2569 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2570 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2571 PSW |= (z ? PSW_Z : 0);
2575 // 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
2576 8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
2579 // start-sanitize-am33
2581 // end-sanitize-am33
2588 temp = load_byte (State.regs[REG_A0 + AN0]);
2589 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2590 temp = temp & ~State.regs[REG_D0 + DM1];
2591 store_byte (State.regs[REG_A0 + AN0], temp);
2592 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2593 PSW |= (z ? PSW_Z : 0);
2597 // 1111 1110 0000 0001 abs32... imm8....;
2598 // bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2599 8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
2602 // start-sanitize-am33
2604 // end-sanitize-am33
2606 /* OP_FE010000 (); */
2611 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2612 z = (temp & IMM8) == 0;
2613 temp = temp & ~(IMM8);
2614 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2615 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2616 PSW |= (z ? PSW_Z : 0);
2620 // 1111 1010 1111 01An d8...... imm8....;
2621 // bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2622 8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
2625 // start-sanitize-am33
2627 // end-sanitize-am33
2629 /* OP_FAF40000 (); */
2634 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2635 z = (temp & (IMM8)) == 0;
2636 temp = temp & ~(IMM8);
2637 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2638 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2639 PSW |= (z ? PSW_Z : 0);
2643 // 1111 0010 1011 DmDn; asr Dm,Dn
2644 8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
2647 // start-sanitize-am33
2649 // end-sanitize-am33
2656 temp = State.regs[REG_D0 + DN0];
2658 temp >>= State.regs[REG_D0 + DM1];
2659 State.regs[REG_D0 + DN0] = temp;
2660 z = (State.regs[REG_D0 + DN0] == 0);
2661 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2662 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2663 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2667 // 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
2668 8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
2671 // start-sanitize-am33
2673 // end-sanitize-am33
2680 temp = State.regs[REG_D0 + DN0];
2683 State.regs[REG_D0 + DN0] = temp;
2684 z = (State.regs[REG_D0 + DN0] == 0);
2685 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2686 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2687 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2691 // 1111 0010 1010 DmDn; lsr Dm,Dn
2692 8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
2695 // start-sanitize-am33
2697 // end-sanitize-am33
2703 c = State.regs[REG_D0 + DN0] & 1;
2704 State.regs[REG_D0 + DN0]
2705 >>= State.regs[REG_D0 + DM1];
2706 z = (State.regs[REG_D0 + DN0] == 0);
2707 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2708 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2709 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2713 // 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
2714 8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
2717 // start-sanitize-am33
2719 // end-sanitize-am33
2725 c = State.regs[REG_D0 + DN0] & 1;
2726 State.regs[REG_D0 + DN0] >>= IMM8;
2727 z = (State.regs[REG_D0 + DN0] == 0);
2728 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2729 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2730 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2734 // 1111 0010 1001 DmDn; asl Dm,Dn
2735 8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
2738 // start-sanitize-am33
2740 // end-sanitize-am33
2746 State.regs[REG_D0 + DN0]
2747 <<= State.regs[REG_D0 + DM1];
2748 z = (State.regs[REG_D0 + DN0] == 0);
2749 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2750 PSW &= ~(PSW_Z | PSW_N);
2751 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2755 // 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
2756 8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
2759 // start-sanitize-am33
2761 // end-sanitize-am33
2767 State.regs[REG_D0 + DN0] <<= IMM8;
2768 z = (State.regs[REG_D0 + DN0] == 0);
2769 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2770 PSW &= ~(PSW_Z | PSW_N);
2771 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2775 // 0101 01Dn; als2 Dn
2776 4.0x5,01,2.DN0:S0:::asl2
2779 // start-sanitize-am33
2781 // end-sanitize-am33
2787 State.regs[REG_D0 + DN0] <<= 2;
2788 z = (State.regs[REG_D0 + DN0] == 0);
2789 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2790 PSW &= ~(PSW_Z | PSW_N);
2791 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2795 // 1111 0010 1000 01Dn; ror Dn
2796 8.0xf2+4.0x8,01,2.DN0:D0:::ror
2799 // start-sanitize-am33
2801 // end-sanitize-am33
2804 unsigned long value;
2808 value = State.regs[REG_D0 + DN0];
2812 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2813 State.regs[REG_D0 + DN0] = value;
2815 n = (value & 0x80000000) != 0;
2816 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2817 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2821 // 1111 0010 1000 00Dn; rol Dn
2822 8.0xf2+4.0x8,00,2.DN0:D0:::rol
2825 // start-sanitize-am33
2827 // end-sanitize-am33
2830 unsigned long value;
2834 value = State.regs[REG_D0 + DN0];
2835 c = (value & 0x80000000) ? 1 : 0;
2838 value |= ((PSW & PSW_C) != 0);
2839 State.regs[REG_D0 + DN0] = value;
2841 n = (value & 0x80000000) != 0;
2842 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2843 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2847 // 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
2848 8.0xc8+8.D8:S1:::beq
2851 // start-sanitize-am33
2853 // end-sanitize-am33
2859 State.regs[REG_PC] += EXTEND8 (D8);
2865 // 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
2866 8.0xc9+8.D8:S1:::bne
2869 // start-sanitize-am33
2871 // end-sanitize-am33
2877 State.regs[REG_PC] += EXTEND8 (D8);
2883 // 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
2884 8.0xc1+8.D8:S1:::bgt
2887 // start-sanitize-am33
2889 // end-sanitize-am33
2894 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2896 State.regs[REG_PC] += EXTEND8 (D8);
2902 // 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
2903 8.0xc2+8.D8:S1:::bge
2906 // start-sanitize-am33
2908 // end-sanitize-am33
2912 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2914 State.regs[REG_PC] += EXTEND8 (D8);
2920 // 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
2921 8.0xc3+8.D8:S1:::ble
2924 // start-sanitize-am33
2926 // end-sanitize-am33
2931 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2933 State.regs[REG_PC] += EXTEND8 (D8);
2939 // 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
2940 8.0xc0+8.D8:S1:::blt
2943 // start-sanitize-am33
2945 // end-sanitize-am33
2949 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2951 State.regs[REG_PC] += EXTEND8 (D8);
2957 // 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
2958 8.0xc5+8.D8:S1:::bhi
2961 // start-sanitize-am33
2963 // end-sanitize-am33
2967 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2969 State.regs[REG_PC] += EXTEND8 (D8);
2975 // 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
2976 8.0xc6+8.D8:S1:::bcc
2979 // start-sanitize-am33
2981 // end-sanitize-am33
2987 State.regs[REG_PC] += EXTEND8 (D8);
2993 // 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
2994 8.0xc7+8.D8:S1:::bls
2997 // start-sanitize-am33
2999 // end-sanitize-am33
3003 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
3005 State.regs[REG_PC] += EXTEND8 (D8);
3011 // 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
3012 8.0xc4+8.D8:S1:::bcs
3015 // start-sanitize-am33
3017 // end-sanitize-am33
3023 State.regs[REG_PC] += EXTEND8 (D8);
3029 // 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
3030 8.0xf8+8.0xe8+8.D8:D1:::bvc
3033 // start-sanitize-am33
3035 // end-sanitize-am33
3041 State.regs[REG_PC] += EXTEND8 (D8);
3047 // 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
3048 8.0xf8+8.0xe9+8.D8:D1:::bvs
3051 // start-sanitize-am33
3053 // end-sanitize-am33
3059 State.regs[REG_PC] += EXTEND8 (D8);
3065 // 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
3066 8.0xf8+8.0xea+8.D8:D1:::bnc
3069 // start-sanitize-am33
3071 // end-sanitize-am33
3077 State.regs[REG_PC] += EXTEND8 (D8);
3083 // 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
3084 8.0xf8+8.0xeb+8.D8:D1:::bns
3087 // start-sanitize-am33
3089 // end-sanitize-am33
3095 State.regs[REG_PC] += EXTEND8 (D8);
3101 // 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
3102 8.0xca+8.D8:S1:::bra
3105 // start-sanitize-am33
3107 // end-sanitize-am33
3111 State.regs[REG_PC] += EXTEND8 (D8);
3120 // start-sanitize-am33
3122 // end-sanitize-am33
3128 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3138 // start-sanitize-am33
3140 // end-sanitize-am33
3146 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3156 // start-sanitize-am33
3158 // end-sanitize-am33
3163 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
3165 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3175 // start-sanitize-am33
3177 // end-sanitize-am33
3181 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3183 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3193 // start-sanitize-am33
3195 // end-sanitize-am33
3200 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3202 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3212 // start-sanitize-am33
3214 // end-sanitize-am33
3218 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
3220 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3230 // start-sanitize-am33
3232 // end-sanitize-am33
3236 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
3238 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3248 // start-sanitize-am33
3250 // end-sanitize-am33
3256 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3266 // start-sanitize-am33
3268 // end-sanitize-am33
3272 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
3274 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3284 // start-sanitize-am33
3286 // end-sanitize-am33
3292 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3302 // start-sanitize-am33
3304 // end-sanitize-am33
3308 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3317 // start-sanitize-am33
3319 // end-sanitize-am33
3323 State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
3324 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
3328 // 1111 0000 1111 01An; jmp (An)
3329 8.0xf0+4.0xf,01,2.AN0:D0:::jmp
3332 // start-sanitize-am33
3334 // end-sanitize-am33
3337 PC = load_word (State.regs[REG_A0 + AN0]);
3342 // 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
3343 8.0xcc+8.D16A+8.D16B:S2:::jmp
3346 // start-sanitize-am33
3348 // end-sanitize-am33
3351 PC = cia + EXTEND16(FETCH16(D16A, D16B));
3356 // 1101 1100 d32........; jmp (d32, PC)
3357 8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
3360 // start-sanitize-am33
3362 // end-sanitize-am33
3364 /* OP_DC000000 (); */
3365 PC = cia + FETCH32(D32A, D32B, D32C, D32D);
3370 // 1111 0000 1111 00An; calls (An)
3371 8.0xf0+4.0xf,00,2.AN0:D0:::calls
3374 // start-sanitize-am33
3376 // end-sanitize-am33
3379 unsigned int next_pc, sp;
3382 sp = State.regs[REG_SP];
3383 next_pc = State.regs[REG_PC] + 2;
3384 store_word(sp, next_pc);
3385 State.regs[REG_MDR] = next_pc;
3386 State.regs[REG_PC] = State.regs[REG_A0 + AN0];
3391 // 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
3392 8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
3395 // start-sanitize-am33
3397 // end-sanitize-am33
3399 /* OP_FAFF0000 (); */
3400 unsigned int next_pc, sp;
3403 sp = State.regs[REG_SP];
3404 next_pc = State.regs[REG_PC] + 4;
3405 store_word(sp, next_pc);
3406 State.regs[REG_MDR] = next_pc;
3407 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
3412 // 1111 1100 1111 1111 d32.....; calls (d32,PC)
3413 8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
3416 // start-sanitize-am33
3418 // end-sanitize-am33
3420 /* OP_FCFF0000 (); */
3421 unsigned int next_pc, sp;
3424 sp = State.regs[REG_SP];
3425 next_pc = State.regs[REG_PC] + 6;
3426 store_word(sp, next_pc);
3427 State.regs[REG_MDR] = next_pc;
3428 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3433 // 1111 0000 1111 1100; rets
3434 8.0xf0+8.0xfc:D0:::rets
3437 // start-sanitize-am33
3439 // end-sanitize-am33
3444 sp = State.regs[REG_SP];
3445 State.regs[REG_PC] = load_word(sp);
3450 // 1111 0000 1111 1101; rti
3451 8.0xf0+8.0xfd:D0:::rti
3454 // start-sanitize-am33
3456 // end-sanitize-am33
3461 sp = State.regs[REG_SP];
3462 PSW = load_half(sp);
3463 State.regs[REG_PC] = load_word(sp+4);
3464 State.regs[REG_SP] +=8;
3469 // 1111 0000 1111 1110; trap
3470 8.0xf0+8.0xfe:D0:::trap
3473 // start-sanitize-am33
3475 // end-sanitize-am33
3478 unsigned int sp, next_pc;
3481 sp = State.regs[REG_SP];
3482 next_pc = State.regs[REG_PC] + 2;
3483 store_word(sp, next_pc);
3488 // 1111 0000 1111 1111; rtm
3489 8.0xf0+8.0xff:D0:::rtm
3492 // start-sanitize-am33
3494 // end-sanitize-am33
3506 // start-sanitize-am33
3508 // end-sanitize-am33
3515 // 1111 0101 0000 DmDn; udf20 Dm,Dm
3516 8.0xf5+4.0x0,2.DM1,2.DM0:D0:::putx
3522 State.regs[REG_MDRQ] = State.regs[REG_D0 + DM0];
3526 // 1111 0110 1111 DmDn; udf15 Dn,Dn
3527 8.0xf6+4.0xf,2.DN1,2.DN0:D0:::getx
3530 // start-sanitize-am33
3532 // end-sanitize-am33
3538 z = (State.regs[REG_MDRQ] == 0);
3539 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
3540 State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
3542 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3543 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
3547 // 1111 0110 0000 DmDn; udf00 Dm,Dn
3548 8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
3551 // start-sanitize-am33
3553 // end-sanitize-am33
3556 unsigned long long temp;
3560 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3561 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
3562 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3563 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3564 z = (State.regs[REG_D0 + DN0] == 0);
3565 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3566 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3567 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3571 // 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
3572 8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
3575 // start-sanitize-am33
3577 // end-sanitize-am33
3580 unsigned long long temp;
3584 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3585 * (signed64)(signed32)EXTEND8 (IMM8));
3586 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3587 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3588 z = (State.regs[REG_D0 + DN0] == 0);
3589 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3590 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3591 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3595 // 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
3596 8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
3599 // start-sanitize-am33
3601 // end-sanitize-am33
3603 /* OP_FB000000 (); */
3604 unsigned long long temp;
3608 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3609 * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
3610 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3611 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3612 z = (State.regs[REG_D0 + DN0] == 0);
3613 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3614 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3615 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3619 // 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
3620 8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
3623 // start-sanitize-am33
3625 // end-sanitize-am33
3627 /* OP_FD000000 (); */
3628 unsigned long long temp;
3632 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3633 * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3634 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3635 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3636 z = (State.regs[REG_D0 + DN0] == 0);
3637 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3638 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3639 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3643 // 1111 0110 0001 DmDn; udf01 Dm,Dn
3644 8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
3647 // start-sanitize-am33
3649 // end-sanitize-am33
3652 unsigned long long temp;
3656 temp = ((unsigned64) State.regs[REG_D0 + DN0]
3657 * (unsigned64) State.regs[REG_D0 + DM1]);
3658 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3659 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3660 z = (State.regs[REG_D0 + DN0] == 0);
3661 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3662 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3663 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3667 // 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
3668 8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
3671 // start-sanitize-am33
3673 // end-sanitize-am33
3676 unsigned long long temp;
3680 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3681 * (unsigned64)EXTEND8 (IMM8));
3682 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3683 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3684 z = (State.regs[REG_D0 + DN0] == 0);
3685 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3686 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3687 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3691 // 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
3692 8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
3695 // start-sanitize-am33
3697 // end-sanitize-am33
3699 /* OP_FB140000 (); */
3700 unsigned long long temp;
3704 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3705 * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
3706 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3707 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3708 z = (State.regs[REG_D0 + DN0] == 0);
3709 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3710 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3711 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3715 // 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
3716 8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
3719 // start-sanitize-am33
3721 // end-sanitize-am33
3723 /* OP_FD140000 (); */
3724 unsigned long long temp;
3728 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3729 * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3730 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3731 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3732 z = (State.regs[REG_D0 + DN0] == 0);
3733 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3734 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3735 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3739 // 1111 0110 0100 DmDn; udf04 Dm,Dn
3740 8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
3743 // start-sanitize-am33
3745 // end-sanitize-am33
3751 temp = State.regs[REG_D0 + DM1];
3752 temp = (temp > 0x7fff ? 0x7fff : temp);
3753 temp = (temp < -0x8000 ? -0x8000 : temp);
3754 State.regs[REG_D0 + DN0] = temp;
3758 // 1111 0110 0101 DmDn; udf05 Dm,Dn
3759 8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
3762 // start-sanitize-am33
3764 // end-sanitize-am33
3770 temp = State.regs[REG_D0 + DM1];
3771 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3772 temp = (temp < -0x800000 ? -0x800000 : temp);
3773 State.regs[REG_D0 + DN0] = temp;
3777 // 1111 0110 0111 DmDn; udf07 Dm,Dn
3778 8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
3781 // start-sanitize-am33
3783 // end-sanitize-am33
3789 temp = State.regs[REG_D0 + DM1];
3790 temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
3791 c = (temp != 0 ? 1 : 0);
3793 PSW |= (c ? PSW_C : 0);
3797 // 1111 0000 1100 0000; syscall
3798 8.0xf0+8.0xc0:D0:::syscall
3801 // start-sanitize-am33
3803 // end-sanitize-am33
3815 // start-sanitize-am33
3817 // end-sanitize-am33
3821 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
3825 // 1100 1110 regs....; movm (SP),regs
3826 8.0xce+8.REGS:S1:::movm
3829 // start-sanitize-am33
3831 // end-sanitize-am33
3834 unsigned long sp = State.regs[REG_SP];
3843 State.regs[REG_LAR] = load_word (sp);
3845 State.regs[REG_LIR] = load_word (sp);
3847 State.regs[REG_MDR] = load_word (sp);
3849 State.regs[REG_A0 + 1] = load_word (sp);
3851 State.regs[REG_A0] = load_word (sp);
3853 State.regs[REG_D0 + 1] = load_word (sp);
3855 State.regs[REG_D0] = load_word (sp);
3861 State.regs[REG_A0 + 3] = load_word (sp);
3867 State.regs[REG_A0 + 2] = load_word (sp);
3873 State.regs[REG_D0 + 3] = load_word (sp);
3879 State.regs[REG_D0 + 2] = load_word (sp);
3883 /* start-sanitize-am33 */
3884 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
3888 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
3890 State.regs[REG_E0 + 1] = load_word (sp);
3892 State.regs[REG_E0 + 0] = load_word (sp);
3898 State.regs[REG_E0 + 7] = load_word (sp);
3900 State.regs[REG_E0 + 6] = load_word (sp);
3902 State.regs[REG_E0 + 5] = load_word (sp);
3904 State.regs[REG_E0 + 4] = load_word (sp);
3910 State.regs[REG_E0 + 3] = load_word (sp);
3912 State.regs[REG_E0 + 2] = load_word (sp);
3916 /* end-sanitize-am33 */
3918 /* And make sure to update the stack pointer. */
3919 State.regs[REG_SP] = sp;
3923 // 1100 1111 regs....; movm regs,(SP)
3924 8.0xcf+8.REGS:S1a:::movm
3927 // start-sanitize-am33
3929 // end-sanitize-am33
3932 unsigned long sp = State.regs[REG_SP];
3938 /* start-sanitize-am33 */
3939 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
3944 store_word (sp, State.regs[REG_E0 + 2]);
3946 store_word (sp, State.regs[REG_E0 + 3]);
3952 store_word (sp, State.regs[REG_E0 + 4]);
3954 store_word (sp, State.regs[REG_E0 + 5]);
3956 store_word (sp, State.regs[REG_E0 + 6]);
3958 store_word (sp, State.regs[REG_E0 + 7]);
3964 store_word (sp, State.regs[REG_E0 + 0]);
3966 store_word (sp, State.regs[REG_E0 + 1]);
3968 /* Need to save MDQR, MCRH, MCRL, and MCVF */
3971 /* end-sanitize-am33 */
3976 store_word (sp, State.regs[REG_D0 + 2]);
3982 store_word (sp, State.regs[REG_D0 + 3]);
3988 store_word (sp, State.regs[REG_A0 + 2]);
3994 store_word (sp, State.regs[REG_A0 + 3]);
4000 store_word (sp, State.regs[REG_D0]);
4002 store_word (sp, State.regs[REG_D0 + 1]);
4004 store_word (sp, State.regs[REG_A0]);
4006 store_word (sp, State.regs[REG_A0 + 1]);
4008 store_word (sp, State.regs[REG_MDR]);
4010 store_word (sp, State.regs[REG_LIR]);
4012 store_word (sp, State.regs[REG_LAR]);
4016 /* And make sure to update the stack pointer. */
4017 State.regs[REG_SP] = sp;
4020 // 1100 1101 d16..... regs.... imm8....;
4021 // call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.)
4022 8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
4025 // start-sanitize-am33
4027 // end-sanitize-am33
4029 /* OP_CD000000 (); */
4030 unsigned int next_pc, sp;
4034 sp = State.regs[REG_SP];
4036 store_word(sp, next_pc);
4040 /* start-sanitize-am33 */
4041 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4046 store_word (sp, State.regs[REG_E0 + 2]);
4048 store_word (sp, State.regs[REG_E0 + 3]);
4054 store_word (sp, State.regs[REG_E0 + 4]);
4056 store_word (sp, State.regs[REG_E0 + 5]);
4058 store_word (sp, State.regs[REG_E0 + 6]);
4060 store_word (sp, State.regs[REG_E0 + 7]);
4066 store_word (sp, State.regs[REG_E0 + 0]);
4068 store_word (sp, State.regs[REG_E0 + 1]);
4070 /* Need to save MDQR, MCRH, MCRL, and MCVF */
4073 /* end-sanitize-am33 */
4078 store_word (sp, State.regs[REG_D0 + 2]);
4084 store_word (sp, State.regs[REG_D0 + 3]);
4090 store_word (sp, State.regs[REG_A0 + 2]);
4096 store_word (sp, State.regs[REG_A0 + 3]);
4102 store_word (sp, State.regs[REG_D0]);
4104 store_word (sp, State.regs[REG_D0 + 1]);
4106 store_word (sp, State.regs[REG_A0]);
4108 store_word (sp, State.regs[REG_A0 + 1]);
4110 store_word (sp, State.regs[REG_MDR]);
4112 store_word (sp, State.regs[REG_LIR]);
4114 store_word (sp, State.regs[REG_LAR]);
4118 /* Update the stack pointer, note that the register saves to do not
4119 modify SP. The SP adjustment is derived totally from the imm8
4121 State.regs[REG_SP] -= IMM8;
4122 State.regs[REG_MDR] = next_pc;
4123 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
4128 // 1101 1101 d32..... regs.... imm8....;
4129 // call (d32,PC),regs,imm8 (imm8 is zero-extended.)
4130 8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
4133 // start-sanitize-am33
4135 // end-sanitize-am33
4137 /* OP_DD000000 (); */
4138 unsigned int next_pc, sp;
4142 sp = State.regs[REG_SP];
4143 next_pc = State.regs[REG_PC] + 7;
4144 /* could assert that nia == next_pc here */
4145 store_word(sp, next_pc);
4149 /* start-sanitize-am33 */
4150 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4155 store_word (sp, State.regs[REG_E0 + 2]);
4157 store_word (sp, State.regs[REG_E0 + 3]);
4163 store_word (sp, State.regs[REG_E0 + 4]);
4165 store_word (sp, State.regs[REG_E0 + 5]);
4167 store_word (sp, State.regs[REG_E0 + 6]);
4169 store_word (sp, State.regs[REG_E0 + 7]);
4175 store_word (sp, State.regs[REG_E0 + 0]);
4177 store_word (sp, State.regs[REG_E0 + 1]);
4179 /* Need to save MDQR, MCRH, MCRL, and MCVF */
4182 /* end-sanitize-am33 */
4187 store_word (sp, State.regs[REG_D0 + 2]);
4193 store_word (sp, State.regs[REG_D0 + 3]);
4199 store_word (sp, State.regs[REG_A0 + 2]);
4205 store_word (sp, State.regs[REG_A0 + 3]);
4211 store_word (sp, State.regs[REG_D0]);
4213 store_word (sp, State.regs[REG_D0 + 1]);
4215 store_word (sp, State.regs[REG_A0]);
4217 store_word (sp, State.regs[REG_A0 + 1]);
4219 store_word (sp, State.regs[REG_MDR]);
4221 store_word (sp, State.regs[REG_LIR]);
4223 store_word (sp, State.regs[REG_LAR]);
4227 /* Update the stack pointer, note that the register saves to do not
4228 modify SP. The SP adjustment is derived totally from the imm8
4230 State.regs[REG_SP] -= IMM8;
4231 State.regs[REG_MDR] = next_pc;
4232 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
4237 // 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.)
4238 8.0xdf+8.REGS+8.IMM8:S2:::ret
4241 // start-sanitize-am33
4243 // end-sanitize-am33
4246 unsigned int sp, offset;
4250 State.regs[REG_SP] += IMM8;
4251 sp = State.regs[REG_SP];
4256 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4261 State.regs[REG_E0 + 2] = load_word (sp + offset);
4263 State.regs[REG_E0 + 3] = load_word (sp + offset);
4269 State.regs[REG_E0 + 4] = load_word (sp + offset);
4271 State.regs[REG_E0 + 5] = load_word (sp + offset);
4273 State.regs[REG_E0 + 6] = load_word (sp + offset);
4275 State.regs[REG_E0 + 7] = load_word (sp + offset);
4281 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
4283 State.regs[REG_E0 + 0] = load_word (sp + offset);
4285 State.regs[REG_E0 + 1] = load_word (sp + offset);
4293 State.regs[REG_D0 + 2] = load_word (sp + offset);
4299 State.regs[REG_D0 + 3] = load_word (sp + offset);
4305 State.regs[REG_A0 + 2] = load_word (sp + offset);
4311 State.regs[REG_A0 + 3] = load_word (sp + offset);
4317 State.regs[REG_D0] = load_word (sp + offset);
4319 State.regs[REG_D0 + 1] = load_word (sp + offset);
4321 State.regs[REG_A0] = load_word (sp + offset);
4323 State.regs[REG_A0 + 1] = load_word (sp + offset);
4325 State.regs[REG_MDR] = load_word (sp + offset);
4327 State.regs[REG_LIR] = load_word (sp + offset);
4329 State.regs[REG_LAR] = load_word (sp + offset);
4333 /* Restore the PC value. */
4334 State.regs[REG_PC] = load_word(sp);
4339 // 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.)
4340 8.0xde+8.REGS+8.IMM8:S2:::retf
4343 // start-sanitize-am33
4345 // end-sanitize-am33
4348 unsigned int sp, offset;
4352 State.regs[REG_SP] += IMM8;
4353 sp = State.regs[REG_SP];
4354 State.regs[REG_PC] = State.regs[REG_MDR] - 3;
4359 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4364 State.regs[REG_E0 + 2] = load_word (sp + offset);
4366 State.regs[REG_E0 + 3] = load_word (sp + offset);
4372 State.regs[REG_E0 + 4] = load_word (sp + offset);
4374 State.regs[REG_E0 + 5] = load_word (sp + offset);
4376 State.regs[REG_E0 + 6] = load_word (sp + offset);
4378 State.regs[REG_E0 + 7] = load_word (sp + offset);
4384 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
4386 State.regs[REG_E0 + 0] = load_word (sp + offset);
4388 State.regs[REG_E0 + 1] = load_word (sp + offset);
4396 State.regs[REG_D0 + 2] = load_word (sp + offset);
4402 State.regs[REG_D0 + 3] = load_word (sp + offset);
4408 State.regs[REG_A0 + 2] = load_word (sp + offset);
4414 State.regs[REG_A0 + 3] = load_word (sp + offset);
4420 State.regs[REG_D0] = load_word (sp + offset);
4422 State.regs[REG_D0 + 1] = load_word (sp + offset);
4424 State.regs[REG_A0] = load_word (sp + offset);
4426 State.regs[REG_A0 + 1] = load_word (sp + offset);
4428 State.regs[REG_MDR] = load_word (sp + offset);
4430 State.regs[REG_LIR] = load_word (sp + offset);
4432 State.regs[REG_LAR] = load_word (sp + offset);
4437 // start-sanitize-am33
4438 :include::am33:am33.igen
4439 // end-sanitize-am33