1 /* This file is part of the program GDB, the GNU debugger.
3 Copyright (C) 1998-2016 Free Software Foundation, Inc.
4 Contributed by Cygnus Solutions.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "sim-assert.h"
28 mn103tim - mn103002 timers (8 and 16 bit)
33 Implements the mn103002 8 and 16 bit timers as described in the mn103002 user guide.
38 reg = <8bit-timers-addr> <8bit-timers-size> <16bit-timers-addr> <16bit-timers-size>
46 /* The timers' register address blocks */
48 struct mn103tim_block {
53 enum { TIMER8_BLOCK, TIMER16_BLOCK, NR_TIMER_BLOCKS };
55 enum timer_register_types {
57 TM0MD = FIRST_MODE_REG,
64 LAST_MODE_REG = TM6MD,
66 TM0BR = FIRST_BASE_REG,
72 LAST_BASE_REG = TM5BR,
74 TM0BC = FIRST_COUNTER,
86 LAST_TIMER_REG = TM6BC,
90 /* Don't include timer 6 because it's handled specially. */
91 #define NR_8BIT_TIMERS 4
92 #define NR_16BIT_TIMERS 2
93 #define NR_REG_TIMERS 6 /* Exclude timer 6 - it's handled specially. */
96 typedef struct _mn10300_timer_regs {
101 typedef struct _mn10300_timer {
102 unsigned32 div_ratio, start;
103 struct hw_event *event;
108 struct mn103tim_block block[NR_TIMER_BLOCKS];
109 mn10300_timer_regs reg[NR_REG_TIMERS];
110 mn10300_timer timer[NR_TIMERS];
112 /* treat timer 6 registers specially. */
113 unsigned16 tm6md0, tm6md1, tm6bc, tm6ca, tm6cb;
114 unsigned8 tm6mda, tm6mdb; /* compare/capture mode regs for timer 6 */
117 /* output port ID's */
133 static const struct hw_port_descriptor mn103tim_ports[] = {
135 { "timer-0-underflow", TIMER0_UFLOW, 0, output_port, },
136 { "timer-1-underflow", TIMER1_UFLOW, 0, output_port, },
137 { "timer-2-underflow", TIMER2_UFLOW, 0, output_port, },
138 { "timer-3-underflow", TIMER3_UFLOW, 0, output_port, },
139 { "timer-4-underflow", TIMER4_UFLOW, 0, output_port, },
140 { "timer-5-underflow", TIMER5_UFLOW, 0, output_port, },
142 { "timer-6-underflow", TIMER6_UFLOW, 0, output_port, },
143 { "timer-6-compare-a", TIMER6_CMPA, 0, output_port, },
144 { "timer-6-compare-b", TIMER6_CMPB, 0, output_port, },
149 #define bits2to5_mask 0x3c
150 #define bits0to2_mask 0x07
151 #define load_mask 0x40
152 #define count_mask 0x80
153 #define count_and_load_mask (load_mask | count_mask)
154 #define clock_mask 0x03
155 #define clk_ioclk 0x00
156 #define clk_cascaded 0x03
159 /* Finish off the partially created hw device. Attach our local
160 callbacks. Wire up our port names etc */
162 static hw_io_read_buffer_method mn103tim_io_read_buffer;
163 static hw_io_write_buffer_method mn103tim_io_write_buffer;
166 attach_mn103tim_regs (struct hw *me,
167 struct mn103tim *timers)
170 if (hw_find_property (me, "reg") == NULL)
171 hw_abort (me, "Missing \"reg\" property");
172 for (i = 0; i < NR_TIMER_BLOCKS; i++)
174 unsigned_word attach_address;
176 unsigned attach_size;
177 reg_property_spec reg;
178 if (!hw_find_reg_array_property (me, "reg", i, ®))
179 hw_abort (me, "\"reg\" property must contain three addr/size entries");
180 hw_unit_address_to_attach_address (hw_parent (me),
185 timers->block[i].base = attach_address;
186 hw_unit_size_to_attach_size (hw_parent (me),
189 timers->block[i].bound = attach_address + (attach_size - 1);
190 hw_attach_address (hw_parent (me),
192 attach_space, attach_address, attach_size,
198 mn103tim_finish (struct hw *me)
200 struct mn103tim *timers;
203 timers = HW_ZALLOC (me, struct mn103tim);
204 set_hw_data (me, timers);
205 set_hw_io_read_buffer (me, mn103tim_io_read_buffer);
206 set_hw_io_write_buffer (me, mn103tim_io_write_buffer);
207 set_hw_ports (me, mn103tim_ports);
209 /* Attach ourself to our parent bus */
210 attach_mn103tim_regs (me, timers);
212 /* Initialize the timers */
213 for ( i=0; i < NR_REG_TIMERS; ++i )
215 timers->reg[i].mode = 0x00;
216 timers->reg[i].base = 0;
218 for ( i=0; i < NR_TIMERS; ++i )
220 timers->timer[i].event = NULL;
221 timers->timer[i].div_ratio = 0;
222 timers->timer[i].start = 0;
224 timers->tm6md0 = 0x00;
225 timers->tm6md1 = 0x00;
226 timers->tm6bc = 0x0000;
227 timers->tm6ca = 0x0000;
228 timers->tm6cb = 0x0000;
229 timers->tm6mda = 0x00;
230 timers->tm6mdb = 0x00;
238 decode_addr (struct hw *me,
239 struct mn103tim *timers,
240 unsigned_word address)
242 unsigned_word offset;
243 offset = address - timers->block[0].base;
247 case 0x00: return TM0MD;
248 case 0x01: return TM1MD;
249 case 0x02: return TM2MD;
250 case 0x03: return TM3MD;
251 case 0x10: return TM0BR;
252 case 0x11: return TM1BR;
253 case 0x12: return TM2BR;
254 case 0x13: return TM3BR;
255 case 0x20: return TM0BC;
256 case 0x21: return TM1BC;
257 case 0x22: return TM2BC;
258 case 0x23: return TM3BC;
259 case 0x80: return TM4MD;
260 case 0x82: return TM5MD;
261 case 0x84: /* fall through */
262 case 0x85: return TM6MD;
263 case 0x90: return TM4BR;
264 case 0x92: return TM5BR;
265 case 0xa0: return TM4BC;
266 case 0xa2: return TM5BC;
267 case 0xa4: return TM6BC;
268 case 0xb4: return TM6MDA;
269 case 0xb5: return TM6MDB;
270 case 0xc4: return TM6CA;
271 case 0xd4: return TM6CB;
274 hw_abort (me, "bad address");
281 read_mode_reg (struct hw *me,
282 struct mn103tim *timers,
293 /* Accessing 1 byte is ok for all mode registers. */
296 *(unsigned8*)dest = timers->tm6md0;
300 *(unsigned8*)dest = timers->reg[timer_nr].mode;
307 *(unsigned16 *)dest = (timers->tm6md0 << 8) | timers->tm6md1;
309 else if ( timer_nr == 0 || timer_nr == 2 )
311 val16 = (timers->reg[timer_nr].mode << 8)
312 | timers->reg[timer_nr+1].mode;
313 *(unsigned16*)dest = val16;
317 hw_abort (me, "bad read size of 2 bytes to TM%dMD.", timer_nr);
324 val32 = (timers->reg[0].mode << 24 )
325 | (timers->reg[1].mode << 16)
326 | (timers->reg[2].mode << 8)
327 | timers->reg[3].mode;
328 *(unsigned32*)dest = val32;
332 hw_abort (me, "bad read size of 4 bytes to TM%dMD.", timer_nr);
337 hw_abort (me, "bad read size of %d bytes to TM%dMD.",
344 read_base_reg (struct hw *me,
345 struct mn103tim *timers,
353 /* Check nr_bytes: accesses of 1, 2 and 4 bytes allowed depending on timer. */
357 /* Reading 1 byte is ok for all registers. */
358 if ( timer_nr < NR_8BIT_TIMERS )
360 *(unsigned8*)dest = timers->reg[timer_nr].base;
365 if ( timer_nr == 1 || timer_nr == 3 )
367 hw_abort (me, "bad read size of 2 bytes to TM%dBR.", timer_nr);
371 if ( timer_nr < NR_8BIT_TIMERS )
373 val16 = (timers->reg[timer_nr].base<<8)
374 | timers->reg[timer_nr+1].base;
378 val16 = timers->reg[timer_nr].base;
380 *(unsigned16*)dest = val16;
387 val32 = (timers->reg[0].base << 24) | (timers->reg[1].base << 16)
388 | (timers->reg[2].base << 8) | timers->reg[3].base;
389 *(unsigned32*)dest = val32;
391 else if ( timer_nr == 4 )
393 val32 = (timers->reg[4].base << 16) | timers->reg[5].base;
394 *(unsigned32*)dest = val32;
398 hw_abort (me, "bad read size of 4 bytes to TM%dBR.", timer_nr);
403 hw_abort (me, "bad read size must of %d bytes to TM%dBR.",
410 read_counter (struct hw *me,
411 struct mn103tim *timers,
418 if ( NULL == timers->timer[timer_nr].event )
420 /* Timer is not counting, use value in base register. */
423 val = 0; /* timer 6 is an up counter */
427 val = timers->reg[timer_nr].base;
432 if ( timer_nr == 6 ) /* timer 6 is an up counter. */
434 val = hw_event_queue_time(me) - timers->timer[timer_nr].start;
438 /* ticks left = start time + div ratio - curr time */
439 /* Cannot use base register because it can be written during counting and it
440 doesn't affect counter until underflow occurs. */
442 val = timers->timer[timer_nr].start + timers->timer[timer_nr].div_ratio
443 - hw_event_queue_time(me);
449 *(unsigned8 *)dest = val;
453 *(unsigned16 *)dest = val;
457 *(unsigned32 *)dest = val;
461 hw_abort(me, "bad read size for reading counter");
468 read_special_timer6_reg (struct hw *me,
469 struct mn103tim *timers,
479 switch ( timer_nr ) {
481 *(unsigned8 *)dest = timers->tm6mda;
485 *(unsigned8 *)dest = timers->tm6mdb;
489 *(unsigned8 *)dest = timers->tm6ca;
493 *(unsigned8 *)dest = timers->tm6cb;
503 if ( timer_nr == TM6CA )
505 *(unsigned16 *)dest = timers->tm6ca;
507 else if ( timer_nr == TM6CB )
509 *(unsigned16 *)dest = timers->tm6cb;
513 hw_abort(me, "bad read size for timer 6 mode A/B register");
518 hw_abort(me, "bad read size for timer 6 register");
525 mn103tim_io_read_buffer (struct hw *me,
531 struct mn103tim *timers = hw_data (me);
532 enum timer_register_types timer_reg;
534 HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
536 timer_reg = decode_addr (me, timers, base);
538 /* It can be either a mode register, a base register, a binary counter, */
539 /* or a special timer 6 register. Check in that order. */
540 if ( timer_reg >= FIRST_MODE_REG && timer_reg <= LAST_MODE_REG )
542 read_mode_reg(me, timers, timer_reg-FIRST_MODE_REG, dest, nr_bytes);
544 else if ( timer_reg <= LAST_BASE_REG )
546 read_base_reg(me, timers, timer_reg-FIRST_BASE_REG, dest, nr_bytes);
548 else if ( timer_reg <= LAST_COUNTER )
550 read_counter(me, timers, timer_reg-FIRST_COUNTER, dest, nr_bytes);
552 else if ( timer_reg <= LAST_TIMER_REG )
554 read_special_timer6_reg(me, timers, timer_reg, dest, nr_bytes);
558 hw_abort(me, "invalid timer register address.");
566 do_counter_event (struct hw *me,
569 struct mn103tim *timers = hw_data(me);
570 long timer_nr = (long) data;
573 /* Check if counting is still enabled. */
574 if ( (timers->reg[timer_nr].mode & count_mask) != 0 )
576 /* Generate an interrupt for the timer underflow (TIMERn_UFLOW). */
578 /* Port event occurs on port of last cascaded timer. */
579 /* This works across timer range from 0 to NR_REG_TIMERS because */
580 /* the first 16 bit timer (timer 4) is not allowed to be set as */
581 /* a cascading timer. */
582 for ( next_timer = timer_nr+1; next_timer < NR_REG_TIMERS; ++next_timer )
584 if ( (timers->reg[next_timer].mode & clock_mask) != clk_cascaded )
589 hw_port_event (me, next_timer-1, 1);
591 /* Schedule next timeout. */
592 timers->timer[timer_nr].start = hw_event_queue_time(me);
593 /* FIX: Check if div_ratio has changed and if it's now 0. */
594 timers->timer[timer_nr].event
595 = hw_event_queue_schedule (me, timers->timer[timer_nr].div_ratio,
596 do_counter_event, (void *)timer_nr);
600 timers->timer[timer_nr].event = NULL;
607 do_counter6_event (struct hw *me,
610 struct mn103tim *timers = hw_data(me);
611 long timer_nr = (long) data;
614 /* Check if counting is still enabled. */
615 if ( (timers->reg[timer_nr].mode & count_mask) != 0 )
617 /* Generate an interrupt for the timer underflow (TIMERn_UFLOW). */
618 hw_port_event (me, timer_nr, 1);
620 /* Schedule next timeout. */
621 timers->timer[timer_nr].start = hw_event_queue_time(me);
622 /* FIX: Check if div_ratio has changed and if it's now 0. */
623 timers->timer[timer_nr].event
624 = hw_event_queue_schedule (me, timers->timer[timer_nr].div_ratio,
625 do_counter6_event, (void *)timer_nr);
629 timers->timer[timer_nr].event = NULL;
635 write_base_reg (struct hw *me,
636 struct mn103tim *timers,
642 const unsigned8 *buf8 = source;
643 const unsigned16 *buf16 = source;
645 /* If TMnCNE == 0 (counting is off), writing to the base register
646 (TMnBR) causes a simultaneous write to the counter reg (TMnBC).
647 Else, the TMnBC is reloaded with the value from TMnBR when
648 underflow occurs. Since the counter register is not explicitly
649 maintained, this functionality is handled in read_counter. */
651 /* Check nr_bytes: write of 1, 2 or 4 bytes allowed depending on timer. */
655 /* Storing 1 byte is ok for all registers. */
656 timers->reg[timer_nr].base = buf8[0];
660 if ( timer_nr == 1 || timer_nr == 3 )
662 hw_abort (me, "bad write size of 2 bytes to TM%dBR.", timer_nr);
666 if ( timer_nr < NR_8BIT_TIMERS )
668 timers->reg[timer_nr].base = buf8[0];
669 timers->reg[timer_nr+1].base = buf8[1];
673 timers->reg[timer_nr].base = buf16[0];
681 timers->reg[0].base = buf8[0];
682 timers->reg[1].base = buf8[1];
683 timers->reg[2].base = buf8[2];
684 timers->reg[3].base = buf8[3];
686 else if ( timer_nr == 4 )
688 timers->reg[4].base = buf16[0];
689 timers->reg[5].base = buf16[1];
693 hw_abort (me, "bad write size of 4 bytes to TM%dBR.", timer_nr);
698 hw_abort (me, "bad write size must of %d bytes to TM%dBR.",
705 write_mode_reg (struct hw *me,
706 struct mn103tim *timers,
710 /* for timers 0 to 5 */
713 unsigned8 mode_val, next_mode_val;
714 unsigned32 div_ratio;
718 hw_abort (me, "bad write size of %d bytes to TM%ldMD.", nr_bytes,
722 mode_val = *(unsigned8 *)source;
723 timers->reg[timer_nr].mode = mode_val;
725 if ( ( mode_val & count_and_load_mask ) == count_and_load_mask )
727 hw_abort(me, "Cannot load base reg and start counting simultaneously.");
729 if ( ( mode_val & bits2to5_mask ) != 0 )
731 hw_abort(me, "Cannot write to bits 2 to 5 of mode register");
734 if ( mode_val & count_mask )
736 /* - de-schedule any previous event. */
737 /* - add new event to queue to start counting. */
738 /* - assert that counter == base reg? */
740 /* For cascaded timers, */
741 if ( (mode_val & clock_mask) == clk_cascaded )
743 if ( timer_nr == 0 || timer_nr == 4 )
745 hw_abort(me, "Timer %ld cannot be cascaded.", timer_nr);
750 div_ratio = timers->reg[timer_nr].base;
752 /* Check for cascading. */
753 if ( timer_nr < NR_8BIT_TIMERS )
755 for ( i = timer_nr + 1; i <= 3; ++i )
757 next_mode_val = timers->reg[i].mode;
758 if ( ( next_mode_val & clock_mask ) == clk_cascaded )
760 /* Check that CNE is on. */
761 if ( ( next_mode_val & count_mask ) == 0 )
763 hw_abort (me, "cascaded timer not ready for counting");
765 ASSERT(timers->timer[i].event == NULL);
766 ASSERT(timers->timer[i].div_ratio == 0);
767 div_ratio = div_ratio
768 | (timers->reg[i].base << (8*(i-timer_nr)));
778 /* Mode register for a 16 bit timer */
779 next_mode_val = timers->reg[timer_nr+1].mode;
780 if ( ( next_mode_val & clock_mask ) == clk_cascaded )
782 /* Check that CNE is on. */
783 if ( ( next_mode_val & count_mask ) == 0 )
785 hw_abort (me, "cascaded timer not ready for counting");
787 ASSERT(timers->timer[timer_nr+1].event == NULL);
788 ASSERT(timers->timer[timer_nr+1].div_ratio == 0);
789 div_ratio = div_ratio | (timers->reg[timer_nr+1].base << 16);
793 timers->timer[timer_nr].div_ratio = div_ratio;
795 if ( NULL != timers->timer[timer_nr].event )
797 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
798 timers->timer[timer_nr].event = NULL;
803 /* Set start time. */
804 timers->timer[timer_nr].start = hw_event_queue_time(me);
805 timers->timer[timer_nr].event
806 = hw_event_queue_schedule(me, div_ratio,
814 /* Turn off counting */
815 if ( NULL != timers->timer[timer_nr].event )
817 ASSERT((timers->reg[timer_nr].mode & clock_mask) != clk_cascaded);
818 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
819 timers->timer[timer_nr].event = NULL;
823 if ( (timers->reg[timer_nr].mode & clock_mask) == clk_cascaded )
825 ASSERT(timers->timer[timer_nr].event == NULL);
834 write_tm6md (struct hw *me,
835 struct mn103tim *timers,
836 unsigned_word address,
840 unsigned8 mode_val0 = 0x00, mode_val1 = 0x00;
841 unsigned32 div_ratio;
844 unsigned_word offset = address - timers->block[0].base;
846 if ((offset != 0x84 && nr_bytes > 1) || nr_bytes > 2 )
848 hw_abort (me, "Bad write size of %d bytes to TM6MD", nr_bytes);
851 if ( offset == 0x84 ) /* address of TM6MD */
853 /* Fill in first byte of mode */
854 mode_val0 = *(unsigned8 *)source;
855 timers->tm6md0 = mode_val0;
857 if ( ( mode_val0 & 0x26 ) != 0 )
859 hw_abort(me, "Cannot write to bits 5, 3, and 2 of TM6MD");
863 if ( offset == 0x85 || nr_bytes == 2 )
865 /* Fill in second byte of mode */
868 mode_val1 = *(unsigned8 *)source+1;
872 mode_val1 = *(unsigned8 *)source;
875 timers->tm6md1 = mode_val1;
877 if ( ( mode_val1 & count_and_load_mask ) == count_and_load_mask )
879 hw_abort(me, "Cannot load base reg and start counting simultaneously.");
881 if ( ( mode_val1 & bits0to2_mask ) != 0 )
883 hw_abort(me, "Cannot write to bits 8 to 10 of TM6MD");
887 if ( mode_val1 & count_mask )
889 /* - de-schedule any previous event. */
890 /* - add new event to queue to start counting. */
891 /* - assert that counter == base reg? */
893 div_ratio = timers->tm6ca; /* binary counter for timer 6 */
894 timers->timer[timer_nr].div_ratio = div_ratio;
895 if ( NULL != timers->timer[timer_nr].event )
897 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
898 timers->timer[timer_nr].event = NULL;
903 /* Set start time. */
904 timers->timer[timer_nr].start = hw_event_queue_time(me);
905 timers->timer[timer_nr].event
906 = hw_event_queue_schedule(me, div_ratio,
913 /* Turn off counting */
914 if ( NULL != timers->timer[timer_nr].event )
916 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
917 timers->timer[timer_nr].event = NULL;
925 write_special_timer6_reg (struct hw *me,
926 struct mn103tim *timers,
936 switch ( timer_nr ) {
938 timers->tm6mda = *(unsigned8 *)source;
942 timers->tm6mdb = *(unsigned8 *)source;
946 timers->tm6ca = *(unsigned8 *)source;
950 timers->tm6cb = *(unsigned8 *)source;
960 if ( timer_nr == TM6CA )
962 timers->tm6ca = *(unsigned16 *)source;
964 else if ( timer_nr == TM6CB )
966 timers->tm6cb = *(unsigned16 *)source;
970 hw_abort(me, "bad read size for timer 6 mode A/B register");
975 hw_abort(me, "bad read size for timer 6 register");
982 mn103tim_io_write_buffer (struct hw *me,
988 struct mn103tim *timers = hw_data (me);
989 enum timer_register_types timer_reg;
991 HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,
992 (int) nr_bytes, *(unsigned32 *)source));
994 timer_reg = decode_addr (me, timers, base);
996 /* It can be either a mode register, a base register, a binary counter, */
997 /* or a special timer 6 register. Check in that order. */
998 if ( timer_reg <= LAST_MODE_REG )
1000 if ( timer_reg == 6 )
1002 write_tm6md(me, timers, base, source, nr_bytes);
1006 write_mode_reg(me, timers, timer_reg-FIRST_MODE_REG,
1010 else if ( timer_reg <= LAST_BASE_REG )
1012 write_base_reg(me, timers, timer_reg-FIRST_BASE_REG, source, nr_bytes);
1014 else if ( timer_reg <= LAST_COUNTER )
1016 hw_abort(me, "cannot write to counter");
1018 else if ( timer_reg <= LAST_TIMER_REG )
1020 write_special_timer6_reg(me, timers, timer_reg, source, nr_bytes);
1024 hw_abort(me, "invalid reg type");
1031 const struct hw_descriptor dv_mn103tim_descriptor[] = {
1032 { "mn103tim", mn103tim_finish, },