1 /* This file is part of the program GDB, the GNU debugger.
3 Copyright (C) 1998 Free Software Foundation, Inc.
4 Contributed by Cygnus Solutions.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 mn103int - mn103002 interrupt controller
35 Implements the mn103002 interrupt controller described in the
42 reg = <icr-adr> <icr-siz> <iagr-adr> <iadr-siz> <extmd-adr> <extmd-siz>
44 Specify the address of the ICR (total of 25 registers), IAGR and
45 EXTMD registers (within the parent bus).
47 The reg property value `0x34000100 0x7C 0x34000200 0x8 0x3400280
48 0x8' locates the interrupt controller at the addresses specified in
49 the mn103002 interrupt controller user guide.
57 Non-maskable interrupt output port. An event on this output ports
58 indicates a NMI request from the interrupt controller. The value
59 attached to the event should be ignored.
64 Maskable interrupt level output port. An event on this output port
65 indicates a maskable interrupt request at the specified level. The
66 event value defines the level being requested.
68 The interrupt controller will generate an event on this port
69 whenever there is a change to the internal state of the interrupt
75 Signal from processor indicating that a maskable interrupt has been
76 accepted and the interrupt controller should latch the IAGR with
77 value of the current highest priority interrupting group.
79 The event value is the interrupt level being accepted by the
80 processor. It should be consistent with the most recent LEVEL sent
81 to the processor from the interrupt controller.
86 Level or edge triggered interrupt input port. Each of the 30
87 groups (0..30) can have up to 4 (0..3) interrupt inputs. The
88 interpretation of a port event/value is determined by the
89 configuration of the corresponding interrupt group.
91 For convenience, numerous aliases to these interrupt inputs are
98 For edge triggered interrupts, the interrupt controller does not
99 differentiate between POSITIVE (rising) and NEGATIVE (falling)
100 edges. Instead any input port event is considered to be an
103 For level sensitive interrupts, the interrupt controller ignores
104 active HIGH/LOW settings and instead always interprets a nonzero
105 port value as an interrupt assertion and a zero port value as a
111 /* The interrupt groups - numbered according to mn103002 convention */
113 enum mn103int_trigger {
125 struct mn103int_group {
131 enum mn103int_trigger trigger;
132 enum mn103int_type type;
138 FIRST_LEVEL_GROUP = 2,
139 LAST_LEVEL_GROUP = 30,
147 /* The interrupt controller register address blocks */
149 struct mn103int_block {
154 enum { ICR_BLOCK, IAGR_BLOCK, EXTMD_BLOCK, NR_BLOCKS };
158 struct mn103int_block block[NR_BLOCKS];
159 struct mn103int_group group[NR_GROUPS];
160 unsigned interrupt_accepted_group;
165 /* output port ID's */
173 /* input port ID's */
211 static const struct hw_port_descriptor mn103int_ports[] = {
213 /* interrupt outputs */
215 { "nmi", NMI_PORT, 0, output_port, },
216 { "level", LEVEL_PORT, 0, output_port, },
218 /* interrupt ack (latch) input from cpu */
220 { "ack", ACK_PORT, 0, input_port, },
222 /* interrupt inputs (as names) */
224 { "nmirq", G0_PORT + 0, 0, input_port, },
225 { "watchdog", G0_PORT + 1, 0, input_port, },
226 { "syserr", G0_PORT + 2, 0, input_port, },
228 { "timer-0-underflow", G2_PORT, 0, input_port, },
229 { "timer-1-underflow", G3_PORT, 0, input_port, },
230 { "timer-2-underflow", G4_PORT, 0, input_port, },
231 { "timer-3-underflow", G5_PORT, 0, input_port, },
232 { "timer-4-underflow", G6_PORT, 0, input_port, },
233 { "timer-5-underflow", G7_PORT, 0, input_port, },
234 { "timer-6-underflow", G8_PORT, 0, input_port, },
236 { "timer-6-compare-a", G9_PORT, 0, input_port, },
237 { "timer-6-compare-b", G10_PORT, 0, input_port, },
239 { "dma-0-end", G12_PORT, 0, input_port, },
240 { "dma-1-end", G13_PORT, 0, input_port, },
241 { "dma-2-end", G14_PORT, 0, input_port, },
242 { "dma-3-end", G15_PORT, 0, input_port, },
244 { "serial-0-receive", G16_PORT, 0, input_port, },
245 { "serial-0-transmit", G17_PORT, 0, input_port, },
247 { "serial-1-receive", G18_PORT, 0, input_port, },
248 { "serial-1-transmit", G19_PORT, 0, input_port, },
250 { "serial-2-receive", G20_PORT, 0, input_port, },
251 { "serial-2-transmit", G21_PORT, 0, input_port, },
253 { "irq-0", G23_PORT, 0, input_port, },
254 { "irq-1", G24_PORT, 0, input_port, },
255 { "irq-2", G25_PORT, 0, input_port, },
256 { "irq-3", G26_PORT, 0, input_port, },
257 { "irq-4", G27_PORT, 0, input_port, },
258 { "irq-5", G28_PORT, 0, input_port, },
259 { "irq-6", G29_PORT, 0, input_port, },
260 { "irq-7", G30_PORT, 0, input_port, },
262 /* interrupt inputs (as generic numbers) */
264 { "int", 0, NR_G_PORTS, input_port, },
270 /* Macros for extracting/restoring the various register bits */
272 #define EXTRACT_ID(X) (LSEXTRACTED8 ((X), 3, 0))
273 #define INSERT_ID(X) (LSINSERTED8 ((X), 3, 0))
275 #define EXTRACT_IR(X) (LSEXTRACTED8 ((X), 7, 4))
276 #define INSERT_IR(X) (LSINSERTED8 ((X), 7, 4))
278 #define EXTRACT_IE(X) (LSEXTRACTED8 ((X), 3, 0))
279 #define INSERT_IE(X) (LSINSERTED8 ((X), 3, 0))
281 #define EXTRACT_LV(X) (LSEXTRACTED8 ((X), 6, 4))
282 #define INSERT_LV(X) (LSINSERTED8 ((X), 6, 4))
286 /* Finish off the partially created hw device. Attach our local
287 callbacks. Wire up our port names etc */
289 static hw_io_read_buffer_method mn103int_io_read_buffer;
290 static hw_io_write_buffer_method mn103int_io_write_buffer;
291 static hw_port_event_method mn103int_port_event;
294 attach_mn103int_regs (struct hw *me,
295 struct mn103int *controller)
298 if (hw_find_property (me, "reg") == NULL)
299 hw_abort (me, "Missing \"reg\" property");
300 for (i = 0; i < NR_BLOCKS; i++)
302 unsigned_word attach_address;
304 unsigned attach_size;
305 reg_property_spec reg;
306 if (!hw_find_reg_array_property (me, "reg", i, ®))
307 hw_abort (me, "\"reg\" property must contain three addr/size entries");
308 hw_unit_address_to_attach_address (hw_parent (me),
313 controller->block[i].base = attach_address;
314 hw_unit_size_to_attach_size (hw_parent (me),
317 controller->block[i].bound = attach_address + (attach_size - 1);
318 hw_attach_address (hw_parent (me),
320 attach_space, attach_address, attach_size,
326 mn103int_finish (struct hw *me)
329 struct mn103int *controller;
331 controller = HW_ZALLOC (me, struct mn103int);
332 set_hw_data (me, controller);
333 set_hw_io_read_buffer (me, mn103int_io_read_buffer);
334 set_hw_io_write_buffer (me, mn103int_io_write_buffer);
335 set_hw_ports (me, mn103int_ports);
336 set_hw_port_event (me, mn103int_port_event);
338 /* Attach ourself to our parent bus */
339 attach_mn103int_regs (me, controller);
341 /* Initialize all the groups according to their default configuration */
342 for (gid = 0; gid < NR_GROUPS; gid++)
344 struct mn103int_group *group = &controller->group[gid];
346 group->trigger = NEGATIVE_EDGE;
348 if (FIRST_NMI_GROUP <= gid && gid <= LAST_NMI_GROUP)
350 group->type = NMI_GROUP;
352 else if (FIRST_LEVEL_GROUP <= gid && gid <= LAST_LEVEL_GROUP)
354 group->type = LEVEL_GROUP;
357 hw_abort (me, "internal error - unknown group id");
363 /* Perform the nasty work of figuring out which of the interrupt
364 groups should have its interrupt delivered. */
367 find_highest_interrupt_group (struct hw *me,
368 struct mn103int *controller)
373 /* FIRST_NMI_GROUP (group zero) is used as a special default value
374 when searching for an interrupt group.*/
375 selected = FIRST_NMI_GROUP;
376 controller->group[FIRST_NMI_GROUP].level = 7;
378 for (gid = FIRST_LEVEL_GROUP; gid <= LAST_LEVEL_GROUP; gid++)
380 struct mn103int_group *group = &controller->group[gid];
381 if ((group->request & group->enable) != 0)
383 /* Remember, lower level, higher priority. */
384 if (group->level < controller->group[selected].level)
394 /* Notify the processor of an interrupt level update */
397 push_interrupt_level (struct hw *me,
398 struct mn103int *controller)
400 int selected = find_highest_interrupt_group (me, controller);
401 int level = controller->group[selected].level;
402 HW_TRACE ((me, "port-out - selected=%d level=%d", selected, level));
403 hw_port_event (me, LEVEL_PORT, level);
407 /* An event arrives on an interrupt port */
410 mn103int_port_event (struct hw *me,
416 struct mn103int *controller = hw_data (me);
423 int selected = find_highest_interrupt_group (me, controller);
424 if (controller->group[selected].level != level)
425 hw_abort (me, "botched level synchronisation");
426 controller->interrupt_accepted_group = selected;
427 HW_TRACE ((me, "port-event port=ack level=%d - selected=%d",
436 struct mn103int_group *group;
438 if (my_port > NR_G_PORTS)
439 hw_abort (me, "Event on unknown port %d", my_port);
441 /* map the port onto an interrupt group */
442 gid = (my_port % NR_G_PORTS) / 4;
443 group = &controller->group[gid];
445 interrupt = 1 << iid;
447 /* update our cached input */
449 group->input |= interrupt;
451 group->input &= ~interrupt;
453 /* update the request bits */
454 switch (group->trigger)
459 group->request |= interrupt;
463 group->request |= interrupt;
466 /* force a corresponding output */
472 /* for NMI's the event is the trigger */
473 HW_TRACE ((me, "port-in port=%d group=%d interrupt=%d - NMI",
475 if ((group->request & group->enable) != 0)
477 HW_TRACE ((me, "port-out NMI"));
478 hw_port_event (me, NMI_PORT, 1);
485 /* if an interrupt is now pending */
486 HW_TRACE ((me, "port-in port=%d group=%d interrupt=%d - INT",
488 push_interrupt_level (me, controller);
498 /* Read/write to to an ICR (group control register) */
500 static struct mn103int_group *
501 decode_group (struct hw *me,
502 struct mn103int *controller,
504 unsigned_word *offset)
506 int gid = (base / 4) % NR_GROUPS;
507 *offset = (base % 4);
508 return &controller->group[gid];
512 read_icr (struct hw *me,
513 struct mn103int *controller,
516 unsigned_word offset;
517 struct mn103int_group *group = decode_group (me, controller, base, &offset);
526 val = INSERT_ID (group->request);
527 HW_TRACE ((me, "read-icr group=%d:0 nmi 0x%02x",
539 val = (INSERT_IR (group->request)
540 | INSERT_ID (group->request & group->enable));
541 HW_TRACE ((me, "read-icr group=%d:0 level 0x%02x",
545 val = (INSERT_LV (group->level)
546 | INSERT_IE (group->enable));
547 HW_TRACE ((me, "read-icr level-%d:1 level 0x%02x",
562 write_icr (struct hw *me,
563 struct mn103int *controller,
567 unsigned_word offset;
568 struct mn103int_group *group = decode_group (me, controller, base, &offset);
576 HW_TRACE ((me, "write-icr group=%d:0 nmi 0x%02x",
578 group->request &= ~EXTRACT_ID (val);
588 case 0: /* request/detect */
589 /* Clear any ID bits and then set them according to IR */
590 HW_TRACE ((me, "write-icr group=%d:0 level 0x%02x %x:%x:%x",
592 group->request, EXTRACT_IR (val), EXTRACT_ID (val)));
594 ((EXTRACT_IR (val) & EXTRACT_ID (val))
595 | (EXTRACT_IR (val) & group->request)
596 | (~EXTRACT_IR (val) & ~EXTRACT_ID (val) & group->request));
598 case 1: /* level/enable */
599 HW_TRACE ((me, "write-icr group=%d:1 level 0x%02x",
601 group->level = EXTRACT_LV (val);
602 group->enable = EXTRACT_IE (val);
608 push_interrupt_level (me, controller);
618 /* Read the IAGR (Interrupt accepted group register) */
621 read_iagr (struct hw *me,
622 struct mn103int *controller,
623 unsigned_word offset)
630 if (!(controller->group[controller->interrupt_accepted_group].request
631 & controller->group[controller->interrupt_accepted_group].enable))
633 /* oops, lost the request */
635 HW_TRACE ((me, "read-iagr:0 lost-0"));
639 val = (controller->interrupt_accepted_group << 2);
640 HW_TRACE ((me, "read-iagr:0 %d", (int) val));
646 HW_TRACE ((me, "read-iagr:1 %d", (int) val));
650 HW_TRACE ((me, "read-iagr 0x%08lx bad offset", (long) offset));
657 /* Reads/writes to the EXTMD (external interrupt trigger configuration
660 static struct mn103int_group *
661 external_group (struct mn103int *controller,
662 unsigned_word offset)
667 return &controller->group[16];
669 return &controller->group[20];
676 read_extmd (struct hw *me,
677 struct mn103int *controller,
678 unsigned_word offset)
682 struct mn103int_group *group = external_group (controller, offset);
685 for (gid = 0; gid < 4; gid++)
687 val |= (group[gid].trigger << (gid * 2));
690 HW_TRACE ((me, "read-extmd 0x%02lx", (long) val));
695 write_extmd (struct hw *me,
696 struct mn103int *controller,
697 unsigned_word offset,
701 struct mn103int_group *group = external_group (controller, offset);
704 for (gid = 0; gid < 4; gid++)
706 group[gid].trigger = (val >> (gid * 2)) & 0x3;
707 /* MAYBE: interrupts already pending? */
710 HW_TRACE ((me, "write-extmd 0x%02lx", (long) val));
714 /* generic read/write */
717 decode_addr (struct hw *me,
718 struct mn103int *controller,
719 unsigned_word address,
720 unsigned_word *offset)
723 for (i = 0; i < NR_BLOCKS; i++)
725 if (address >= controller->block[i].base
726 && address <= controller->block[i].bound)
728 *offset = address - controller->block[i].base;
732 hw_abort (me, "bad address");
737 mn103int_io_read_buffer (struct hw *me,
743 struct mn103int *controller = hw_data (me);
744 unsigned8 *buf = dest;
746 /* HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); */
747 for (byte = 0; byte < nr_bytes; byte++)
749 unsigned_word address = base + byte;
750 unsigned_word offset;
751 switch (decode_addr (me, controller, address, &offset))
754 buf[byte] = read_icr (me, controller, offset);
757 buf[byte] = read_iagr (me, controller, offset);
760 buf[byte] = read_extmd (me, controller, offset);
763 hw_abort (me, "bad switch");
770 mn103int_io_write_buffer (struct hw *me,
776 struct mn103int *controller = hw_data (me);
777 const unsigned8 *buf = source;
779 /* HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); */
780 for (byte = 0; byte < nr_bytes; byte++)
782 unsigned_word address = base + byte;
783 unsigned_word offset;
784 switch (decode_addr (me, controller, address, &offset))
787 write_icr (me, controller, offset, buf[byte]);
793 write_extmd (me, controller, offset, buf[byte]);
796 hw_abort (me, "bad switch");
803 const struct hw_descriptor dv_mn103int_descriptor[] = {
804 { "mn103int", mn103int_finish, },