1 /* MIPS Simulator definition.
2 Copyright (C) 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* This simulator doesn't cache the Current Instruction Address */
25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
28 #define SIM_HAVE_BIENDIAN
31 /* hobble some common features for moment */
32 #define WITH_WATCHPOINTS 1
33 #define WITH_MODULO_MEMORY 1
35 #include "sim-basics.h"
37 typedef address_word sim_cia;
40 /* Get the number of instructions. FIXME: must be a more elegant way
43 #define MAX_INSNS (nr_itable_entries)
44 #define INSN_NAME(cpu,i) itable[(i)].name
50 /* Depreciated macros and types for manipulating 64bit values. Use
51 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
53 typedef signed64 word64;
54 typedef unsigned64 uword64;
56 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
57 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
58 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
59 #define SET64HI(t) (((uword64)(t))<<32)
60 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
61 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
63 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
64 assume the HI32bits of the operand are zero, so we must perform a
65 mask to ensure we can use the simple subtraction to sign-extend. */
66 #define SIGNEXTEND(e,b) \
68 (((e) & ((uword64) 1 << ((b) - 1))) \
69 ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
70 : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
72 /* Check if a value will fit within a halfword: */
73 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
77 /* Floating-point operations: */
81 /* FPU registers must be one of the following types. All other values
82 are reserved (and undefined). */
88 /* The following are well outside the normal acceptable format
89 range, and are used in the register status vector. */
90 fmt_unknown = 0x10000000,
91 fmt_uninterpreted = 0x20000000,
92 fmt_uninterpreted_32 = 0x40000000,
93 fmt_uninterpreted_64 = 0x80000000,
96 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
97 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
99 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
100 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
102 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
103 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
104 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
105 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
106 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
107 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
108 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
109 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
110 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
111 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
112 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
113 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
114 unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
115 unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
116 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
117 #define Convert(rm,op,from,to) \
118 convert (SD, CPU, cia, rm, op, from, to)
120 /* Macro to update FPSR condition-code field. This is complicated by
121 the fact that there is a hole in the index range of the bits within
122 the FCSR register. Also, the number of bits visible depends on the
123 MIPS ISA version being supported. */
125 #define SETFCC(cc,v) {\
126 int bit = ((cc == 0) ? 23 : (24 + (cc)));\
127 FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
129 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
131 /* This should be the COC1 value at the start of the preceding
133 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
136 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
138 /* They depend on the CPU being simulated */
139 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
142 /* Standard FCRS bits: */
143 #define IR (0) /* Inexact Result */
144 #define UF (1) /* UnderFlow */
145 #define OF (2) /* OverFlow */
146 #define DZ (3) /* Division by Zero */
147 #define IO (4) /* Invalid Operation */
148 #define UO (5) /* Unimplemented Operation */
150 /* Get masks for individual flags: */
151 #if 1 /* SAFE version */
152 #define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
153 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
154 #define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
156 #define FP_FLAGS(b) (1 << ((b) + 2))
157 #define FP_ENABLE(b) (1 << ((b) + 7))
158 #define FP_CAUSE(b) (1 << ((b) + 12))
161 #define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
163 #define FP_MASK_RM (0x3)
165 #define FP_RM_NEAREST (0) /* Round to nearest (Round) */
166 #define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
167 #define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
168 #define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
169 #define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
171 /* start-sanitize-sky */
178 /* end-sanitize-sky */
184 /* HI/LO register accesses */
186 /* For some MIPS targets, the HI/LO registers have certain timing
187 restrictions in that, for instance, a read of a HI register must be
188 separated by at least three instructions from a preceeding read.
190 The struct below is used to record the last access by each of A MT,
191 MF or other OP instruction to a HI/LO register. See mips.igen for
194 typedef struct _hilo_access {
199 typedef struct _hilo_history {
208 /* Integer ALU operations: */
212 #define ALU32_END(ANS) \
213 if (ALU32_HAD_OVERFLOW) \
214 SignalExceptionIntegerOverflow (); \
215 (ANS) = (signed32) ALU32_OVERFLOW_RESULT
218 #define ALU64_END(ANS) \
219 if (ALU64_HAD_OVERFLOW) \
220 SignalExceptionIntegerOverflow (); \
221 (ANS) = ALU64_OVERFLOW_RESULT;
224 /* start-sanitize-r5900 */
226 /* Figure 10-5 FPU Control/Status Register.
227 Note: some of these bits are different to what is found in a
228 standard MIPS manual. */
230 R5900_FCSR_C = BIT (23), /* OK */
231 R5900_FCSR_I = BIT (17),
232 R5900_FCSR_D = BIT (16),
233 R5900_FCSR_O = BIT (15),
234 R5900_FCSR_U = BIT (14),
235 R5900_FCSR_CAUSE = MASK (16,14),
236 R5900_FCSR_SI = BIT (6),
237 R5900_FCSR_SD = BIT (5),
238 R5900_FCSR_SO = BIT (4),
239 R5900_FCSR_SU = BIT (3),
242 /* Table 10-1 FP format values.
243 Note: some of these bits are different to what is found in a
244 standard MIPS manual. */
251 /* MAX and MIN FP values */
253 R5900_FPMAX = LSMASK32 (30, 0),
254 R5900_FPMIN = LSMASK32 (31, 0),
259 typedef struct _sim_r5900_cpu {
261 /* The R5900 has 32 x 128bit general purpose registers.
262 Fortunatly, the high 64 bits are only touched by multimedia (MMI)
263 instructions. The normal mips instructions just use the lower 64
264 bits. To avoid changing the older parts of the simulator to
265 handle this weirdness, the high 64 bits of each register are kept
266 in a separate array (registers1). The high 64 bits of any
267 register are by convention refered by adding a '1' to the end of
268 the normal register's name. So LO still refers to the low 64
269 bits of the LO register, LO1 refers to the high 64 bits of that
271 signed_word gpr1[32];
272 #define GPR1 ((CPU)->r5900.gpr1)
275 #define LO1 ((CPU)->r5900.lo1)
276 #define HI1 ((CPU)->r5900.hi1)
278 /* The R5900 defines a shift amount register, that controls the
279 amount of certain shift instructions */
280 unsigned_word sa; /* the shift amount register */
281 #define REGISTER_SA (124) /* GET RID IF THIS! */
282 #define SA ((CPU)->r5900.sa)
284 /* The R5900, in addition to the (almost) standard floating point
285 registers, defines a 32 bit accumulator. This is used in
286 multiply/accumulate style instructions */
287 fp_word acc; /* floating-point accumulator */
288 #define ACC ((CPU)->r5900.acc)
290 /* See comments below about needing to count cycles between updating
291 and setting HI/LO registers */
292 hilo_history hi1_history;
293 #define HI1HISTORY (&(CPU)->r5900.hi1_history)
294 hilo_history lo1_history;
295 #define LO1HISTORY (&(CPU)->r5900.lo1_history)
299 #define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
300 #define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
301 #define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
302 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
304 #define BYTES_IN_MIPS_REGS (sizeof(signed_word))
305 #define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
306 #define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
307 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
309 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
310 T - type of the sub part
311 TC - # of T's in the mips part of the "register"
312 I - index (from 0) of desired sub part
313 A - low part of "register"
314 A1 - high part of register
316 #define SUB_REG_FETCH(T,TC,A,A1,I) \
317 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
318 + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
319 ? ((TC) - 1 - (I) % (TC)) \
326 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
327 where <type> has two letters:
328 1 is S=signed or U=unsigned
329 2 is B=byte H=halfword W=word D=doubleword
332 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
333 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
334 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
335 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
337 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
338 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
339 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
340 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
342 #define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
343 #define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
344 #define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
345 #define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
347 #define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
348 #define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
349 #define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
350 #define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
353 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
354 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
355 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
356 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
358 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
359 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
360 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
361 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
363 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
364 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
365 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
366 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
368 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
369 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
370 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
371 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
375 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
376 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
377 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
378 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
380 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
381 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
382 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
383 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
385 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
386 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
387 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
388 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
390 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
391 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
392 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
393 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
395 /* end-sanitize-r5900 */
399 /* The following is probably not used for MIPS IV onwards: */
400 /* Slots for delayed register updates. For the moment we just have a
401 fixed number of slots (rather than a more generic, dynamic
402 system). This keeps the simulator fast. However, we only allow
403 for the register update to be delayed for a single instruction
405 #define PSLOTS (8) /* Maximum number of instruction cycles */
407 typedef struct _pending_write_queue {
411 int slot_delay[PSLOTS];
412 int slot_size[PSLOTS];
413 int slot_bit[PSLOTS];
414 void *slot_dest[PSLOTS];
415 unsigned64 slot_value[PSLOTS];
416 } pending_write_queue;
418 #ifndef PENDING_TRACE
419 #define PENDING_TRACE 0
421 #define PENDING_IN ((CPU)->pending.in)
422 #define PENDING_OUT ((CPU)->pending.out)
423 #define PENDING_TOTAL ((CPU)->pending.total)
424 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
425 #define PENDING_SLOT_BIT ((CPU)->pending.slot_size)
426 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
427 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
428 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
430 /* Invalidate the pending write queue, all pending writes are
433 #define PENDING_INVALIDATE() \
434 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
436 /* Schedule a write to DEST for N cycles time. For 64 bit
437 destinations, schedule two writes. For floating point registers,
438 the caller should schedule a write to both the dest register and
439 the FPR_STATE register. When BIT is non-negative, only BIT of DEST
442 #define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
444 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
445 sim_engine_abort (SD, CPU, cia, \
446 "PENDING_SCHED - buffer overflow\n"); \
448 sim_io_printf (SD, "PENDING_SCHED - dest 0x%lx, val 0x%lx, pending_in %d, pending_out %d, pending_total %d\n", (unsigned long) (DEST), (unsigned long) (VAL), PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
449 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
450 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
451 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
452 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
453 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
456 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
457 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
459 #define PENDING_TICK() pending_tick (SD, CPU, cia)
461 #define PENDING_FLUSH() abort () /* think about this one */
462 #define PENDING_FP() abort () /* think about this one */
464 /* For backward compatibility */
465 #define PENDING_FILL(R,VAL) \
467 if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR) \
468 PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 2, -1); \
470 PENDING_SCHED(GPR[(R)], VAL, 2, -1); \
478 /* The following are internal simulator state variables: */
479 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
480 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
481 address_word dspc; /* delay-slot PC */
482 #define DSPC ((CPU)->dspc)
485 /* Issue a delay slot instruction immediatly by re-calling
487 #define DELAY_SLOT(TARGET) \
489 address_word target = (TARGET); \
490 instruction_word delay_insn; \
491 sim_events_slip (SD, 1); \
492 CIA = CIA + 4; /* NOTE not mips16 */ \
493 STATE |= simDELAYSLOT; \
494 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ \
495 idecode_issue (CPU_, delay_insn, (CIA)); \
496 STATE &= ~simDELAYSLOT; \
499 #define NULLIFY_NEXT_INSTRUCTION() \
501 sim_events_slip (SD, 1); \
502 dotrace (SD, CPU, tracefh, 2, NIA, 4, "load instruction"); \
506 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
507 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
511 /* State of the simulator */
513 unsigned int dsstate;
514 #define STATE ((CPU)->state)
515 #define DSSTATE ((CPU)->dsstate)
517 /* Flags in the "state" variable: */
518 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
519 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
520 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
521 #define simPCOC0 (1 << 17) /* COC[1] from current */
522 #define simPCOC1 (1 << 18) /* COC[1] from previous */
523 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
524 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
525 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
526 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
528 #define ENGINE_ISSUE_PREFIX_HOOK() \
530 /* Perform any pending writes */ \
532 /* Set previous flag, depending on current: */ \
533 if (STATE & simPCOC0) \
536 STATE &= ~simPCOC1; \
537 /* and update the current value: */ \
541 STATE &= ~simPCOC0; \
545 /* This is nasty, since we have to rely on matching the register
546 numbers used by GDB. Unfortunately, depending on the MIPS target
547 GDB uses different register numbers. We cannot just include the
548 relevant "gdb/tm.h" link, since GDB may not be configured before
549 the sim world, and also the GDB header file requires too much other
553 #define LAST_EMBED_REGNUM (89)
554 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
555 /* start-sanitize-r5900 */
557 #define NUM_REGS (128)
558 /* end-sanitize-r5900 */
561 /* start-sanitize-sky */
564 /* Number of machine registers */
565 #define NUM_VU_REGS 153
566 #define NUM_VU_INTEGER_REGS 16
568 #define NUM_VIF_REGS 25
570 #define FIRST_VEC_REG 25
571 #define NUM_R5900_REGS 128
574 #define NUM_REGS (NUM_R5900_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
575 #endif /* no tm-txvu.h */
576 #endif /* TARGET_SKY */
577 /* end-sanitize-sky */
580 /* start-sanitize-sky */
581 /* NOTE: THE VALUES of THESE CONSTANTS MUST BE IN SYNC WITH THOSE IN WF.H */
582 /* end-sanitize-sky */
584 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
585 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
586 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
589 /* To keep this default simulator simple, and fast, we use a direct
590 vector of registers. The internal simulator engine then uses
591 manifests to access the correct slot. */
593 unsigned_word registers[LAST_EMBED_REGNUM + 1];
594 int register_widths[NUM_REGS];
595 #define REGISTERS ((CPU)->registers)
597 #define GPR (®ISTERS[0])
598 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
600 /* While space is allocated for the floating point registers in the
601 main registers array, they are stored separatly. This is because
602 their size may not necessarily match the size of either the
603 general-purpose or system specific registers */
607 #define FGR ((CPU)->fgr)
609 #define LO (REGISTERS[33])
610 #define HI (REGISTERS[34])
612 #define PC (REGISTERS[PCIDX])
613 #define CAUSE (REGISTERS[36])
615 #define SR (REGISTERS[SRIDX]) /* CPU status register */
617 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
618 #define FCR31IDX (70)
619 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
621 #define Debug (REGISTERS[86])
622 #define DEPC (REGISTERS[87])
623 #define EPC (REGISTERS[88])
624 #define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
626 unsigned_word c0_config_reg;
627 #define C0_CONFIG ((CPU)->c0_config_reg)
629 /* The following are pseudonyms for standard registers */
630 #define ZERO (REGISTERS[0])
631 #define V0 (REGISTERS[2])
632 #define A0 (REGISTERS[4])
633 #define A1 (REGISTERS[5])
634 #define A2 (REGISTERS[6])
635 #define A3 (REGISTERS[7])
637 #define T8 (REGISTERS[T8IDX])
639 #define SP (REGISTERS[SPIDX])
641 #define RA (REGISTERS[RAIDX])
643 /* Keep the current format state for each register: */
644 FP_formats fpr_state[32];
645 #define FPR_STATE ((CPU)->fpr_state)
647 pending_write_queue pending;
649 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
650 read-write instructions. It is set when a linked load occurs. It
651 is tested and cleared by the conditional store. It is cleared
652 (during other CPU operations) when a store to the location would
653 no longer be atomic. In particular, it is cleared by exception
654 return instructions. */
656 #define LLBIT ((CPU)->llbit)
659 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
660 corruptions caused by using the HI or LO register too close to a
661 following operation is spotted. See mips.igen for more details. */
663 hilo_history hi_history;
664 #define HIHISTORY (&(CPU)->hi_history)
665 hilo_history lo_history;
666 #define LOHISTORY (&(CPU)->lo_history)
668 /* start-sanitize-r5900 */
671 /* end-sanitize-r5900 */
672 /* start-sanitize-vr5400 */
674 /* The MDMX ISA has a very very large accumulator */
675 unsigned8 acc[3 * 8];
676 /* end-sanitize-vr5400 */
677 /* start-sanitize-sky */
680 /* Device on which instruction issue last occured. */
683 /* end-sanitize-sky */
688 /* MIPS specific simulator watch config */
690 void watch_options_install PARAMS ((SIM_DESC sd));
699 /* FIXME: At present much of the simulator is still static */
704 sim_cpu cpu[MAX_NR_PROCESSORS];
706 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
708 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
711 /* start-sanitize-sky */
714 /* Record of option for floating point implementation type. */
716 #define STATE_FP_TYPE_OPT(sd) ((sd)->fp_type_opt)
717 #define STATE_FP_TYPE_OPT_ACCURATE 0x80000000
720 /* end-sanitize-sky */
727 /* Status information: */
729 /* TODO : these should be the bitmasks for these bits within the
730 status register. At the moment the following are VR4300
732 #define status_KSU_mask (0x3) /* mask for KSU bits */
733 #define status_KSU_shift (3) /* shift for field */
734 #define ksu_kernel (0x0)
735 #define ksu_supervisor (0x1)
736 #define ksu_user (0x2)
737 #define ksu_unknown (0x3)
739 #define status_IE (1 << 0) /* Interrupt enable */
740 #define status_EXL (1 << 1) /* Exception level */
741 #define status_RE (1 << 25) /* Reverse Endian in user mode */
742 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
743 #define status_SR (1 << 20) /* soft reset or NMI */
744 #define status_BEV (1 << 22) /* Location of general exception vectors */
745 #define status_TS (1 << 21) /* TLB shutdown has occurred */
746 #define status_ERL (1 << 2) /* Error level */
747 #define status_RP (1 << 27) /* Reduced Power mode */
748 /* start-sanitize-r5900 */
749 #define status_CU0 (1 << 28) /* COP0 usable */
750 #define status_CU1 (1 << 29) /* COP1 usable */
751 #define status_CU2 (1 << 30) /* COP2 usable */
752 /* end-sanitize-r5900 */
754 /* Specializations for TX39 family */
755 #define status_IEc (1 << 0) /* Interrupt enable (current) */
756 #define status_KUc (1 << 1) /* Kernel/User mode */
757 #define status_IEp (1 << 2) /* Interrupt enable (previous) */
758 #define status_KUp (1 << 3) /* Kernel/User mode */
759 #define status_IEo (1 << 4) /* Interrupt enable (old) */
760 #define status_KUo (1 << 5) /* Kernel/User mode */
761 #define status_IM_mask (0xff) /* Interrupt mask */
762 #define status_IM_shift (8)
763 #define status_NMI (1 << 20) /* NMI */
764 #define status_NMI (1 << 20) /* NMI */
766 #define cause_EXC_mask (0x1f) /* Exception code */
767 #define cause_EXC_shift (2)
768 #define cause_SW0 (1 << 8) /* Software interrupt 0 */
769 #define cause_SW1 (1 << 9) /* Software interrupt 1 */
770 #define cause_IP_mask (0x3f) /* Interrupt pending field */
771 #define cause_IP_shift (10)
772 #define cause_CE_mask (0x3) /* Coprocessor error */
773 #define cause_CE_shift (28)
775 #define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
778 /* NOTE: We keep the following status flags as bit values (1 for true,
779 0 for false). This allows them to be used in binary boolean
780 operations without worrying about what exactly the non-zero true
784 #ifdef SUBTARGET_R3900
785 #define UserMode ((SR & status_KUc) ? 1 : 0)
787 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
788 #endif /* SUBTARGET_R3900 */
791 /* Hardware configuration. Affects endianness of LoadMemory and
792 StoreMemory and the endianness of Kernel and Supervisor mode
793 execution. The value is 0 for little-endian; 1 for big-endian. */
794 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
795 /*(state & simBE) ? 1 : 0)*/
798 /* This mode is selected if in User mode with the RE bit being set in
799 SR (Status Register). It reverses the endianness of load and store
801 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
804 /* The endianness for load and store instructions (0=little;1=big). In
805 User mode this endianness may be switched by setting the state_RE
806 bit in the SR register. Thus, BigEndianCPU may be computed as
807 (BigEndianMem EOR ReverseEndian). */
808 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
814 /* NOTE: These numbers depend on the processor architecture being
816 #define Interrupt (0)
817 #define TLBModification (1)
820 #define AddressLoad (4)
821 #define AddressStore (5)
822 #define InstructionFetch (6)
823 #define DataReference (7)
824 #define SystemCall (8)
825 #define BreakPoint (9)
826 #define ReservedInstruction (10)
827 #define CoProcessorUnusable (11)
828 #define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
831 #define DebugBreakPoint (16)
833 #define NMIReset (31)
836 /* The following exception code is actually private to the simulator
837 world. It is *NOT* a processor feature, and is used to signal
838 run-time errors in the simulator. */
839 #define SimulatorFault (0xFFFFFFFF)
841 /* The following break instructions are reserved for use by the
842 simulator. The first is used to halt the simulation. The second
843 is used by gdb for break-points. NOTE: Care must be taken, since
844 this value may be used in later revisions of the MIPS ISA. */
845 #define HALT_INSTRUCTION_MASK (0x03FFFFC0)
847 #define HALT_INSTRUCTION (0x03ff000d)
848 #define HALT_INSTRUCTION2 (0x0000ffcd)
850 /* start-sanitize-sky */
851 #define HALT_INSTRUCTION_PASS (0x03fffc0d)
852 #define HALT_INSTRUCTION_FAIL (0x03ffffcd)
853 /* end-sanitize-sky */
855 #define BREAKPOINT_INSTRUCTION (0x0005000d)
856 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
859 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
860 #define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
861 #define SignalExceptionInterrupt() signal_exception (SD, CPU, cia, Interrupt)
862 #define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
863 #define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
864 #define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
865 #define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
866 #define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
867 #define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
868 #define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
869 #define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
871 /* Co-processor accesses */
873 void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
874 void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
875 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
876 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
878 #define COP_LW(coproc_num,coproc_reg,memword) \
879 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
880 #define COP_LD(coproc_num,coproc_reg,memword) \
881 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
882 #define COP_SW(coproc_num,coproc_reg) \
883 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
884 #define COP_SD(coproc_num,coproc_reg) \
885 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
887 /* start-sanitize-sky */
889 void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
890 int coproc_num, int coproc_reg, unsigned128 memword));
891 unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
892 int coproc_num, int coproc_reg));
893 #define COP_LQ(coproc_num,coproc_reg,memword) \
894 cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
895 #define COP_SQ(coproc_num,coproc_reg) \
896 cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
897 #endif /* TARGET_SKY */
898 /* end-sanitize-sky */
900 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
901 #define DecodeCoproc(instruction) \
902 decode_coproc (SD, CPU, cia, (instruction))
906 /* Memory accesses */
908 /* The following are generic to all versions of the MIPS architecture
911 /* Memory Access Types (for CCA): */
913 #define CachedNoncoherent (1)
914 #define CachedCoherent (2)
917 #define isINSTRUCTION (1 == 0) /* FALSE */
918 #define isDATA (1 == 1) /* TRUE */
919 #define isLOAD (1 == 0) /* FALSE */
920 #define isSTORE (1 == 1) /* TRUE */
921 #define isREAL (1 == 0) /* FALSE */
922 #define isRAW (1 == 1) /* TRUE */
923 /* The parameter HOST (isTARGET / isHOST) is ignored */
924 #define isTARGET (1 == 0) /* FALSE */
925 /* #define isHOST (1 == 1) TRUE */
927 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
928 is the number of bytes minus 1. */
929 #define AccessLength_BYTE (0)
930 #define AccessLength_HALFWORD (1)
931 #define AccessLength_TRIPLEBYTE (2)
932 #define AccessLength_WORD (3)
933 #define AccessLength_QUINTIBYTE (4)
934 #define AccessLength_SEXTIBYTE (5)
935 #define AccessLength_SEPTIBYTE (6)
936 #define AccessLength_DOUBLEWORD (7)
937 #define AccessLength_QUADWORD (15)
940 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
941 ? AccessLength_DOUBLEWORD /*7*/ \
942 : AccessLength_WORD /*3*/)
943 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
947 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
948 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
949 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
951 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
952 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
953 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
955 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
956 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
957 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
959 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
960 #define CacheOp(op,pAddr,vAddr,instruction) \
961 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
963 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
964 #define SyncOperation(stype) \
965 sync_operation (SD, CPU, cia, (stype))
967 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
968 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
969 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
971 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
972 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
973 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
974 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
975 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
977 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
980 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
982 char* pr_addr PARAMS ((SIM_ADDR addr));
983 char* pr_uword64 PARAMS ((uword64 addr));
985 /* start-sanitize-sky */
987 #ifdef SIM_ENGINE_HALT_HOOK
988 #undef SIM_ENGINE_HALT_HOOK
991 void sky_sim_engine_halt PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
992 #define SIM_ENGINE_HALT_HOOK(sd, last, cia) sky_sim_engine_halt(sd, last, cia);
994 #ifndef TM_TXVU_H /* In case GDB hasn't been configured yet */
995 enum txvu_cpu_context
997 TXVU_CPU_AUTO = -1, /* context-sensitive context */
998 TXVU_CPU_MASTER = 0, /* R5900 core */
999 TXVU_CPU_VU0 = 1, /* Vector units */
1001 TXVU_CPU_VIF0 = 3, /* FIFO's */
1003 TXVU_CPU_LAST /* Count of context types */
1006 /* memory segment for communication with GDB */
1007 #define GDB_COMM_AREA 0x21010000
1008 #define GDB_COMM_SIZE 0x4000
1010 /* Memory address containing last device to execute */
1011 #define LAST_DEVICE GDB_COMM_AREA
1013 #define BREAK_MASK 0x02 /* Breakpoint bit is #57 */
1014 #endif /* !TM_TXVU_H */
1015 #endif /* TARGET_SKY */
1016 /* end-sanitize-sky */
1018 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1019 #include "sim-main.c"