sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 // In mips.igen, the semantics for many of the instructions were created
   4 // using code generated by gencode.  Those semantic segments could be
   5 // greatly simplified.
   6 //
   7 //    <insn> ::=
   8 //        <insn-word> { "+" <insn-word> }
   9 //        ":" <format-name>
  10 //        ":" <filter-flags>
  11 //        ":" <options>
  12 //        ":" <name>
  13 //        <nl>
  14 //        { <insn-model> }
  15 //        { <insn-mnemonic> }
  16 //        <code-block>
  17 //
  18
  19
  20 // IGEN config - mips16
  21 // :option:16::insn-bit-size:16
  22 // :option:16::hi-bit-nr:15
  23 :option:16::insn-specifying-widths:true
  24 :option:16::gen-delayed-branch:false
  25
  26 // IGEN config - mips32/64..
  27 // :option:32::insn-bit-size:32
  28 // :option:32::hi-bit-nr:31
  29 :option:32::insn-specifying-widths:true
  30 :option:32::gen-delayed-branch:false
  31
  32
  33 // Generate separate simulators for each target
  34 // :option:::multi-sim:true
  35
  36
  37 // Models known by this simulator
  38 :model:::mipsI:mips3000:
  39 :model:::mipsII:mips6000:
  40 :model:::mipsIII:mips4000:
  41 :model:::mipsIV:mips8000:
  42 :model:::mips16:mips16:
  43 // start-sanitize-r5900
  44 :model:::r5900:mips5900:
  45 // end-sanitize-r5900
  46 :model:::r3900:mips3900:
  47 // start-sanitize-tx19
  48 :model:::tx19:tx19:
  49 // end-sanitize-tx19
  50 :model:::vr4100:mips4100:
  51 // start-sanitize-vr4xxx
  52 :model:::vr4121:mips4121:
  53 // end-sanitize-vr4xxx
  54 // start-sanitize-vr4320
  55 :model:::vr4320:mips4320:
  56 // end-sanitize-vr4320
  57 // start-sanitize-cygnus
  58 :model:::vr5400:mips5400:
  59 :model:::mdmx:mdmx:
  60 // end-sanitize-cygnus
  61 :model:::vr5000:mips5000:
  62
  63
  64
  65 // Pseudo instructions known by IGEN
  66 :internal::::illegal:
  67 {
  68   SignalException (ReservedInstruction, 0);
  69 }
  70
  71
  72 // Pseudo instructions known by interp.c
  73 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  74 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  75 "rsvd <OP>"
  76 {
  77   SignalException (ReservedInstruction, instruction_0);
  78 }
  79
  80
  81
  82 // Helper:
  83 //
  84 // Simulate a 32 bit delayslot instruction
  85 //
  86
  87 :function:::address_word:delayslot32:address_word target
  88 {
  89   instruction_word delay_insn;
  90   sim_events_slip (SD, 1);
  91   DSPC = CIA;
  92   CIA = CIA + 4; /* NOTE not mips16 */
  93   STATE |= simDELAYSLOT;
  94   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  95   idecode_issue (CPU_, delay_insn, (CIA));
  96   STATE &= ~simDELAYSLOT;
  97   return target;
  98 }
  99
 100 :function:::address_word:nullify_next_insn32:
 101 {
 102   sim_events_slip (SD, 1);
 103   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 104   return CIA + 8;
 105 }
 106
 107 // start-sanitize-branchbug4011
 108 :function:::void:check_4011_branch_bug:
 109 {
 110   if (BRANCHBUG4011_OPTION == 2 && BRANCHBUG4011_LAST_TARGET == CIA)
 111     sim_engine_abort (SD, CPU, CIA, "4011 BRANCH BUG: %s at 0x%08lx was target of branch at 0x%08lx\n",
 112                       itable[MY_INDEX].name,
 113                       (long) CIA,
 114                       (long) BRANCHBUG4011_LAST_CIA);
 115 }
 116
 117 :function:::void:mark_4011_branch_bug:address_word target
 118 {
 119   if (BRANCHBUG4011_OPTION)
 120     {
 121       BRANCHBUG4011_OPTION = 2;
 122       BRANCHBUG4011_LAST_TARGET = target;
 123       BRANCHBUG4011_LAST_CIA = CIA;
 124     }
 125 }
 126
 127 // end-sanitize-branchbug4011
 128 // Helper:
 129 //
 130 // Check that an access to a HI/LO register meets timing requirements
 131 //
 132 // The following requirements exist:
 133 //
 134 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 135 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 136 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 137 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 138 //
 139
 140 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 141 {
 142   if (history->mf.timestamp + 3 > time)
 143     {
 144       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 145                         itable[MY_INDEX].name,
 146                         new, (long) CIA,
 147                         (long) history->mf.cia);
 148       return 0;
 149     }
 150   return 1;
 151 }
 152
 153 :function:::int:check_mt_hilo:hilo_history *history
 154 *mipsI,mipsII,mipsIII,mipsIV:
 155 *vr4100:
 156 *vr5000:
 157 // start-sanitize-vr4xxx
 158 *vr4121:
 159 // end-sanitize-vr4xxx
 160 // start-sanitize-vr4320
 161 *vr4320:
 162 // end-sanitize-vr4320
 163 // start-sanitize-cygnus
 164 *vr5400:
 165 // end-sanitize-cygnus
 166 {
 167   signed64 time = sim_events_time (SD);
 168   int ok = check_mf_cycles (SD_, history, time, "MT");
 169   history->mt.timestamp = time;
 170   history->mt.cia = CIA;
 171   return ok;
 172 }
 173
 174 :function:::int:check_mt_hilo:hilo_history *history
 175 *r3900:
 176 // start-sanitize-tx19
 177 *tx19:
 178 // end-sanitize-tx19
 179 // start-sanitize-r5900
 180 *r5900:
 181 // end-sanitize-r5900
 182 {
 183   signed64 time = sim_events_time (SD);
 184   history->mt.timestamp = time;
 185   history->mt.cia = CIA;
 186   return 1;
 187 }
 188
 189
 190 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 191 *mipsI,mipsII,mipsIII,mipsIV:
 192 *vr4100:
 193 *vr5000:
 194 // start-sanitize-vr4xxx
 195 *vr4121:
 196 // end-sanitize-vr4xxx
 197 // start-sanitize-vr4320
 198 *vr4320:
 199 // end-sanitize-vr4320
 200 // start-sanitize-cygnus
 201 *vr5400:
 202 // end-sanitize-cygnus
 203 *r3900:
 204 // start-sanitize-tx19
 205 *tx19:
 206 // end-sanitize-tx19
 207 {
 208   signed64 time = sim_events_time (SD);
 209   int ok = 1;
 210   if (peer != NULL
 211       && peer->mt.timestamp > history->op.timestamp
 212       && history->mt.timestamp < history->op.timestamp
 213       && ! (history->mf.timestamp > history->op.timestamp
 214             && history->mf.timestamp < peer->mt.timestamp)
 215       && ! (peer->mf.timestamp > history->op.timestamp
 216             && peer->mf.timestamp < peer->mt.timestamp))
 217     {
 218       /* The peer has been written to since the last OP yet we have
 219          not */
 220       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 221                         itable[MY_INDEX].name,
 222                         (long) CIA,
 223                         (long) history->op.cia,
 224                         (long) peer->mt.cia);
 225       ok = 0;
 226     }
 227   history->mf.timestamp = time;
 228   history->mf.cia = CIA;
 229   return ok;
 230 }
 231
 232 // start-sanitize-r5900
 233 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
 234 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 235 // end-sanitize-r5900
 236 // start-sanitize-r5900
 237 *r5900:
 238 // end-sanitize-r5900
 239 // start-sanitize-r5900
 240 {
 241   /* FIXME: could record the fact that a stall occured if we want */
 242   signed64 time = sim_events_time (SD);
 243   history->mf.timestamp = time;
 244   history->mf.cia = CIA;
 245   return 1;
 246 }
 247 // end-sanitize-r5900
 248
 249
 250 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 251 *mipsI,mipsII,mipsIII,mipsIV:
 252 *vr4100:
 253 *vr5000:
 254 // start-sanitize-vr4xxx
 255 *vr4121:
 256 // end-sanitize-vr4xxx
 257 // start-sanitize-vr4320
 258 *vr4320:
 259 // end-sanitize-vr4320
 260 // start-sanitize-cygnus
 261 *vr5400:
 262 // end-sanitize-cygnus
 263 {
 264   signed64 time = sim_events_time (SD);
 265   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 266             && check_mf_cycles (SD_, lo, time, "OP"));
 267   hi->op.timestamp = time;
 268   lo->op.timestamp = time;
 269   hi->op.cia = CIA;
 270   lo->op.cia = CIA;
 271   return ok;
 272 }
 273
 274 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 275 // a mf{hi,lo}
 276 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 277 *r3900:
 278 // start-sanitize-tx19
 279 *tx19:
 280 // end-sanitize-tx19
 281 // start-sanitize-r5900
 282 *r5900:
 283 // end-sanitize-r5900
 284 {
 285   /* FIXME: could record the fact that a stall occured if we want */
 286   signed64 time = sim_events_time (SD);
 287   hi->op.timestamp = time;
 288   lo->op.timestamp = time;
 289   hi->op.cia = CIA;
 290   lo->op.cia = CIA;
 291   return 1;
 292 }
 293
 294
 295 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 296 *mipsI,mipsII,mipsIII,mipsIV:
 297 *vr4100:
 298 *vr5000:
 299 // start-sanitize-vr4xxx
 300 *vr4121:
 301 // end-sanitize-vr4xxx
 302 // start-sanitize-vr4320
 303 *vr4320:
 304 // end-sanitize-vr4320
 305 // start-sanitize-cygnus
 306 *vr5400:
 307 // end-sanitize-cygnus
 308 *r3900:
 309 // start-sanitize-tx19
 310 *tx19:
 311 // end-sanitize-tx19
 312 {
 313   signed64 time = sim_events_time (SD);
 314   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 315             && check_mf_cycles (SD_, lo, time, "OP"));
 316   hi->op.timestamp = time;
 317   lo->op.timestamp = time;
 318   hi->op.cia = CIA;
 319   lo->op.cia = CIA;
 320   return ok;
 321 }
 322
 323
 324 // start-sanitize-r5900
 325 // The r5900 div et.al insns _can_ be exectuted immediatly after
 326 // a mf{hi,lo}
 327 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 328 // end-sanitize-r5900
 329 // start-sanitize-r5900
 330 *r5900:
 331 // end-sanitize-r5900
 332 // start-sanitize-r5900
 333 {
 334   /* FIXME: could record the fact that a stall occured if we want */
 335   signed64 time = sim_events_time (SD);
 336   hi->op.timestamp = time;
 337   lo->op.timestamp = time;
 338   hi->op.cia = CIA;
 339   lo->op.cia = CIA;
 340   return 1;
 341 }
 342 // end-sanitize-r5900
 343
 344
 345
 346 //
 347 // Mips Architecture:
 348 //
 349 //        CPU Instruction Set (mipsI - mipsIV)
 350 //
 351
 352
 353
 354 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 355 "add r<RD>, r<RS>, r<RT>"
 356 *mipsI,mipsII,mipsIII,mipsIV:
 357 *vr4100:
 358 *vr5000:
 359 // start-sanitize-vr4xxx
 360 *vr4121:
 361 // end-sanitize-vr4xxx
 362 // start-sanitize-vr4320
 363 *vr4320:
 364 // end-sanitize-vr4320
 365 // start-sanitize-cygnus
 366 *vr5400:
 367 // end-sanitize-cygnus
 368 // start-sanitize-r5900
 369 *r5900:
 370 // end-sanitize-r5900
 371 *r3900:
 372 // start-sanitize-tx19
 373 *tx19:
 374 // end-sanitize-tx19
 375 {
 376   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 377   {
 378     ALU32_BEGIN (GPR[RS]);
 379     ALU32_ADD (GPR[RT]);
 380     ALU32_END (GPR[RD]);
 381   }
 382   TRACE_ALU_RESULT (GPR[RD]);
 383 }
 384
 385
 386
 387 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 388 "addi r<RT>, r<RS>, IMMEDIATE"
 389 *mipsI,mipsII,mipsIII,mipsIV:
 390 *vr4100:
 391 *vr5000:
 392 // start-sanitize-vr4xxx
 393 *vr4121:
 394 // end-sanitize-vr4xxx
 395 // start-sanitize-vr4320
 396 *vr4320:
 397 // end-sanitize-vr4320
 398 // start-sanitize-cygnus
 399 *vr5400:
 400 // end-sanitize-cygnus
 401 // start-sanitize-r5900
 402 *r5900:
 403 // end-sanitize-r5900
 404 *r3900:
 405 // start-sanitize-tx19
 406 *tx19:
 407 // end-sanitize-tx19
 408 {
 409   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 410   {
 411     ALU32_BEGIN (GPR[RS]);
 412     ALU32_ADD (EXTEND16 (IMMEDIATE));
 413     ALU32_END (GPR[RT]);
 414   }
 415   TRACE_ALU_RESULT (GPR[RT]);
 416 }
 417
 418
 419
 420 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 421 {
 422   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 423   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 424   TRACE_ALU_RESULT (GPR[rt]);
 425 }
 426
 427 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 428 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 429 *mipsI,mipsII,mipsIII,mipsIV:
 430 *vr4100:
 431 *vr5000:
 432 // start-sanitize-vr4xxx
 433 *vr4121:
 434 // end-sanitize-vr4xxx
 435 // start-sanitize-vr4320
 436 *vr4320:
 437 // end-sanitize-vr4320
 438 // start-sanitize-cygnus
 439 *vr5400:
 440 // end-sanitize-cygnus
 441 // start-sanitize-r5900
 442 *r5900:
 443 // end-sanitize-r5900
 444 *r3900:
 445 // start-sanitize-tx19
 446 *tx19:
 447 // end-sanitize-tx19
 448 {
 449   do_addiu (SD_, RS, RT, IMMEDIATE);
 450 }
 451
 452
 453
 454 :function:::void:do_addu:int rs, int rt, int rd
 455 {
 456   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 457   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 458   TRACE_ALU_RESULT (GPR[rd]);
 459 }
 460
 461 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 462 "addu r<RD>, r<RS>, r<RT>"
 463 *mipsI,mipsII,mipsIII,mipsIV:
 464 *vr4100:
 465 *vr5000:
 466 // start-sanitize-vr4xxx
 467 *vr4121:
 468 // end-sanitize-vr4xxx
 469 // start-sanitize-vr4320
 470 *vr4320:
 471 // end-sanitize-vr4320
 472 // start-sanitize-cygnus
 473 *vr5400:
 474 // end-sanitize-cygnus
 475 // start-sanitize-r5900
 476 *r5900:
 477 // end-sanitize-r5900
 478 *r3900:
 479 // start-sanitize-tx19
 480 *tx19:
 481 // end-sanitize-tx19
 482 {
 483   do_addu (SD_, RS, RT, RD);
 484 }
 485
 486
 487
 488 :function:::void:do_and:int rs, int rt, int rd
 489 {
 490   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 491   GPR[rd] = GPR[rs] & GPR[rt];
 492   TRACE_ALU_RESULT (GPR[rd]);
 493 }
 494
 495 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 496 "and r<RD>, r<RS>, r<RT>"
 497 *mipsI,mipsII,mipsIII,mipsIV:
 498 *vr4100:
 499 *vr5000:
 500 // start-sanitize-vr4xxx
 501 *vr4121:
 502 // end-sanitize-vr4xxx
 503 // start-sanitize-vr4320
 504 *vr4320:
 505 // end-sanitize-vr4320
 506 // start-sanitize-cygnus
 507 *vr5400:
 508 // end-sanitize-cygnus
 509 // start-sanitize-r5900
 510 *r5900:
 511 // end-sanitize-r5900
 512 *r3900:
 513 // start-sanitize-tx19
 514 *tx19:
 515 // end-sanitize-tx19
 516 {
 517   do_and (SD_, RS, RT, RD);
 518 }
 519
 520
 521
 522 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 523 "and r<RT>, r<RS>, <IMMEDIATE>"
 524 *mipsI,mipsII,mipsIII,mipsIV:
 525 *vr4100:
 526 *vr5000:
 527 // start-sanitize-vr4xxx
 528 *vr4121:
 529 // end-sanitize-vr4xxx
 530 // start-sanitize-vr4320
 531 *vr4320:
 532 // end-sanitize-vr4320
 533 // start-sanitize-cygnus
 534 *vr5400:
 535 // end-sanitize-cygnus
 536 // start-sanitize-r5900
 537 *r5900:
 538 // end-sanitize-r5900
 539 *r3900:
 540 // start-sanitize-tx19
 541 *tx19:
 542 // end-sanitize-tx19
 543 {
 544   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 545   GPR[RT] = GPR[RS] & IMMEDIATE;
 546   TRACE_ALU_RESULT (GPR[RT]);
 547 }
 548
 549
 550
 551 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 552 "beq r<RS>, r<RT>, <OFFSET>"
 553 *mipsI,mipsII,mipsIII,mipsIV:
 554 *vr4100:
 555 *vr5000:
 556 // start-sanitize-vr4xxx
 557 *vr4121:
 558 // end-sanitize-vr4xxx
 559 // start-sanitize-vr4320
 560 *vr4320:
 561 // end-sanitize-vr4320
 562 // start-sanitize-cygnus
 563 *vr5400:
 564 // end-sanitize-cygnus
 565 // start-sanitize-r5900
 566 *r5900:
 567 // end-sanitize-r5900
 568 *r3900:
 569 // start-sanitize-tx19
 570 *tx19:
 571 // end-sanitize-tx19
 572 {
 573   address_word offset = EXTEND16 (OFFSET) << 2;
 574   check_branch_bug ();
 575   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 576     {
 577       mark_branch_bug (NIA+offset);
 578       DELAY_SLOT (NIA + offset);
 579     }
 580 }
 581
 582
 583
 584 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 585 "beql r<RS>, r<RT>, <OFFSET>"
 586 *mipsII:
 587 *mipsIII:
 588 *mipsIV:
 589 *vr4100:
 590 *vr5000:
 591 // start-sanitize-vr4xxx
 592 *vr4121:
 593 // end-sanitize-vr4xxx
 594 // start-sanitize-vr4320
 595 *vr4320:
 596 // end-sanitize-vr4320
 597 // start-sanitize-cygnus
 598 *vr5400:
 599 // end-sanitize-cygnus
 600 // start-sanitize-r5900
 601 *r5900:
 602 // end-sanitize-r5900
 603 *r3900:
 604 // start-sanitize-tx19
 605 *tx19:
 606 // end-sanitize-tx19
 607 {
 608   address_word offset = EXTEND16 (OFFSET) << 2;
 609   check_branch_bug ();
 610   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 611     {
 612       mark_branch_bug (NIA+offset);
 613       DELAY_SLOT (NIA + offset);
 614     }
 615   else
 616     NULLIFY_NEXT_INSTRUCTION ();
 617 }
 618
 619
 620
 621 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 622 "bgez r<RS>, <OFFSET>"
 623 *mipsI,mipsII,mipsIII,mipsIV:
 624 *vr4100:
 625 *vr5000:
 626 // start-sanitize-vr4xxx
 627 *vr4121:
 628 // end-sanitize-vr4xxx
 629 // start-sanitize-vr4320
 630 *vr4320:
 631 // end-sanitize-vr4320
 632 // start-sanitize-cygnus
 633 *vr5400:
 634 // end-sanitize-cygnus
 635 // start-sanitize-r5900
 636 *r5900:
 637 // end-sanitize-r5900
 638 *r3900:
 639 // start-sanitize-tx19
 640 *tx19:
 641 // end-sanitize-tx19
 642 {
 643   address_word offset = EXTEND16 (OFFSET) << 2;
 644   check_branch_bug ();
 645   if ((signed_word) GPR[RS] >= 0)
 646     {
 647       mark_branch_bug (NIA+offset);
 648       DELAY_SLOT (NIA + offset);
 649     }
 650 }
 651
 652
 653
 654 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 655 "bgezal r<RS>, <OFFSET>"
 656 *mipsI,mipsII,mipsIII,mipsIV:
 657 *vr4100:
 658 *vr5000:
 659 // start-sanitize-vr4xxx
 660 *vr4121:
 661 // end-sanitize-vr4xxx
 662 // start-sanitize-vr4320
 663 *vr4320:
 664 // end-sanitize-vr4320
 665 // start-sanitize-cygnus
 666 *vr5400:
 667 // end-sanitize-cygnus
 668 // start-sanitize-r5900
 669 *r5900:
 670 // end-sanitize-r5900
 671 *r3900:
 672 // start-sanitize-tx19
 673 *tx19:
 674 // end-sanitize-tx19
 675 {
 676   address_word offset = EXTEND16 (OFFSET) << 2;
 677   check_branch_bug ();
 678   RA = (CIA + 8);
 679   if ((signed_word) GPR[RS] >= 0)
 680     {
 681       mark_branch_bug (NIA+offset);
 682       DELAY_SLOT (NIA + offset);
 683     }
 684 }
 685
 686
 687
 688 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 689 "bgezall r<RS>, <OFFSET>"
 690 *mipsII:
 691 *mipsIII:
 692 *mipsIV:
 693 *vr4100:
 694 *vr5000:
 695 // start-sanitize-vr4xxx
 696 *vr4121:
 697 // end-sanitize-vr4xxx
 698 // start-sanitize-vr4320
 699 *vr4320:
 700 // end-sanitize-vr4320
 701 // start-sanitize-cygnus
 702 *vr5400:
 703 // end-sanitize-cygnus
 704 // start-sanitize-r5900
 705 *r5900:
 706 // end-sanitize-r5900
 707 *r3900:
 708 // start-sanitize-tx19
 709 *tx19:
 710 // end-sanitize-tx19
 711 {
 712   address_word offset = EXTEND16 (OFFSET) << 2;
 713   check_branch_bug ();
 714   RA = (CIA + 8);
 715   /* NOTE: The branch occurs AFTER the next instruction has been
 716      executed */
 717   if ((signed_word) GPR[RS] >= 0)
 718     {
 719       mark_branch_bug (NIA+offset);
 720       DELAY_SLOT (NIA + offset);
 721     }
 722   else
 723     NULLIFY_NEXT_INSTRUCTION ();
 724 }
 725
 726
 727
 728 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 729 "bgezl r<RS>, <OFFSET>"
 730 *mipsII:
 731 *mipsIII:
 732 *mipsIV:
 733 *vr4100:
 734 *vr5000:
 735 // start-sanitize-vr4xxx
 736 *vr4121:
 737 // end-sanitize-vr4xxx
 738 // start-sanitize-vr4320
 739 *vr4320:
 740 // end-sanitize-vr4320
 741 // start-sanitize-cygnus
 742 *vr5400:
 743 // end-sanitize-cygnus
 744 // start-sanitize-r5900
 745 *r5900:
 746 // end-sanitize-r5900
 747 *r3900:
 748 // start-sanitize-tx19
 749 *tx19:
 750 // end-sanitize-tx19
 751 {
 752   address_word offset = EXTEND16 (OFFSET) << 2;
 753   check_branch_bug ();
 754   if ((signed_word) GPR[RS] >= 0)
 755     {
 756       mark_branch_bug (NIA+offset);
 757       DELAY_SLOT (NIA + offset);
 758     }
 759   else
 760     NULLIFY_NEXT_INSTRUCTION ();
 761 }
 762
 763
 764
 765 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 766 "bgtz r<RS>, <OFFSET>"
 767 *mipsI,mipsII,mipsIII,mipsIV:
 768 *vr4100:
 769 *vr5000:
 770 // start-sanitize-vr4xxx
 771 *vr4121:
 772 // end-sanitize-vr4xxx
 773 // start-sanitize-vr4320
 774 *vr4320:
 775 // end-sanitize-vr4320
 776 // start-sanitize-cygnus
 777 *vr5400:
 778 // end-sanitize-cygnus
 779 // start-sanitize-r5900
 780 *r5900:
 781 // end-sanitize-r5900
 782 *r3900:
 783 // start-sanitize-tx19
 784 *tx19:
 785 // end-sanitize-tx19
 786 {
 787   address_word offset = EXTEND16 (OFFSET) << 2;
 788   check_branch_bug ();
 789   if ((signed_word) GPR[RS] > 0)
 790     {
 791       mark_branch_bug (NIA+offset);
 792       DELAY_SLOT (NIA + offset);
 793     }
 794 }
 795
 796
 797
 798 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 799 "bgtzl r<RS>, <OFFSET>"
 800 *mipsII:
 801 *mipsIII:
 802 *mipsIV:
 803 *vr4100:
 804 *vr5000:
 805 // start-sanitize-vr4xxx
 806 *vr4121:
 807 // end-sanitize-vr4xxx
 808 // start-sanitize-vr4320
 809 *vr4320:
 810 // end-sanitize-vr4320
 811 // start-sanitize-cygnus
 812 *vr5400:
 813 // end-sanitize-cygnus
 814 // start-sanitize-r5900
 815 *r5900:
 816 // end-sanitize-r5900
 817 *r3900:
 818 // start-sanitize-tx19
 819 *tx19:
 820 // end-sanitize-tx19
 821 {
 822   address_word offset = EXTEND16 (OFFSET) << 2;
 823   check_branch_bug ();
 824   /* NOTE: The branch occurs AFTER the next instruction has been
 825      executed */
 826   if ((signed_word) GPR[RS] > 0)
 827     {
 828       mark_branch_bug (NIA+offset);
 829       DELAY_SLOT (NIA + offset);
 830     }
 831   else
 832     NULLIFY_NEXT_INSTRUCTION ();
 833 }
 834
 835
 836
 837 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 838 "blez r<RS>, <OFFSET>"
 839 *mipsI,mipsII,mipsIII,mipsIV:
 840 *vr4100:
 841 *vr5000:
 842 // start-sanitize-vr4xxx
 843 *vr4121:
 844 // end-sanitize-vr4xxx
 845 // start-sanitize-vr4320
 846 *vr4320:
 847 // end-sanitize-vr4320
 848 // start-sanitize-cygnus
 849 *vr5400:
 850 // end-sanitize-cygnus
 851 // start-sanitize-r5900
 852 *r5900:
 853 // end-sanitize-r5900
 854 *r3900:
 855 // start-sanitize-tx19
 856 *tx19:
 857 // end-sanitize-tx19
 858 {
 859   address_word offset = EXTEND16 (OFFSET) << 2;
 860   check_branch_bug ();
 861   /* NOTE: The branch occurs AFTER the next instruction has been
 862      executed */
 863   if ((signed_word) GPR[RS] <= 0)
 864     {
 865       mark_branch_bug (NIA+offset);
 866       DELAY_SLOT (NIA + offset);
 867     }
 868 }
 869
 870
 871
 872 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 873 "bgezl r<RS>, <OFFSET>"
 874 *mipsII:
 875 *mipsIII:
 876 *mipsIV:
 877 *vr4100:
 878 *vr5000:
 879 // start-sanitize-vr4xxx
 880 *vr4121:
 881 // end-sanitize-vr4xxx
 882 // start-sanitize-vr4320
 883 *vr4320:
 884 // end-sanitize-vr4320
 885 // start-sanitize-cygnus
 886 *vr5400:
 887 // end-sanitize-cygnus
 888 // start-sanitize-r5900
 889 *r5900:
 890 // end-sanitize-r5900
 891 *r3900:
 892 // start-sanitize-tx19
 893 *tx19:
 894 // end-sanitize-tx19
 895 {
 896   address_word offset = EXTEND16 (OFFSET) << 2;
 897   check_branch_bug ();
 898   if ((signed_word) GPR[RS] <= 0)
 899     {
 900       mark_branch_bug (NIA+offset);
 901       DELAY_SLOT (NIA + offset);
 902     }
 903   else
 904     NULLIFY_NEXT_INSTRUCTION ();
 905 }
 906
 907
 908
 909 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 910 "bltz r<RS>, <OFFSET>"
 911 *mipsI,mipsII,mipsIII,mipsIV:
 912 *vr4100:
 913 *vr5000:
 914 // start-sanitize-vr4xxx
 915 *vr4121:
 916 // end-sanitize-vr4xxx
 917 // start-sanitize-vr4320
 918 *vr4320:
 919 // end-sanitize-vr4320
 920 // start-sanitize-cygnus
 921 *vr5400:
 922 // end-sanitize-cygnus
 923 // start-sanitize-r5900
 924 *r5900:
 925 // end-sanitize-r5900
 926 *r3900:
 927 // start-sanitize-tx19
 928 *tx19:
 929 // end-sanitize-tx19
 930 {
 931   address_word offset = EXTEND16 (OFFSET) << 2;
 932   check_branch_bug ();
 933   if ((signed_word) GPR[RS] < 0)
 934     {
 935       mark_branch_bug (NIA+offset);
 936       DELAY_SLOT (NIA + offset);
 937     }
 938 }
 939
 940
 941
 942 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 943 "bltzal r<RS>, <OFFSET>"
 944 *mipsI,mipsII,mipsIII,mipsIV:
 945 *vr4100:
 946 *vr5000:
 947 // start-sanitize-vr4xxx
 948 *vr4121:
 949 // end-sanitize-vr4xxx
 950 // start-sanitize-vr4320
 951 *vr4320:
 952 // end-sanitize-vr4320
 953 // start-sanitize-cygnus
 954 *vr5400:
 955 // end-sanitize-cygnus
 956 // start-sanitize-r5900
 957 *r5900:
 958 // end-sanitize-r5900
 959 *r3900:
 960 // start-sanitize-tx19
 961 *tx19:
 962 // end-sanitize-tx19
 963 {
 964   address_word offset = EXTEND16 (OFFSET) << 2;
 965   check_branch_bug ();
 966   RA = (CIA + 8);
 967   /* NOTE: The branch occurs AFTER the next instruction has been
 968      executed */
 969   if ((signed_word) GPR[RS] < 0)
 970     {
 971       mark_branch_bug (NIA+offset);
 972       DELAY_SLOT (NIA + offset);
 973     }
 974 }
 975
 976
 977
 978 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 979 "bltzall r<RS>, <OFFSET>"
 980 *mipsII:
 981 *mipsIII:
 982 *mipsIV:
 983 *vr4100:
 984 *vr5000:
 985 // start-sanitize-vr4xxx
 986 *vr4121:
 987 // end-sanitize-vr4xxx
 988 // start-sanitize-vr4320
 989 *vr4320:
 990 // end-sanitize-vr4320
 991 // start-sanitize-cygnus
 992 *vr5400:
 993 // end-sanitize-cygnus
 994 // start-sanitize-r5900
 995 *r5900:
 996 // end-sanitize-r5900
 997 *r3900:
 998 // start-sanitize-tx19
 999 *tx19:
1000 // end-sanitize-tx19
1001 {
1002   address_word offset = EXTEND16 (OFFSET) << 2;
1003   check_branch_bug ();
1004   RA = (CIA + 8);
1005   if ((signed_word) GPR[RS] < 0)
1006     {
1007       mark_branch_bug (NIA+offset);
1008       DELAY_SLOT (NIA + offset);
1009     }
1010   else
1011     NULLIFY_NEXT_INSTRUCTION ();
1012 }
1013
1014
1015
1016 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1017 "bltzl r<RS>, <OFFSET>"
1018 *mipsII:
1019 *mipsIII:
1020 *mipsIV:
1021 *vr4100:
1022 *vr5000:
1023 // start-sanitize-vr4xxx
1024 *vr4121:
1025 // end-sanitize-vr4xxx
1026 // start-sanitize-vr4320
1027 *vr4320:
1028 // end-sanitize-vr4320
1029 // start-sanitize-cygnus
1030 *vr5400:
1031 // end-sanitize-cygnus
1032 // start-sanitize-r5900
1033 *r5900:
1034 // end-sanitize-r5900
1035 *r3900:
1036 // start-sanitize-tx19
1037 *tx19:
1038 // end-sanitize-tx19
1039 {
1040   address_word offset = EXTEND16 (OFFSET) << 2;
1041   check_branch_bug ();
1042   /* NOTE: The branch occurs AFTER the next instruction has been
1043      executed */
1044   if ((signed_word) GPR[RS] < 0)
1045     {
1046       mark_branch_bug (NIA+offset);
1047       DELAY_SLOT (NIA + offset);
1048     }
1049   else
1050     NULLIFY_NEXT_INSTRUCTION ();
1051 }
1052
1053
1054
1055 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1056 "bne r<RS>, r<RT>, <OFFSET>"
1057 *mipsI,mipsII,mipsIII,mipsIV:
1058 *vr4100:
1059 *vr5000:
1060 // start-sanitize-vr4xxx
1061 *vr4121:
1062 // end-sanitize-vr4xxx
1063 // start-sanitize-vr4320
1064 *vr4320:
1065 // end-sanitize-vr4320
1066 // start-sanitize-cygnus
1067 *vr5400:
1068 // end-sanitize-cygnus
1069 // start-sanitize-r5900
1070 *r5900:
1071 // end-sanitize-r5900
1072 *r3900:
1073 // start-sanitize-tx19
1074 *tx19:
1075 // end-sanitize-tx19
1076 {
1077   address_word offset = EXTEND16 (OFFSET) << 2;
1078   check_branch_bug ();
1079   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1080     {
1081       mark_branch_bug (NIA+offset);
1082       DELAY_SLOT (NIA + offset);
1083     }
1084 }
1085
1086
1087
1088 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1089 "bnel r<RS>, r<RT>, <OFFSET>"
1090 *mipsII:
1091 *mipsIII:
1092 *mipsIV:
1093 *vr4100:
1094 *vr5000:
1095 // start-sanitize-vr4xxx
1096 *vr4121:
1097 // end-sanitize-vr4xxx
1098 // start-sanitize-vr4320
1099 *vr4320:
1100 // end-sanitize-vr4320
1101 // start-sanitize-cygnus
1102 *vr5400:
1103 // end-sanitize-cygnus
1104 // start-sanitize-r5900
1105 *r5900:
1106 // end-sanitize-r5900
1107 *r3900:
1108 // start-sanitize-tx19
1109 *tx19:
1110 // end-sanitize-tx19
1111 {
1112   address_word offset = EXTEND16 (OFFSET) << 2;
1113   check_branch_bug ();
1114   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1115     {
1116       mark_branch_bug (NIA+offset);
1117       DELAY_SLOT (NIA + offset);
1118     }
1119   else
1120     NULLIFY_NEXT_INSTRUCTION ();
1121 }
1122
1123
1124
1125 000000,20.CODE,001101:SPECIAL:32::BREAK
1126 "break"
1127 *mipsI,mipsII,mipsIII,mipsIV:
1128 *vr4100:
1129 *vr5000:
1130 // start-sanitize-vr4xxx
1131 *vr4121:
1132 // end-sanitize-vr4xxx
1133 // start-sanitize-vr4320
1134 *vr4320:
1135 // end-sanitize-vr4320
1136 // start-sanitize-cygnus
1137 *vr5400:
1138 // end-sanitize-cygnus
1139 // start-sanitize-r5900
1140 *r5900:
1141 // end-sanitize-r5900
1142 *r3900:
1143 // start-sanitize-tx19
1144 *tx19:
1145 // end-sanitize-tx19
1146 {
1147   /* Check for some break instruction which are reserved for use by the simulator.  */
1148   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1149   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1150       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1151     {
1152       sim_engine_halt (SD, CPU, NULL, cia,
1153                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1154     }
1155   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1156            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1157     {
1158       if (STATE & simDELAYSLOT)
1159         PC = cia - 4; /* reference the branch instruction */
1160       else
1161         PC = cia;
1162       sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1163     }
1164 // start-sanitize-sky
1165 #ifdef TARGET_SKY
1166   else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
1167     {
1168       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
1169     }
1170   else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
1171     {
1172       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
1173     }
1174   else if (break_code == (PRINTF_INSTRUCTION & HALT_INSTRUCTION_MASK))
1175     {
1176       sim_monitor(SD, CPU, cia, 316);   /* Magic number for idt printf routine. */
1177     }
1178   else if (break_code == (LOAD_INSTRUCTION & HALT_INSTRUCTION_MASK))
1179     {
1180       /* This is a multi-phase load instruction.  Load next configured
1181          executable and return its starting PC in A0 ($4). */
1182
1183       if (STATE_MLOAD_INDEX (SD) == STATE_MLOAD_COUNT (SD))
1184         {
1185           sim_io_eprintf (SD, "Cannot load program %d.  Not enough load-next options.\n",
1186                           STATE_MLOAD_COUNT (SD));
1187           A0 = 0;
1188         }
1189       else
1190         {
1191           char* next = STATE_MLOAD_NAME (SD) [STATE_MLOAD_INDEX (SD)];
1192           SIM_RC rc;
1193
1194           STATE_MLOAD_INDEX (SD) ++;
1195
1196           /* call sim_load_file, preserving most previous state */
1197           rc = sim_load (SD, next, NULL, 0);
1198           if(rc != SIM_RC_OK)
1199             {
1200               sim_io_eprintf (SD, "Error during multi-phase load #%d.\n",
1201                               STATE_MLOAD_INDEX (SD));
1202               A0 = 0;
1203             }
1204           else
1205             A0 = STATE_START_ADDR (SD);
1206         }
1207     }
1208 #endif TARGET_SKY
1209 // end-sanitize-sky
1210
1211   else
1212     {
1213       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1214          the exception. */
1215       SignalException(BreakPoint, instruction_0);
1216     }
1217 }
1218
1219
1220
1221
1222
1223
1224 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1225 "dadd r<RD>, r<RS>, r<RT>"
1226 *mipsIII:
1227 *mipsIV:
1228 *vr4100:
1229 *vr5000:
1230 // start-sanitize-vr4xxx
1231 *vr4121:
1232 // end-sanitize-vr4xxx
1233 // start-sanitize-vr4320
1234 *vr4320:
1235 // end-sanitize-vr4320
1236 // start-sanitize-cygnus
1237 *vr5400:
1238 // end-sanitize-cygnus
1239 // start-sanitize-r5900
1240 *r5900:
1241 // end-sanitize-r5900
1242 // start-sanitize-tx19
1243 *tx19:
1244 // end-sanitize-tx19
1245 {
1246   /* this check's for overflow */
1247   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1248   {
1249     ALU64_BEGIN (GPR[RS]);
1250     ALU64_ADD (GPR[RT]);
1251     ALU64_END (GPR[RD]);
1252   }
1253   TRACE_ALU_RESULT (GPR[RD]);
1254 }
1255
1256
1257
1258 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1259 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1260 *mipsIII:
1261 *mipsIV:
1262 *vr4100:
1263 *vr5000:
1264 // start-sanitize-vr4xxx
1265 *vr4121:
1266 // end-sanitize-vr4xxx
1267 // start-sanitize-vr4320
1268 *vr4320:
1269 // end-sanitize-vr4320
1270 // start-sanitize-cygnus
1271 *vr5400:
1272 // end-sanitize-cygnus
1273 // start-sanitize-r5900
1274 *r5900:
1275 // end-sanitize-r5900
1276 // start-sanitize-tx19
1277 *tx19:
1278 // end-sanitize-tx19
1279 {
1280   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1281   {
1282     ALU64_BEGIN (GPR[RS]);
1283     ALU64_ADD (EXTEND16 (IMMEDIATE));
1284     ALU64_END (GPR[RT]);
1285   }
1286   TRACE_ALU_RESULT (GPR[RT]);
1287 }
1288
1289
1290
1291 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1292 {
1293   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1294   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1295   TRACE_ALU_RESULT (GPR[rt]);
1296 }
1297
1298 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1299 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1300 *mipsIII:
1301 *mipsIV:
1302 *vr4100:
1303 *vr5000:
1304 // start-sanitize-vr4xxx
1305 *vr4121:
1306 // end-sanitize-vr4xxx
1307 // start-sanitize-vr4320
1308 *vr4320:
1309 // end-sanitize-vr4320
1310 // start-sanitize-cygnus
1311 *vr5400:
1312 // end-sanitize-cygnus
1313 // start-sanitize-r5900
1314 *r5900:
1315 // end-sanitize-r5900
1316 // start-sanitize-tx19
1317 *tx19:
1318 // end-sanitize-tx19
1319 {
1320   do_daddiu (SD_, RS, RT, IMMEDIATE);
1321 }
1322
1323
1324
1325 :function:::void:do_daddu:int rs, int rt, int rd
1326 {
1327   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1328   GPR[rd] = GPR[rs] + GPR[rt];
1329   TRACE_ALU_RESULT (GPR[rd]);
1330 }
1331
1332 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1333 "daddu r<RD>, r<RS>, r<RT>"
1334 *mipsIII:
1335 *mipsIV:
1336 *vr4100:
1337 *vr5000:
1338 // start-sanitize-vr4xxx
1339 *vr4121:
1340 // end-sanitize-vr4xxx
1341 // start-sanitize-vr4320
1342 *vr4320:
1343 // end-sanitize-vr4320
1344 // start-sanitize-cygnus
1345 *vr5400:
1346 // end-sanitize-cygnus
1347 // start-sanitize-r5900
1348 *r5900:
1349 // end-sanitize-r5900
1350 // start-sanitize-tx19
1351 *tx19:
1352 // end-sanitize-tx19
1353 {
1354   do_daddu (SD_, RS, RT, RD);
1355 }
1356
1357
1358
1359 :function:::void:do_ddiv:int rs, int rt
1360 {
1361   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1362   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1363   {
1364     signed64 n = GPR[rs];
1365     signed64 d = GPR[rt];
1366     signed64 hi;
1367     signed64 lo;
1368     if (d == 0)
1369       {
1370         lo = SIGNED64 (0x8000000000000000);
1371         hi = 0;
1372       }
1373     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1374       {
1375         lo = SIGNED64 (0x8000000000000000);
1376         hi = 0;
1377       }
1378     else
1379       {
1380         lo = (n / d);
1381         hi = (n % d);
1382       }
1383     HI = hi;
1384     LO = lo;
1385   }
1386   TRACE_ALU_RESULT2 (HI, LO);
1387 }
1388
1389 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1390 "ddiv r<RS>, r<RT>"
1391 *mipsIII:
1392 *mipsIV:
1393 *vr4100:
1394 *vr5000:
1395 // start-sanitize-vr4xxx
1396 *vr4121:
1397 // end-sanitize-vr4xxx
1398 // start-sanitize-vr4320
1399 *vr4320:
1400 // end-sanitize-vr4320
1401 // start-sanitize-cygnus
1402 *vr5400:
1403 // end-sanitize-cygnus
1404 // start-sanitize-r5900
1405 *r5900:
1406 // end-sanitize-r5900
1407 // start-sanitize-tx19
1408 *tx19:
1409 // end-sanitize-tx19
1410 {
1411   do_ddiv (SD_, RS, RT);
1412 }
1413
1414
1415
1416 :function:::void:do_ddivu:int rs, int rt
1417 {
1418   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1419   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1420   {
1421     unsigned64 n = GPR[rs];
1422     unsigned64 d = GPR[rt];
1423     unsigned64 hi;
1424     unsigned64 lo;
1425     if (d == 0)
1426       {
1427         lo = SIGNED64 (0x8000000000000000);
1428         hi = 0;
1429       }
1430     else
1431       {
1432         lo = (n / d);
1433         hi = (n % d);
1434       }
1435     HI = hi;
1436     LO = lo;
1437   }
1438   TRACE_ALU_RESULT2 (HI, LO);
1439 }
1440
1441 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1442 "ddivu r<RS>, r<RT>"
1443 *mipsIII:
1444 *mipsIV:
1445 *vr4100:
1446 *vr5000:
1447 // start-sanitize-vr4xxx
1448 *vr4121:
1449 // end-sanitize-vr4xxx
1450 // start-sanitize-vr4320
1451 *vr4320:
1452 // end-sanitize-vr4320
1453 // start-sanitize-cygnus
1454 *vr5400:
1455 // end-sanitize-cygnus
1456 // start-sanitize-tx19
1457 *tx19:
1458 // end-sanitize-tx19
1459 {
1460   do_ddivu (SD_, RS, RT);
1461 }
1462
1463
1464
1465 :function:::void:do_div:int rs, int rt
1466 {
1467   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1468   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1469   {
1470     signed32 n = GPR[rs];
1471     signed32 d = GPR[rt];
1472     if (d == 0)
1473       {
1474         LO = EXTEND32 (0x80000000);
1475         HI = EXTEND32 (0);
1476       }
1477     else if (n == SIGNED32 (0x80000000) && d == -1)
1478       {
1479         LO = EXTEND32 (0x80000000);
1480         HI = EXTEND32 (0);
1481       }
1482     else
1483       {
1484         LO = EXTEND32 (n / d);
1485         HI = EXTEND32 (n % d);
1486       }
1487   }
1488   TRACE_ALU_RESULT2 (HI, LO);
1489 }
1490
1491 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1492 "div r<RS>, r<RT>"
1493 *mipsI,mipsII,mipsIII,mipsIV:
1494 *vr4100:
1495 *vr5000:
1496 // start-sanitize-vr4xxx
1497 *vr4121:
1498 // end-sanitize-vr4xxx
1499 // start-sanitize-vr4320
1500 *vr4320:
1501 // end-sanitize-vr4320
1502 // start-sanitize-cygnus
1503 *vr5400:
1504 // end-sanitize-cygnus
1505 // start-sanitize-r5900
1506 *r5900:
1507 // end-sanitize-r5900
1508 *r3900:
1509 // start-sanitize-tx19
1510 *tx19:
1511 // end-sanitize-tx19
1512 {
1513   do_div (SD_, RS, RT);
1514 }
1515
1516
1517
1518 :function:::void:do_divu:int rs, int rt
1519 {
1520   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1521   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1522   {
1523     unsigned32 n = GPR[rs];
1524     unsigned32 d = GPR[rt];
1525     if (d == 0)
1526       {
1527         LO = EXTEND32 (0x80000000);
1528         HI = EXTEND32 (0);
1529       }
1530    else
1531      {
1532        LO = EXTEND32 (n / d);
1533        HI = EXTEND32 (n % d);
1534      }
1535   }
1536   TRACE_ALU_RESULT2 (HI, LO);
1537 }
1538
1539 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1540 "divu r<RS>, r<RT>"
1541 *mipsI,mipsII,mipsIII,mipsIV:
1542 *vr4100:
1543 *vr5000:
1544 // start-sanitize-vr4xxx
1545 *vr4121:
1546 // end-sanitize-vr4xxx
1547 // start-sanitize-vr4320
1548 *vr4320:
1549 // end-sanitize-vr4320
1550 // start-sanitize-cygnus
1551 *vr5400:
1552 // end-sanitize-cygnus
1553 // start-sanitize-r5900
1554 *r5900:
1555 // end-sanitize-r5900
1556 *r3900:
1557 // start-sanitize-tx19
1558 *tx19:
1559 // end-sanitize-tx19
1560 {
1561   do_divu (SD_, RS, RT);
1562 }
1563
1564
1565
1566 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1567 {
1568   unsigned64 lo;
1569   unsigned64 hi;
1570   unsigned64 m00;
1571   unsigned64 m01;
1572   unsigned64 m10;
1573   unsigned64 m11;
1574   unsigned64 mid;
1575   int sign;
1576   unsigned64 op1 = GPR[rs];
1577   unsigned64 op2 = GPR[rt];
1578   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1579   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1580   /* make signed multiply unsigned */
1581   sign = 0;
1582   if (signed_p)
1583     {
1584       if (op1 < 0)
1585         {
1586           op1 = - op1;
1587           ++sign;
1588         }
1589       if (op2 < 0)
1590         {
1591           op2 = - op2;
1592           ++sign;
1593         }
1594     }
1595   /* multuply out the 4 sub products */
1596   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1597   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1598   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1599   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1600   /* add the products */
1601   mid = ((unsigned64) VH4_8 (m00)
1602          + (unsigned64) VL4_8 (m10)
1603          + (unsigned64) VL4_8 (m01));
1604   lo = U8_4 (mid, m00);
1605   hi = (m11
1606         + (unsigned64) VH4_8 (mid)
1607         + (unsigned64) VH4_8 (m01)
1608         + (unsigned64) VH4_8 (m10));
1609   /* fix the sign */
1610   if (sign & 1)
1611     {
1612       lo = -lo;
1613       if (lo == 0)
1614         hi = -hi;
1615       else
1616         hi = -hi - 1;
1617     }
1618   /* save the result HI/LO (and a gpr) */
1619   LO = lo;
1620   HI = hi;
1621   if (rd != 0)
1622     GPR[rd] = lo;
1623   TRACE_ALU_RESULT2 (HI, LO);
1624 }
1625
1626 :function:::void:do_dmult:int rs, int rt, int rd
1627 {
1628   do_dmultx (SD_, rs, rt, rd, 1);
1629 }
1630
1631 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1632 "dmult r<RS>, r<RT>"
1633 *mipsIII,mipsIV:
1634 *vr4100:
1635 // start-sanitize-vr4xxx
1636 *vr4121:
1637 // end-sanitize-vr4xxx
1638 // start-sanitize-tx19
1639 *tx19:
1640 // end-sanitize-tx19
1641 // start-sanitize-vr4320
1642 *vr4320:
1643 // end-sanitize-vr4320
1644 {
1645   do_dmult (SD_, RS, RT, 0);
1646 }
1647
1648 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1649 "dmult r<RS>, r<RT>":RD == 0
1650 "dmult r<RD>, r<RS>, r<RT>"
1651 *vr5000:
1652 // start-sanitize-cygnus
1653 *vr5400:
1654 // end-sanitize-cygnus
1655 {
1656   do_dmult (SD_, RS, RT, RD);
1657 }
1658
1659
1660
1661 :function:::void:do_dmultu:int rs, int rt, int rd
1662 {
1663   do_dmultx (SD_, rs, rt, rd, 0);
1664 }
1665
1666 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1667 "dmultu r<RS>, r<RT>"
1668 *mipsIII,mipsIV:
1669 *vr4100:
1670 // start-sanitize-vr4xxx
1671 *vr4121:
1672 // end-sanitize-vr4xxx
1673 // start-sanitize-tx19
1674 *tx19:
1675 // end-sanitize-tx19
1676 // start-sanitize-vr4320
1677 *vr4320:
1678 // end-sanitize-vr4320
1679 {
1680   do_dmultu (SD_, RS, RT, 0);
1681 }
1682
1683 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1684 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1685 "dmultu r<RS>, r<RT>"
1686 *vr5000:
1687 // start-sanitize-cygnus
1688 *vr5400:
1689 // end-sanitize-cygnus
1690 {
1691   do_dmultu (SD_, RS, RT, RD);
1692 }
1693
1694 :function:::void:do_dsll:int rt, int rd, int shift
1695 {
1696   GPR[rd] = GPR[rt] << shift;
1697 }
1698
1699 :function:::void:do_dsllv:int rs, int rt, int rd
1700 {
1701   int s = MASKED64 (GPR[rs], 5, 0);
1702   GPR[rd] = GPR[rt] << s;
1703 }
1704
1705
1706 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1707 "dsll r<RD>, r<RT>, <SHIFT>"
1708 *mipsIII:
1709 *mipsIV:
1710 *vr4100:
1711 *vr5000:
1712 // start-sanitize-vr4xxx
1713 *vr4121:
1714 // end-sanitize-vr4xxx
1715 // start-sanitize-vr4320
1716 *vr4320:
1717 // end-sanitize-vr4320
1718 // start-sanitize-cygnus
1719 *vr5400:
1720 // end-sanitize-cygnus
1721 // start-sanitize-r5900
1722 *r5900:
1723 // end-sanitize-r5900
1724 // start-sanitize-tx19
1725 *tx19:
1726 // end-sanitize-tx19
1727 {
1728   do_dsll (SD_, RT, RD, SHIFT);
1729 }
1730
1731
1732 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1733 "dsll32 r<RD>, r<RT>, <SHIFT>"
1734 *mipsIII:
1735 *mipsIV:
1736 *vr4100:
1737 *vr5000:
1738 // start-sanitize-vr4xxx
1739 *vr4121:
1740 // end-sanitize-vr4xxx
1741 // start-sanitize-vr4320
1742 *vr4320:
1743 // end-sanitize-vr4320
1744 // start-sanitize-cygnus
1745 *vr5400:
1746 // end-sanitize-cygnus
1747 // start-sanitize-r5900
1748 *r5900:
1749 // end-sanitize-r5900
1750 // start-sanitize-tx19
1751 *tx19:
1752 // end-sanitize-tx19
1753 {
1754   int s = 32 + SHIFT;
1755   GPR[RD] = GPR[RT] << s;
1756 }
1757
1758 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1759 "dsllv r<RD>, r<RT>, r<RS>"
1760 *mipsIII:
1761 *mipsIV:
1762 *vr4100:
1763 *vr5000:
1764 // start-sanitize-vr4xxx
1765 *vr4121:
1766 // end-sanitize-vr4xxx
1767 // start-sanitize-vr4320
1768 *vr4320:
1769 // end-sanitize-vr4320
1770 // start-sanitize-cygnus
1771 *vr5400:
1772 // end-sanitize-cygnus
1773 // start-sanitize-r5900
1774 *r5900:
1775 // end-sanitize-r5900
1776 // start-sanitize-tx19
1777 *tx19:
1778 // end-sanitize-tx19
1779 {
1780   do_dsllv (SD_, RS, RT, RD);
1781 }
1782
1783 :function:::void:do_dsra:int rt, int rd, int shift
1784 {
1785   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1786 }
1787
1788
1789 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1790 "dsra r<RD>, r<RT>, <SHIFT>"
1791 *mipsIII:
1792 *mipsIV:
1793 *vr4100:
1794 *vr5000:
1795 // start-sanitize-vr4xxx
1796 *vr4121:
1797 // end-sanitize-vr4xxx
1798 // start-sanitize-vr4320
1799 *vr4320:
1800 // end-sanitize-vr4320
1801 // start-sanitize-cygnus
1802 *vr5400:
1803 // end-sanitize-cygnus
1804 // start-sanitize-r5900
1805 *r5900:
1806 // end-sanitize-r5900
1807 // start-sanitize-tx19
1808 *tx19:
1809 // end-sanitize-tx19
1810 {
1811   do_dsra (SD_, RT, RD, SHIFT);
1812 }
1813
1814
1815 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1816 "dsra32 r<RT>, r<RD>, <SHIFT>"
1817 *mipsIII:
1818 *mipsIV:
1819 *vr4100:
1820 *vr5000:
1821 // start-sanitize-vr4xxx
1822 *vr4121:
1823 // end-sanitize-vr4xxx
1824 // start-sanitize-vr4320
1825 *vr4320:
1826 // end-sanitize-vr4320
1827 // start-sanitize-cygnus
1828 *vr5400:
1829 // end-sanitize-cygnus
1830 // start-sanitize-r5900
1831 *r5900:
1832 // end-sanitize-r5900
1833 // start-sanitize-tx19
1834 *tx19:
1835 // end-sanitize-tx19
1836 {
1837   int s = 32 + SHIFT;
1838   GPR[RD] = ((signed64) GPR[RT]) >> s;
1839 }
1840
1841
1842 :function:::void:do_dsrav:int rs, int rt, int rd
1843 {
1844   int s = MASKED64 (GPR[rs], 5, 0);
1845   TRACE_ALU_INPUT2 (GPR[rt], s);
1846   GPR[rd] = ((signed64) GPR[rt]) >> s;
1847   TRACE_ALU_RESULT (GPR[rd]);
1848 }
1849
1850 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1851 "dsra32 r<RT>, r<RD>, r<RS>"
1852 *mipsIII:
1853 *mipsIV:
1854 *vr4100:
1855 *vr5000:
1856 // start-sanitize-vr4xxx
1857 *vr4121:
1858 // end-sanitize-vr4xxx
1859 // start-sanitize-vr4320
1860 *vr4320:
1861 // end-sanitize-vr4320
1862 // start-sanitize-cygnus
1863 *vr5400:
1864 // end-sanitize-cygnus
1865 // start-sanitize-r5900
1866 *r5900:
1867 // end-sanitize-r5900
1868 // start-sanitize-tx19
1869 *tx19:
1870 // end-sanitize-tx19
1871 {
1872   do_dsrav (SD_, RS, RT, RD);
1873 }
1874
1875 :function:::void:do_dsrl:int rt, int rd, int shift
1876 {
1877   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1878 }
1879
1880
1881 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1882 "dsrl r<RD>, r<RT>, <SHIFT>"
1883 *mipsIII:
1884 *mipsIV:
1885 *vr4100:
1886 *vr5000:
1887 // start-sanitize-vr4xxx
1888 *vr4121:
1889 // end-sanitize-vr4xxx
1890 // start-sanitize-vr4320
1891 *vr4320:
1892 // end-sanitize-vr4320
1893 // start-sanitize-cygnus
1894 *vr5400:
1895 // end-sanitize-cygnus
1896 // start-sanitize-r5900
1897 *r5900:
1898 // end-sanitize-r5900
1899 // start-sanitize-tx19
1900 *tx19:
1901 // end-sanitize-tx19
1902 {
1903   do_dsrl (SD_, RT, RD, SHIFT);
1904 }
1905
1906
1907 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1908 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1909 *mipsIII:
1910 *mipsIV:
1911 *vr4100:
1912 *vr5000:
1913 // start-sanitize-vr4xxx
1914 *vr4121:
1915 // end-sanitize-vr4xxx
1916 // start-sanitize-vr4320
1917 *vr4320:
1918 // end-sanitize-vr4320
1919 // start-sanitize-cygnus
1920 *vr5400:
1921 // end-sanitize-cygnus
1922 // start-sanitize-r5900
1923 *r5900:
1924 // end-sanitize-r5900
1925 // start-sanitize-tx19
1926 *tx19:
1927 // end-sanitize-tx19
1928 {
1929   int s = 32 + SHIFT;
1930   GPR[RD] = (unsigned64) GPR[RT] >> s;
1931 }
1932
1933
1934 :function:::void:do_dsrlv:int rs, int rt, int rd
1935 {
1936   int s = MASKED64 (GPR[rs], 5, 0);
1937   GPR[rd] = (unsigned64) GPR[rt] >> s;
1938 }
1939
1940
1941
1942 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1943 "dsrl32 r<RD>, r<RT>, r<RS>"
1944 *mipsIII:
1945 *mipsIV:
1946 *vr4100:
1947 *vr5000:
1948 // start-sanitize-vr4xxx
1949 *vr4121:
1950 // end-sanitize-vr4xxx
1951 // start-sanitize-vr4320
1952 *vr4320:
1953 // end-sanitize-vr4320
1954 // start-sanitize-cygnus
1955 *vr5400:
1956 // end-sanitize-cygnus
1957 // start-sanitize-r5900
1958 *r5900:
1959 // end-sanitize-r5900
1960 // start-sanitize-tx19
1961 *tx19:
1962 // end-sanitize-tx19
1963 {
1964   do_dsrlv (SD_, RS, RT, RD);
1965 }
1966
1967
1968 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1969 "dsub r<RD>, r<RS>, r<RT>"
1970 *mipsIII:
1971 *mipsIV:
1972 *vr4100:
1973 *vr5000:
1974 // start-sanitize-vr4xxx
1975 *vr4121:
1976 // end-sanitize-vr4xxx
1977 // start-sanitize-vr4320
1978 *vr4320:
1979 // end-sanitize-vr4320
1980 // start-sanitize-cygnus
1981 *vr5400:
1982 // end-sanitize-cygnus
1983 // start-sanitize-r5900
1984 *r5900:
1985 // end-sanitize-r5900
1986 // start-sanitize-tx19
1987 *tx19:
1988 // end-sanitize-tx19
1989 {
1990   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1991   {
1992     ALU64_BEGIN (GPR[RS]);
1993     ALU64_SUB (GPR[RT]);
1994     ALU64_END (GPR[RD]);
1995   }
1996   TRACE_ALU_RESULT (GPR[RD]);
1997 }
1998
1999
2000 :function:::void:do_dsubu:int rs, int rt, int rd
2001 {
2002   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2003   GPR[rd] = GPR[rs] - GPR[rt];
2004   TRACE_ALU_RESULT (GPR[rd]);
2005 }
2006
2007 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
2008 "dsubu r<RD>, r<RS>, r<RT>"
2009 *mipsIII:
2010 *mipsIV:
2011 *vr4100:
2012 *vr5000:
2013 // start-sanitize-vr4xxx
2014 *vr4121:
2015 // end-sanitize-vr4xxx
2016 // start-sanitize-vr4320
2017 *vr4320:
2018 // end-sanitize-vr4320
2019 // start-sanitize-cygnus
2020 *vr5400:
2021 // end-sanitize-cygnus
2022 // start-sanitize-r5900
2023 *r5900:
2024 // end-sanitize-r5900
2025 // start-sanitize-tx19
2026 *tx19:
2027 // end-sanitize-tx19
2028 {
2029   do_dsubu (SD_, RS, RT, RD);
2030 }
2031
2032
2033 000010,26.INSTR_INDEX:NORMAL:32::J
2034 "j <INSTR_INDEX>"
2035 *mipsI,mipsII,mipsIII,mipsIV:
2036 *vr4100:
2037 *vr5000:
2038 // start-sanitize-vr4xxx
2039 *vr4121:
2040 // end-sanitize-vr4xxx
2041 // start-sanitize-vr4320
2042 *vr4320:
2043 // end-sanitize-vr4320
2044 // start-sanitize-cygnus
2045 *vr5400:
2046 // end-sanitize-cygnus
2047 // start-sanitize-r5900
2048 *r5900:
2049 // end-sanitize-r5900
2050 *r3900:
2051 // start-sanitize-tx19
2052 *tx19:
2053 // end-sanitize-tx19
2054 {
2055   /* NOTE: The region used is that of the delay slot NIA and NOT the
2056      current instruction */
2057   address_word region = (NIA & MASK (63, 28));
2058   DELAY_SLOT (region | (INSTR_INDEX << 2));
2059 }
2060
2061
2062 000011,26.INSTR_INDEX:NORMAL:32::JAL
2063 "jal <INSTR_INDEX>"
2064 *mipsI,mipsII,mipsIII,mipsIV:
2065 *vr4100:
2066 *vr5000:
2067 // start-sanitize-vr4xxx
2068 *vr4121:
2069 // end-sanitize-vr4xxx
2070 // start-sanitize-vr4320
2071 *vr4320:
2072 // end-sanitize-vr4320
2073 // start-sanitize-cygnus
2074 *vr5400:
2075 // end-sanitize-cygnus
2076 // start-sanitize-r5900
2077 *r5900:
2078 // end-sanitize-r5900
2079 *r3900:
2080 // start-sanitize-tx19
2081 *tx19:
2082 // end-sanitize-tx19
2083 {
2084   /* NOTE: The region used is that of the delay slot and NOT the
2085      current instruction */
2086   address_word region = (NIA & MASK (63, 28));
2087   GPR[31] = CIA + 8;
2088   DELAY_SLOT (region | (INSTR_INDEX << 2));
2089 }
2090
2091 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
2092 "jalr r<RS>":RD == 31
2093 "jalr r<RD>, r<RS>"
2094 *mipsI,mipsII,mipsIII,mipsIV:
2095 *vr4100:
2096 *vr5000:
2097 // start-sanitize-vr4xxx
2098 *vr4121:
2099 // end-sanitize-vr4xxx
2100 // start-sanitize-vr4320
2101 *vr4320:
2102 // end-sanitize-vr4320
2103 // start-sanitize-cygnus
2104 *vr5400:
2105 // end-sanitize-cygnus
2106 // start-sanitize-r5900
2107 *r5900:
2108 // end-sanitize-r5900
2109 *r3900:
2110 // start-sanitize-tx19
2111 *tx19:
2112 // end-sanitize-tx19
2113 {
2114   address_word temp = GPR[RS];
2115   GPR[RD] = CIA + 8;
2116   DELAY_SLOT (temp);
2117 }
2118
2119
2120 000000,5.RS,000000000000000001000:SPECIAL:32::JR
2121 "jr r<RS>"
2122 *mipsI,mipsII,mipsIII,mipsIV:
2123 *vr4100:
2124 *vr5000:
2125 // start-sanitize-vr4xxx
2126 *vr4121:
2127 // end-sanitize-vr4xxx
2128 // start-sanitize-vr4320
2129 *vr4320:
2130 // end-sanitize-vr4320
2131 // start-sanitize-cygnus
2132 *vr5400:
2133 // end-sanitize-cygnus
2134 // start-sanitize-r5900
2135 *r5900:
2136 // end-sanitize-r5900
2137 *r3900:
2138 // start-sanitize-tx19
2139 *tx19:
2140 // end-sanitize-tx19
2141 {
2142   DELAY_SLOT (GPR[RS]);
2143 }
2144
2145
2146 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
2147 {
2148   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2149   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2150   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2151   unsigned int byte;
2152   address_word paddr;
2153   int uncached;
2154   unsigned64 memval;
2155   address_word vaddr;
2156
2157   vaddr = base + offset;
2158   if ((vaddr & access) != 0)
2159     {
2160       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
2161     }
2162   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2163   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2164   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
2165   byte = ((vaddr & mask) ^ bigendiancpu);
2166   return (memval >> (8 * byte));
2167 }
2168
2169
2170 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2171 "lb r<RT>, <OFFSET>(r<BASE>)"
2172 *mipsI,mipsII,mipsIII,mipsIV:
2173 *vr4100:
2174 *vr5000:
2175 // start-sanitize-vr4xxx
2176 *vr4121:
2177 // end-sanitize-vr4xxx
2178 // start-sanitize-vr4320
2179 *vr4320:
2180 // end-sanitize-vr4320
2181 // start-sanitize-cygnus
2182 *vr5400:
2183 // end-sanitize-cygnus
2184 // start-sanitize-r5900
2185 *r5900:
2186 // end-sanitize-r5900
2187 *r3900:
2188 // start-sanitize-tx19
2189 *tx19:
2190 // end-sanitize-tx19
2191 {
2192   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2193 }
2194
2195
2196 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2197 "lbu r<RT>, <OFFSET>(r<BASE>)"
2198 *mipsI,mipsII,mipsIII,mipsIV:
2199 *vr4100:
2200 *vr5000:
2201 // start-sanitize-vr4xxx
2202 *vr4121:
2203 // end-sanitize-vr4xxx
2204 // start-sanitize-vr4320
2205 *vr4320:
2206 // end-sanitize-vr4320
2207 // start-sanitize-cygnus
2208 *vr5400:
2209 // end-sanitize-cygnus
2210 // start-sanitize-r5900
2211 *r5900:
2212 // end-sanitize-r5900
2213 *r3900:
2214 // start-sanitize-tx19
2215 *tx19:
2216 // end-sanitize-tx19
2217 {
2218   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2219 }
2220
2221
2222 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2223 "ld r<RT>, <OFFSET>(r<BASE>)"
2224 *mipsIII:
2225 *mipsIV:
2226 *vr4100:
2227 *vr5000:
2228 // start-sanitize-vr4xxx
2229 *vr4121:
2230 // end-sanitize-vr4xxx
2231 // start-sanitize-vr4320
2232 *vr4320:
2233 // end-sanitize-vr4320
2234 // start-sanitize-cygnus
2235 *vr5400:
2236 // end-sanitize-cygnus
2237 // start-sanitize-r5900
2238 *r5900:
2239 // end-sanitize-r5900
2240 // start-sanitize-tx19
2241 *tx19:
2242 // end-sanitize-tx19
2243 {
2244   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2245 }
2246
2247
2248 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2249 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2250 *mipsII:
2251 *mipsIII:
2252 *mipsIV:
2253 *vr4100:
2254 *vr5000:
2255 // start-sanitize-vr4xxx
2256 *vr4121:
2257 // end-sanitize-vr4xxx
2258 // start-sanitize-vr4320
2259 *vr4320:
2260 // end-sanitize-vr4320
2261 // start-sanitize-cygnus
2262 *vr5400:
2263 // end-sanitize-cygnus
2264 *r3900:
2265 // start-sanitize-tx19
2266 *tx19:
2267 // end-sanitize-tx19
2268 {
2269   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2270 }
2271
2272
2273
2274
2275 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2276 "ldl r<RT>, <OFFSET>(r<BASE>)"
2277 *mipsIII:
2278 *mipsIV:
2279 *vr4100:
2280 *vr5000:
2281 // start-sanitize-vr4xxx
2282 *vr4121:
2283 // end-sanitize-vr4xxx
2284 // start-sanitize-vr4320
2285 *vr4320:
2286 // end-sanitize-vr4320
2287 // start-sanitize-cygnus
2288 *vr5400:
2289 // end-sanitize-cygnus
2290 // start-sanitize-r5900
2291 *r5900:
2292 // end-sanitize-r5900
2293 // start-sanitize-tx19
2294 *tx19:
2295 // end-sanitize-tx19
2296 {
2297   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2298 }
2299
2300
2301 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2302 "ldr r<RT>, <OFFSET>(r<BASE>)"
2303 *mipsIII:
2304 *mipsIV:
2305 *vr4100:
2306 *vr5000:
2307 // start-sanitize-vr4xxx
2308 *vr4121:
2309 // end-sanitize-vr4xxx
2310 // start-sanitize-vr4320
2311 *vr4320:
2312 // end-sanitize-vr4320
2313 // start-sanitize-cygnus
2314 *vr5400:
2315 // end-sanitize-cygnus
2316 // start-sanitize-r5900
2317 *r5900:
2318 // end-sanitize-r5900
2319 // start-sanitize-tx19
2320 *tx19:
2321 // end-sanitize-tx19
2322 {
2323   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2324 }
2325
2326
2327 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2328 "lh r<RT>, <OFFSET>(r<BASE>)"
2329 *mipsI,mipsII,mipsIII,mipsIV:
2330 *vr4100:
2331 *vr5000:
2332 // start-sanitize-vr4xxx
2333 *vr4121:
2334 // end-sanitize-vr4xxx
2335 // start-sanitize-vr4320
2336 *vr4320:
2337 // end-sanitize-vr4320
2338 // start-sanitize-cygnus
2339 *vr5400:
2340 // end-sanitize-cygnus
2341 // start-sanitize-r5900
2342 *r5900:
2343 // end-sanitize-r5900
2344 *r3900:
2345 // start-sanitize-tx19
2346 *tx19:
2347 // end-sanitize-tx19
2348 {
2349   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2350 }
2351
2352
2353 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2354 "lhu r<RT>, <OFFSET>(r<BASE>)"
2355 *mipsI,mipsII,mipsIII,mipsIV:
2356 *vr4100:
2357 *vr5000:
2358 // start-sanitize-vr4xxx
2359 *vr4121:
2360 // end-sanitize-vr4xxx
2361 // start-sanitize-vr4320
2362 *vr4320:
2363 // end-sanitize-vr4320
2364 // start-sanitize-cygnus
2365 *vr5400:
2366 // end-sanitize-cygnus
2367 // start-sanitize-r5900
2368 *r5900:
2369 // end-sanitize-r5900
2370 *r3900:
2371 // start-sanitize-tx19
2372 *tx19:
2373 // end-sanitize-tx19
2374 {
2375   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2376 }
2377
2378
2379 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2380 "ll r<RT>, <OFFSET>(r<BASE>)"
2381 *mipsII:
2382 *mipsIII:
2383 *mipsIV:
2384 *vr4100:
2385 *vr5000:
2386 // start-sanitize-vr4xxx
2387 *vr4121:
2388 // end-sanitize-vr4xxx
2389 // start-sanitize-vr4320
2390 *vr4320:
2391 // end-sanitize-vr4320
2392 // start-sanitize-cygnus
2393 *vr5400:
2394 // end-sanitize-cygnus
2395 // start-sanitize-r5900
2396 *r5900:
2397 // end-sanitize-r5900
2398 // start-sanitize-tx19
2399 *tx19:
2400 // end-sanitize-tx19
2401 {
2402   unsigned32 instruction = instruction_0;
2403   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2404   int destreg = ((instruction >> 16) & 0x0000001F);
2405   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2406   {
2407     address_word vaddr = ((unsigned64)op1 + offset);
2408     address_word paddr;
2409     int uncached;
2410     if ((vaddr & 3) != 0)
2411       {
2412         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2413       }
2414     else
2415       {
2416         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2417           {
2418             unsigned64 memval = 0;
2419             unsigned64 memval1 = 0;
2420             unsigned64 mask = 0x7;
2421             unsigned int shift = 2;
2422             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2423             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2424             unsigned int byte;
2425             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2426             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2427             byte = ((vaddr & mask) ^ (bigend << shift));
2428             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2429             LLBIT = 1;
2430           }
2431       }
2432   }
2433 }
2434
2435
2436 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2437 "lld r<RT>, <OFFSET>(r<BASE>)"
2438 *mipsIII:
2439 *mipsIV:
2440 *vr4100:
2441 *vr5000:
2442 // start-sanitize-vr4xxx
2443 *vr4121:
2444 // end-sanitize-vr4xxx
2445 // start-sanitize-vr4320
2446 *vr4320:
2447 // end-sanitize-vr4320
2448 // start-sanitize-cygnus
2449 *vr5400:
2450 // end-sanitize-cygnus
2451 // start-sanitize-r5900
2452 *r5900:
2453 // end-sanitize-r5900
2454 // start-sanitize-tx19
2455 *tx19:
2456 // end-sanitize-tx19
2457 {
2458   unsigned32 instruction = instruction_0;
2459   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2460   int destreg = ((instruction >> 16) & 0x0000001F);
2461   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2462   {
2463     address_word vaddr = ((unsigned64)op1 + offset);
2464     address_word paddr;
2465     int uncached;
2466     if ((vaddr & 7) != 0)
2467       {
2468         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2469       }
2470     else
2471       {
2472         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2473           {
2474             unsigned64 memval = 0;
2475             unsigned64 memval1 = 0;
2476             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2477             GPR[destreg] = memval;
2478             LLBIT = 1;
2479           }
2480       }
2481   }
2482 }
2483
2484
2485 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2486 "lui r<RT>, <IMMEDIATE>"
2487 *mipsI,mipsII,mipsIII,mipsIV:
2488 *vr4100:
2489 *vr5000:
2490 // start-sanitize-vr4xxx
2491 *vr4121:
2492 // end-sanitize-vr4xxx
2493 // start-sanitize-vr4320
2494 *vr4320:
2495 // end-sanitize-vr4320
2496 // start-sanitize-cygnus
2497 *vr5400:
2498 // end-sanitize-cygnus
2499 // start-sanitize-r5900
2500 *r5900:
2501 // end-sanitize-r5900
2502 *r3900:
2503 // start-sanitize-tx19
2504 *tx19:
2505 // end-sanitize-tx19
2506 {
2507   TRACE_ALU_INPUT1 (IMMEDIATE);
2508   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2509   TRACE_ALU_RESULT (GPR[RT]);
2510 }
2511
2512
2513 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2514 "lw r<RT>, <OFFSET>(r<BASE>)"
2515 *mipsI,mipsII,mipsIII,mipsIV:
2516 *vr4100:
2517 *vr5000:
2518 // start-sanitize-vr4xxx
2519 *vr4121:
2520 // end-sanitize-vr4xxx
2521 // start-sanitize-vr4320
2522 *vr4320:
2523 // end-sanitize-vr4320
2524 // start-sanitize-cygnus
2525 *vr5400:
2526 // end-sanitize-cygnus
2527 // start-sanitize-r5900
2528 *r5900:
2529 // end-sanitize-r5900
2530 *r3900:
2531 // start-sanitize-tx19
2532 *tx19:
2533 // end-sanitize-tx19
2534 {
2535   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2536 }
2537
2538
2539 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2540 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2541 *mipsI,mipsII,mipsIII,mipsIV:
2542 *vr4100:
2543 *vr5000:
2544 // start-sanitize-vr4xxx
2545 *vr4121:
2546 // end-sanitize-vr4xxx
2547 // start-sanitize-vr4320
2548 *vr4320:
2549 // end-sanitize-vr4320
2550 // start-sanitize-cygnus
2551 *vr5400:
2552 // end-sanitize-cygnus
2553 // start-sanitize-r5900
2554 *r5900:
2555 // end-sanitize-r5900
2556 *r3900:
2557 // start-sanitize-tx19
2558 *tx19:
2559 // end-sanitize-tx19
2560 {
2561   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2562 }
2563
2564
2565 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2566 {
2567   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2568   address_word reverseendian = (ReverseEndian ? -1 : 0);
2569   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2570   unsigned int byte;
2571   unsigned int word;
2572   address_word paddr;
2573   int uncached;
2574   unsigned64 memval;
2575   address_word vaddr;
2576   int nr_lhs_bits;
2577   int nr_rhs_bits;
2578   unsigned_word lhs_mask;
2579   unsigned_word temp;
2580
2581   vaddr = base + offset;
2582   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2583   paddr = (paddr ^ (reverseendian & mask));
2584   if (BigEndianMem == 0)
2585     paddr = paddr & ~access;
2586
2587   /* compute where within the word/mem we are */
2588   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2589   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2590   nr_lhs_bits = 8 * byte + 8;
2591   nr_rhs_bits = 8 * access - 8 * byte;
2592   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2593
2594   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2595            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2596            (long) ((unsigned64) paddr >> 32), (long) paddr,
2597            word, byte, nr_lhs_bits, nr_rhs_bits); */
2598
2599   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2600   if (word == 0)
2601     {
2602       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2603       temp = (memval << nr_rhs_bits);
2604     }
2605   else
2606     {
2607       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2608       temp = (memval >> nr_lhs_bits);
2609     }
2610   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2611   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2612
2613   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2614            (long) ((unsigned64) memval >> 32), (long) memval,
2615            (long) ((unsigned64) temp >> 32), (long) temp,
2616            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2617            (long) (rt >> 32), (long) rt); */
2618   return rt;
2619 }
2620
2621
2622 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2623 "lwl r<RT>, <OFFSET>(r<BASE>)"
2624 *mipsI,mipsII,mipsIII,mipsIV:
2625 *vr4100:
2626 *vr5000:
2627 // start-sanitize-vr4xxx
2628 *vr4121:
2629 // end-sanitize-vr4xxx
2630 // start-sanitize-vr4320
2631 *vr4320:
2632 // end-sanitize-vr4320
2633 // start-sanitize-cygnus
2634 *vr5400:
2635 // end-sanitize-cygnus
2636 // start-sanitize-r5900
2637 *r5900:
2638 // end-sanitize-r5900
2639 *r3900:
2640 // start-sanitize-tx19
2641 *tx19:
2642 // end-sanitize-tx19
2643 {
2644   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2645 }
2646
2647
2648 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2649 {
2650   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2651   address_word reverseendian = (ReverseEndian ? -1 : 0);
2652   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2653   unsigned int byte;
2654   address_word paddr;
2655   int uncached;
2656   unsigned64 memval;
2657   address_word vaddr;
2658
2659   vaddr = base + offset;
2660   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2661   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2662   paddr = (paddr ^ (reverseendian & mask));
2663   if (BigEndianMem != 0)
2664     paddr = paddr & ~access;
2665   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2666   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2667   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2668   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2669      (long) paddr, byte, (long) paddr, (long) memval); */
2670   {
2671     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2672     rt &= ~screen;
2673     rt |= (memval >> (8 * byte)) & screen;
2674   }
2675   return rt;
2676 }
2677
2678
2679 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2680 "lwr r<RT>, <OFFSET>(r<BASE>)"
2681 *mipsI,mipsII,mipsIII,mipsIV:
2682 *vr4100:
2683 *vr5000:
2684 // start-sanitize-vr4xxx
2685 *vr4121:
2686 // end-sanitize-vr4xxx
2687 // start-sanitize-vr4320
2688 *vr4320:
2689 // end-sanitize-vr4320
2690 // start-sanitize-cygnus
2691 *vr5400:
2692 // end-sanitize-cygnus
2693 // start-sanitize-r5900
2694 *r5900:
2695 // end-sanitize-r5900
2696 *r3900:
2697 // start-sanitize-tx19
2698 *tx19:
2699 // end-sanitize-tx19
2700 {
2701   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2702 }
2703
2704
2705 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2706 "lwu r<RT>, <OFFSET>(r<BASE>)"
2707 *mipsIII:
2708 *mipsIV:
2709 *vr4100:
2710 *vr5000:
2711 // start-sanitize-vr4xxx
2712 *vr4121:
2713 // end-sanitize-vr4xxx
2714 // start-sanitize-vr4320
2715 *vr4320:
2716 // end-sanitize-vr4320
2717 // start-sanitize-cygnus
2718 *vr5400:
2719 // end-sanitize-cygnus
2720 // start-sanitize-r5900
2721 *r5900:
2722 // end-sanitize-r5900
2723 // start-sanitize-tx19
2724 *tx19:
2725 // end-sanitize-tx19
2726 {
2727   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2728 }
2729
2730
2731 :function:::void:do_mfhi:int rd
2732 {
2733   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2734   TRACE_ALU_INPUT1 (HI);
2735   GPR[rd] = HI;
2736   TRACE_ALU_RESULT (GPR[rd]);
2737 }
2738
2739 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2740 "mfhi r<RD>"
2741 *mipsI,mipsII,mipsIII,mipsIV:
2742 *vr4100:
2743 *vr5000:
2744 // start-sanitize-vr4xxx
2745 *vr4121:
2746 // end-sanitize-vr4xxx
2747 // start-sanitize-vr4320
2748 *vr4320:
2749 // end-sanitize-vr4320
2750 // start-sanitize-cygnus
2751 *vr5400:
2752 // end-sanitize-cygnus
2753 // start-sanitize-r5900
2754 *r5900:
2755 // end-sanitize-r5900
2756 *r3900:
2757 // start-sanitize-tx19
2758 *tx19:
2759 // end-sanitize-tx19
2760 {
2761   do_mfhi (SD_, RD);
2762 }
2763
2764
2765
2766 :function:::void:do_mflo:int rd
2767 {
2768   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2769   TRACE_ALU_INPUT1 (LO);
2770   GPR[rd] = LO;
2771   TRACE_ALU_RESULT (GPR[rd]);
2772 }
2773
2774 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2775 "mflo r<RD>"
2776 *mipsI,mipsII,mipsIII,mipsIV:
2777 *vr4100:
2778 *vr5000:
2779 // start-sanitize-vr4xxx
2780 *vr4121:
2781 // end-sanitize-vr4xxx
2782 // start-sanitize-vr4320
2783 *vr4320:
2784 // end-sanitize-vr4320
2785 // start-sanitize-cygnus
2786 *vr5400:
2787 // end-sanitize-cygnus
2788 // start-sanitize-r5900
2789 *r5900:
2790 // end-sanitize-r5900
2791 *r3900:
2792 // start-sanitize-tx19
2793 *tx19:
2794 // end-sanitize-tx19
2795 {
2796   do_mflo (SD_, RD);
2797 }
2798
2799
2800
2801 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2802 "movn r<RD>, r<RS>, r<RT>"
2803 *mipsIV:
2804 *vr5000:
2805 // start-sanitize-vr4xxx
2806 *vr4121:
2807 // end-sanitize-vr4xxx
2808 // start-sanitize-vr4320
2809 *vr4320:
2810 // end-sanitize-vr4320
2811 // start-sanitize-cygnus
2812 *vr5400:
2813 // end-sanitize-cygnus
2814 // start-sanitize-r5900
2815 *r5900:
2816 // end-sanitize-r5900
2817 {
2818   if (GPR[RT] != 0)
2819     GPR[RD] = GPR[RS];
2820 }
2821
2822
2823
2824 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2825 "movz r<RD>, r<RS>, r<RT>"
2826 *mipsIV:
2827 *vr5000:
2828 // start-sanitize-vr4320
2829 *vr4320:
2830 // end-sanitize-vr4320
2831 // start-sanitize-cygnus
2832 *vr5400:
2833 // end-sanitize-cygnus
2834 // start-sanitize-r5900
2835 *r5900:
2836 // end-sanitize-r5900
2837 {
2838   if (GPR[RT] == 0)
2839     GPR[RD] = GPR[RS];
2840 }
2841
2842
2843
2844 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2845 "mthi r<RS>"
2846 *mipsI,mipsII,mipsIII,mipsIV:
2847 *vr4100:
2848 *vr5000:
2849 // start-sanitize-vr4xxx
2850 *vr4121:
2851 // end-sanitize-vr4xxx
2852 // start-sanitize-vr4320
2853 *vr4320:
2854 // end-sanitize-vr4320
2855 // start-sanitize-cygnus
2856 *vr5400:
2857 // end-sanitize-cygnus
2858 // start-sanitize-r5900
2859 *r5900:
2860 // end-sanitize-r5900
2861 *r3900:
2862 // start-sanitize-tx19
2863 *tx19:
2864 // end-sanitize-tx19
2865 {
2866   check_mt_hilo (SD_, HIHISTORY);
2867   HI = GPR[RS];
2868 }
2869
2870
2871
2872 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2873 "mtlo r<RS>"
2874 *mipsI,mipsII,mipsIII,mipsIV:
2875 *vr4100:
2876 *vr5000:
2877 // start-sanitize-vr4xxx
2878 *vr4121:
2879 // end-sanitize-vr4xxx
2880 // start-sanitize-vr4320
2881 *vr4320:
2882 // end-sanitize-vr4320
2883 // start-sanitize-cygnus
2884 *vr5400:
2885 // end-sanitize-cygnus
2886 // start-sanitize-r5900
2887 *r5900:
2888 // end-sanitize-r5900
2889 *r3900:
2890 // start-sanitize-tx19
2891 *tx19:
2892 // end-sanitize-tx19
2893 {
2894   check_mt_hilo (SD_, LOHISTORY);
2895   LO = GPR[RS];
2896 }
2897
2898
2899
2900 :function:::void:do_mult:int rs, int rt, int rd
2901 {
2902   signed64 prod;
2903   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2904   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2905   prod = (((signed64)(signed32) GPR[rs])
2906           * ((signed64)(signed32) GPR[rt]));
2907   LO = EXTEND32 (VL4_8 (prod));
2908   HI = EXTEND32 (VH4_8 (prod));
2909   if (rd != 0)
2910     GPR[rd] = LO;
2911   TRACE_ALU_RESULT2 (HI, LO);
2912 }
2913
2914 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2915 "mult r<RS>, r<RT>"
2916 *mipsI,mipsII,mipsIII,mipsIV:
2917 *vr4100:
2918 // start-sanitize-vr4xxx
2919 *vr4121:
2920 // end-sanitize-vr4xxx
2921 // start-sanitize-vr4320
2922 *vr4320:
2923 // end-sanitize-vr4320
2924 {
2925   do_mult (SD_, RS, RT, 0);
2926 }
2927
2928
2929 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2930 "mult r<RD>, r<RS>, r<RT>"
2931 *vr5000:
2932 // start-sanitize-cygnus
2933 *vr5400:
2934 // end-sanitize-cygnus
2935 // start-sanitize-r5900
2936 *r5900:
2937 // end-sanitize-r5900
2938 *r3900:
2939 // start-sanitize-tx19
2940 *tx19:
2941 // end-sanitize-tx19
2942 {
2943   do_mult (SD_, RS, RT, RD);
2944 }
2945
2946
2947 :function:::void:do_multu:int rs, int rt, int rd
2948 {
2949   unsigned64 prod;
2950   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2951   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2952   prod = (((unsigned64)(unsigned32) GPR[rs])
2953           * ((unsigned64)(unsigned32) GPR[rt]));
2954   LO = EXTEND32 (VL4_8 (prod));
2955   HI = EXTEND32 (VH4_8 (prod));
2956   if (rd != 0)
2957     GPR[rd] = LO;
2958   TRACE_ALU_RESULT2 (HI, LO);
2959 }
2960
2961 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2962 "multu r<RS>, r<RT>"
2963 *mipsI,mipsII,mipsIII,mipsIV:
2964 *vr4100:
2965 // start-sanitize-vr4xxx
2966 *vr4121:
2967 // end-sanitize-vr4xxx
2968 // start-sanitize-vr4320
2969 *vr4320:
2970 // end-sanitize-vr4320
2971 {
2972   do_multu (SD_, RS, RT, 0);
2973 }
2974
2975 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2976 "multu r<RD>, r<RS>, r<RT>"
2977 *vr5000:
2978 // start-sanitize-cygnus
2979 *vr5400:
2980 // end-sanitize-cygnus
2981 // start-sanitize-r5900
2982 *r5900:
2983 // end-sanitize-r5900
2984 *r3900:
2985 // start-sanitize-tx19
2986 *tx19:
2987 // end-sanitize-tx19
2988 {
2989   do_multu (SD_, RS, RT, 0);
2990 }
2991
2992
2993 :function:::void:do_nor:int rs, int rt, int rd
2994 {
2995   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2996   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2997   TRACE_ALU_RESULT (GPR[rd]);
2998 }
2999
3000 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
3001 "nor r<RD>, r<RS>, r<RT>"
3002 *mipsI,mipsII,mipsIII,mipsIV:
3003 *vr4100:
3004 *vr5000:
3005 // start-sanitize-vr4xxx
3006 *vr4121:
3007 // end-sanitize-vr4xxx
3008 // start-sanitize-vr4320
3009 *vr4320:
3010 // end-sanitize-vr4320
3011 // start-sanitize-cygnus
3012 *vr5400:
3013 // end-sanitize-cygnus
3014 // start-sanitize-r5900
3015 *r5900:
3016 // end-sanitize-r5900
3017 *r3900:
3018 // start-sanitize-tx19
3019 *tx19:
3020 // end-sanitize-tx19
3021 {
3022   do_nor (SD_, RS, RT, RD);
3023 }
3024
3025
3026 :function:::void:do_or:int rs, int rt, int rd
3027 {
3028   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3029   GPR[rd] = (GPR[rs] | GPR[rt]);
3030   TRACE_ALU_RESULT (GPR[rd]);
3031 }
3032
3033 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
3034 "or r<RD>, r<RS>, r<RT>"
3035 *mipsI,mipsII,mipsIII,mipsIV:
3036 *vr4100:
3037 *vr5000:
3038 // start-sanitize-vr4xxx
3039 *vr4121:
3040 // end-sanitize-vr4xxx
3041 // start-sanitize-vr4320
3042 *vr4320:
3043 // end-sanitize-vr4320
3044 // start-sanitize-cygnus
3045 *vr5400:
3046 // end-sanitize-cygnus
3047 // start-sanitize-r5900
3048 *r5900:
3049 // end-sanitize-r5900
3050 *r3900:
3051 // start-sanitize-tx19
3052 *tx19:
3053 // end-sanitize-tx19
3054 {
3055   do_or (SD_, RS, RT, RD);
3056 }
3057
3058
3059
3060 :function:::void:do_ori:int rs, int rt, unsigned immediate
3061 {
3062   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3063   GPR[rt] = (GPR[rs] | immediate);
3064   TRACE_ALU_RESULT (GPR[rt]);
3065 }
3066
3067 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
3068 "ori r<RT>, r<RS>, <IMMEDIATE>"
3069 *mipsI,mipsII,mipsIII,mipsIV:
3070 *vr4100:
3071 *vr5000:
3072 // start-sanitize-vr4xxx
3073 *vr4121:
3074 // end-sanitize-vr4xxx
3075 // start-sanitize-vr4320
3076 *vr4320:
3077 // end-sanitize-vr4320
3078 // start-sanitize-cygnus
3079 *vr5400:
3080 // end-sanitize-cygnus
3081 // start-sanitize-r5900
3082 *r5900:
3083 // end-sanitize-r5900
3084 *r3900:
3085 // start-sanitize-tx19
3086 *tx19:
3087 // end-sanitize-tx19
3088 {
3089   do_ori (SD_, RS, RT, IMMEDIATE);
3090 }
3091
3092
3093 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
3094 *mipsIV:
3095 *vr5000:
3096 // start-sanitize-vr4320
3097 *vr4320:
3098 // end-sanitize-vr4320
3099 // start-sanitize-cygnus
3100 *vr5400:
3101 // end-sanitize-cygnus
3102 // start-sanitize-r5900
3103 *r5900:
3104 // end-sanitize-r5900
3105 {
3106   unsigned32 instruction = instruction_0;
3107   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3108   int hint = ((instruction >> 16) & 0x0000001F);
3109   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3110   {
3111     address_word vaddr = ((unsigned64)op1 + offset);
3112     address_word paddr;
3113     int uncached;
3114     {
3115       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3116         Prefetch(uncached,paddr,vaddr,isDATA,hint);
3117     }
3118   }
3119 }
3120
3121 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
3122 {
3123   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3124   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
3125   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
3126   unsigned int byte;
3127   address_word paddr;
3128   int uncached;
3129   unsigned64 memval;
3130   address_word vaddr;
3131
3132   vaddr = base + offset;
3133   if ((vaddr & access) != 0)
3134     {
3135       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
3136     }
3137   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3138   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3139   byte = ((vaddr & mask) ^ bigendiancpu);
3140   memval = (word << (8 * byte));
3141   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
3142 }
3143
3144
3145 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
3146 "sb r<RT>, <OFFSET>(r<BASE>)"
3147 *mipsI,mipsII,mipsIII,mipsIV:
3148 *vr4100:
3149 *vr5000:
3150 // start-sanitize-vr4xxx
3151 *vr4121:
3152 // end-sanitize-vr4xxx
3153 // start-sanitize-vr4320
3154 *vr4320:
3155 // end-sanitize-vr4320
3156 // start-sanitize-cygnus
3157 *vr5400:
3158 // end-sanitize-cygnus
3159 // start-sanitize-r5900
3160 *r5900:
3161 // end-sanitize-r5900
3162 *r3900:
3163 // start-sanitize-tx19
3164 *tx19:
3165 // end-sanitize-tx19
3166 {
3167   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3168 }
3169
3170
3171 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
3172 "sc r<RT>, <OFFSET>(r<BASE>)"
3173 *mipsII:
3174 *mipsIII:
3175 *mipsIV:
3176 *vr4100:
3177 *vr5000:
3178 // start-sanitize-vr4xxx
3179 *vr4121:
3180 // end-sanitize-vr4xxx
3181 // start-sanitize-vr4320
3182 *vr4320:
3183 // end-sanitize-vr4320
3184 // start-sanitize-cygnus
3185 *vr5400:
3186 // end-sanitize-cygnus
3187 // start-sanitize-r5900
3188 *r5900:
3189 // end-sanitize-r5900
3190 // start-sanitize-tx19
3191 *tx19:
3192 // end-sanitize-tx19
3193 {
3194   unsigned32 instruction = instruction_0;
3195   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3196   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3197   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3198   {
3199     address_word vaddr = ((unsigned64)op1 + offset);
3200     address_word paddr;
3201     int uncached;
3202     if ((vaddr & 3) != 0)
3203       {
3204         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3205       }
3206     else
3207       {
3208         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3209           {
3210             unsigned64 memval = 0;
3211             unsigned64 memval1 = 0;
3212             unsigned64 mask = 0x7;
3213             unsigned int byte;
3214             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3215             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3216             memval = ((unsigned64) op2 << (8 * byte));
3217             if (LLBIT)
3218               {
3219                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3220               }
3221             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
3222           }
3223       }
3224   }
3225 }
3226
3227
3228 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3229 "scd r<RT>, <OFFSET>(r<BASE>)"
3230 *mipsIII:
3231 *mipsIV:
3232 *vr4100:
3233 *vr5000:
3234 // start-sanitize-vr4xxx
3235 *vr4121:
3236 // end-sanitize-vr4xxx
3237 // start-sanitize-vr4320
3238 *vr4320:
3239 // end-sanitize-vr4320
3240 // start-sanitize-cygnus
3241 *vr5400:
3242 // end-sanitize-cygnus
3243 // start-sanitize-r5900
3244 *r5900:
3245 // end-sanitize-r5900
3246 // start-sanitize-tx19
3247 *tx19:
3248 // end-sanitize-tx19
3249 {
3250   unsigned32 instruction = instruction_0;
3251   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3252   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3253   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3254   {
3255     address_word vaddr = ((unsigned64)op1 + offset);
3256     address_word paddr;
3257     int uncached;
3258     if ((vaddr & 7) != 0)
3259       {
3260         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3261       }
3262     else
3263       {
3264         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3265           {
3266             unsigned64 memval = 0;
3267             unsigned64 memval1 = 0;
3268             memval = op2;
3269             if (LLBIT)
3270               {
3271                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3272               }
3273             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
3274           }
3275       }
3276   }
3277 }
3278
3279
3280 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3281 "sd r<RT>, <OFFSET>(r<BASE>)"
3282 *mipsIII:
3283 *mipsIV:
3284 *vr4100:
3285 *vr5000:
3286 // start-sanitize-vr4xxx
3287 *vr4121:
3288 // end-sanitize-vr4xxx
3289 // start-sanitize-vr4320
3290 *vr4320:
3291 // end-sanitize-vr4320
3292 // start-sanitize-cygnus
3293 *vr5400:
3294 // end-sanitize-cygnus
3295 // start-sanitize-r5900
3296 *r5900:
3297 // end-sanitize-r5900
3298 // start-sanitize-tx19
3299 *tx19:
3300 // end-sanitize-tx19
3301 {
3302   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3303 }
3304
3305
3306 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3307 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3308 *mipsII:
3309 *mipsIII:
3310 *mipsIV:
3311 *vr4100:
3312 *vr5000:
3313 // start-sanitize-vr4xxx
3314 *vr4121:
3315 // end-sanitize-vr4xxx
3316 // start-sanitize-vr4320
3317 *vr4320:
3318 // end-sanitize-vr4320
3319 // start-sanitize-cygnus
3320 *vr5400:
3321 // end-sanitize-cygnus
3322 // start-sanitize-tx19
3323 *tx19:
3324 // end-sanitize-tx19
3325 {
3326   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3327 }
3328
3329
3330 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3331 "sdl r<RT>, <OFFSET>(r<BASE>)"
3332 *mipsIII:
3333 *mipsIV:
3334 *vr4100:
3335 *vr5000:
3336 // start-sanitize-vr4xxx
3337 *vr4121:
3338 // end-sanitize-vr4xxx
3339 // start-sanitize-vr4320
3340 *vr4320:
3341 // end-sanitize-vr4320
3342 // start-sanitize-cygnus
3343 *vr5400:
3344 // end-sanitize-cygnus
3345 // start-sanitize-r5900
3346 *r5900:
3347 // end-sanitize-r5900
3348 // start-sanitize-tx19
3349 *tx19:
3350 // end-sanitize-tx19
3351 {
3352   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3353 }
3354
3355
3356 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3357 "sdr r<RT>, <OFFSET>(r<BASE>)"
3358 *mipsIII:
3359 *mipsIV:
3360 *vr4100:
3361 *vr5000:
3362 // start-sanitize-vr4xxx
3363 *vr4121:
3364 // end-sanitize-vr4xxx
3365 // start-sanitize-vr4320
3366 *vr4320:
3367 // end-sanitize-vr4320
3368 // start-sanitize-cygnus
3369 *vr5400:
3370 // end-sanitize-cygnus
3371 // start-sanitize-r5900
3372 *r5900:
3373 // end-sanitize-r5900
3374 // start-sanitize-tx19
3375 *tx19:
3376 // end-sanitize-tx19
3377 {
3378   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3379 }
3380
3381
3382 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3383 "sh r<RT>, <OFFSET>(r<BASE>)"
3384 *mipsI,mipsII,mipsIII,mipsIV:
3385 *vr4100:
3386 *vr5000:
3387 // start-sanitize-vr4xxx
3388 *vr4121:
3389 // end-sanitize-vr4xxx
3390 // start-sanitize-vr4320
3391 *vr4320:
3392 // end-sanitize-vr4320
3393 // start-sanitize-cygnus
3394 *vr5400:
3395 // end-sanitize-cygnus
3396 // start-sanitize-r5900
3397 *r5900:
3398 // end-sanitize-r5900
3399 *r3900:
3400 // start-sanitize-tx19
3401 *tx19:
3402 // end-sanitize-tx19
3403 {
3404   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3405 }
3406
3407
3408 :function:::void:do_sll:int rt, int rd, int shift
3409 {
3410   unsigned32 temp = (GPR[rt] << shift);
3411   TRACE_ALU_INPUT2 (GPR[rt], shift);
3412   GPR[rd] = EXTEND32 (temp);
3413   TRACE_ALU_RESULT (GPR[rd]);
3414 }
3415
3416 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
3417 "sll r<RD>, r<RT>, <SHIFT>"
3418 *mipsI,mipsII,mipsIII,mipsIV:
3419 *vr4100:
3420 *vr5000:
3421 // start-sanitize-vr4xxx
3422 *vr4121:
3423 // end-sanitize-vr4xxx
3424 // start-sanitize-vr4320
3425 *vr4320:
3426 // end-sanitize-vr4320
3427 // start-sanitize-cygnus
3428 *vr5400:
3429 // end-sanitize-cygnus
3430 // start-sanitize-r5900
3431 *r5900:
3432 // end-sanitize-r5900
3433 *r3900:
3434 // start-sanitize-tx19
3435 *tx19:
3436 // end-sanitize-tx19
3437 {
3438   do_sll (SD_, RT, RD, SHIFT);
3439 }
3440
3441
3442 :function:::void:do_sllv:int rs, int rt, int rd
3443 {
3444   int s = MASKED (GPR[rs], 4, 0);
3445   unsigned32 temp = (GPR[rt] << s);
3446   TRACE_ALU_INPUT2 (GPR[rt], s);
3447   GPR[rd] = EXTEND32 (temp);
3448   TRACE_ALU_RESULT (GPR[rd]);
3449 }
3450
3451 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
3452 "sllv r<RD>, r<RT>, r<RS>"
3453 *mipsI,mipsII,mipsIII,mipsIV:
3454 *vr4100:
3455 *vr5000:
3456 // start-sanitize-vr4xxx
3457 *vr4121:
3458 // end-sanitize-vr4xxx
3459 // start-sanitize-vr4320
3460 *vr4320:
3461 // end-sanitize-vr4320
3462 // start-sanitize-cygnus
3463 *vr5400:
3464 // end-sanitize-cygnus
3465 // start-sanitize-r5900
3466 *r5900:
3467 // end-sanitize-r5900
3468 *r3900:
3469 // start-sanitize-tx19
3470 *tx19:
3471 // end-sanitize-tx19
3472 {
3473   do_sllv (SD_, RS, RT, RD);
3474 }
3475
3476
3477 :function:::void:do_slt:int rs, int rt, int rd
3478 {
3479   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3480   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3481   TRACE_ALU_RESULT (GPR[rd]);
3482 }
3483
3484 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
3485 "slt r<RD>, r<RS>, r<RT>"
3486 *mipsI,mipsII,mipsIII,mipsIV:
3487 *vr4100:
3488 *vr5000:
3489 // start-sanitize-vr4xxx
3490 *vr4121:
3491 // end-sanitize-vr4xxx
3492 // start-sanitize-vr4320
3493 *vr4320:
3494 // end-sanitize-vr4320
3495 // start-sanitize-cygnus
3496 *vr5400:
3497 // end-sanitize-cygnus
3498 // start-sanitize-r5900
3499 *r5900:
3500 // end-sanitize-r5900
3501 *r3900:
3502 // start-sanitize-tx19
3503 *tx19:
3504 // end-sanitize-tx19
3505 {
3506   do_slt (SD_, RS, RT, RD);
3507 }
3508
3509
3510 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3511 {
3512   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3513   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3514   TRACE_ALU_RESULT (GPR[rt]);
3515 }
3516
3517 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3518 "slti r<RT>, r<RS>, <IMMEDIATE>"
3519 *mipsI,mipsII,mipsIII,mipsIV:
3520 *vr4100:
3521 *vr5000:
3522 // start-sanitize-vr4xxx
3523 *vr4121:
3524 // end-sanitize-vr4xxx
3525 // start-sanitize-vr4320
3526 *vr4320:
3527 // end-sanitize-vr4320
3528 // start-sanitize-cygnus
3529 *vr5400:
3530 // end-sanitize-cygnus
3531 // start-sanitize-r5900
3532 *r5900:
3533 // end-sanitize-r5900
3534 *r3900:
3535 // start-sanitize-tx19
3536 *tx19:
3537 // end-sanitize-tx19
3538 {
3539   do_slti (SD_, RS, RT, IMMEDIATE);
3540 }
3541
3542
3543 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3544 {
3545   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3546   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3547   TRACE_ALU_RESULT (GPR[rt]);
3548 }
3549
3550 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3551 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3552 *mipsI,mipsII,mipsIII,mipsIV:
3553 *vr4100:
3554 *vr5000:
3555 // start-sanitize-vr4xxx
3556 *vr4121:
3557 // end-sanitize-vr4xxx
3558 // start-sanitize-vr4320
3559 *vr4320:
3560 // end-sanitize-vr4320
3561 // start-sanitize-cygnus
3562 *vr5400:
3563 // end-sanitize-cygnus
3564 // start-sanitize-r5900
3565 *r5900:
3566 // end-sanitize-r5900
3567 *r3900:
3568 // start-sanitize-tx19
3569 *tx19:
3570 // end-sanitize-tx19
3571 {
3572   do_sltiu (SD_, RS, RT, IMMEDIATE);
3573 }
3574
3575
3576
3577 :function:::void:do_sltu:int rs, int rt, int rd
3578 {
3579   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3580   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3581   TRACE_ALU_RESULT (GPR[rd]);
3582 }
3583
3584 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3585 "sltu r<RD>, r<RS>, r<RT>"
3586 *mipsI,mipsII,mipsIII,mipsIV:
3587 *vr4100:
3588 *vr5000:
3589 // start-sanitize-vr4xxx
3590 *vr4121:
3591 // end-sanitize-vr4xxx
3592 // start-sanitize-vr4320
3593 *vr4320:
3594 // end-sanitize-vr4320
3595 // start-sanitize-cygnus
3596 *vr5400:
3597 // end-sanitize-cygnus
3598 // start-sanitize-r5900
3599 *r5900:
3600 // end-sanitize-r5900
3601 *r3900:
3602 // start-sanitize-tx19
3603 *tx19:
3604 // end-sanitize-tx19
3605 {
3606   do_sltu (SD_, RS, RT, RD);
3607 }
3608
3609
3610 :function:::void:do_sra:int rt, int rd, int shift
3611 {
3612   signed32 temp = (signed32) GPR[rt] >> shift;
3613   TRACE_ALU_INPUT2 (GPR[rt], shift);
3614   GPR[rd] = EXTEND32 (temp);
3615   TRACE_ALU_RESULT (GPR[rd]);
3616 }
3617
3618 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3619 "sra r<RD>, r<RT>, <SHIFT>"
3620 *mipsI,mipsII,mipsIII,mipsIV:
3621 *vr4100:
3622 *vr5000:
3623 // start-sanitize-vr4xxx
3624 *vr4121:
3625 // end-sanitize-vr4xxx
3626 // start-sanitize-vr4320
3627 *vr4320:
3628 // end-sanitize-vr4320
3629 // start-sanitize-cygnus
3630 *vr5400:
3631 // end-sanitize-cygnus
3632 // start-sanitize-r5900
3633 *r5900:
3634 // end-sanitize-r5900
3635 *r3900:
3636 // start-sanitize-tx19
3637 *tx19:
3638 // end-sanitize-tx19
3639 {
3640   do_sra (SD_, RT, RD, SHIFT);
3641 }
3642
3643
3644
3645 :function:::void:do_srav:int rs, int rt, int rd
3646 {
3647   int s = MASKED (GPR[rs], 4, 0);
3648   signed32 temp = (signed32) GPR[rt] >> s;
3649   TRACE_ALU_INPUT2 (GPR[rt], s);
3650   GPR[rd] = EXTEND32 (temp);
3651   TRACE_ALU_RESULT (GPR[rd]);
3652 }
3653
3654 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3655 "srav r<RD>, r<RT>, r<RS>"
3656 *mipsI,mipsII,mipsIII,mipsIV:
3657 *vr4100:
3658 *vr5000:
3659 // start-sanitize-vr4xxx
3660 *vr4121:
3661 // end-sanitize-vr4xxx
3662 // start-sanitize-vr4320
3663 *vr4320:
3664 // end-sanitize-vr4320
3665 // start-sanitize-cygnus
3666 *vr5400:
3667 // end-sanitize-cygnus
3668 // start-sanitize-r5900
3669 *r5900:
3670 // end-sanitize-r5900
3671 *r3900:
3672 // start-sanitize-tx19
3673 *tx19:
3674 // end-sanitize-tx19
3675 {
3676   do_srav (SD_, RS, RT, RD);
3677 }
3678
3679
3680
3681 :function:::void:do_srl:int rt, int rd, int shift
3682 {
3683   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3684   TRACE_ALU_INPUT2 (GPR[rt], shift);
3685   GPR[rd] = EXTEND32 (temp);
3686   TRACE_ALU_RESULT (GPR[rd]);
3687 }
3688
3689 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3690 "srl r<RD>, r<RT>, <SHIFT>"
3691 *mipsI,mipsII,mipsIII,mipsIV:
3692 *vr4100:
3693 *vr5000:
3694 // start-sanitize-vr4xxx
3695 *vr4121:
3696 // end-sanitize-vr4xxx
3697 // start-sanitize-vr4320
3698 *vr4320:
3699 // end-sanitize-vr4320
3700 // start-sanitize-cygnus
3701 *vr5400:
3702 // end-sanitize-cygnus
3703 // start-sanitize-r5900
3704 *r5900:
3705 // end-sanitize-r5900
3706 *r3900:
3707 // start-sanitize-tx19
3708 *tx19:
3709 // end-sanitize-tx19
3710 {
3711   do_srl (SD_, RT, RD, SHIFT);
3712 }
3713
3714
3715 :function:::void:do_srlv:int rs, int rt, int rd
3716 {
3717   int s = MASKED (GPR[rs], 4, 0);
3718   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3719   TRACE_ALU_INPUT2 (GPR[rt], s);
3720   GPR[rd] = EXTEND32 (temp);
3721   TRACE_ALU_RESULT (GPR[rd]);
3722 }
3723
3724 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3725 "srlv r<RD>, r<RT>, r<RS>"
3726 *mipsI,mipsII,mipsIII,mipsIV:
3727 *vr4100:
3728 *vr5000:
3729 // start-sanitize-vr4xxx
3730 *vr4121:
3731 // end-sanitize-vr4xxx
3732 // start-sanitize-vr4320
3733 *vr4320:
3734 // end-sanitize-vr4320
3735 // start-sanitize-cygnus
3736 *vr5400:
3737 // end-sanitize-cygnus
3738 // start-sanitize-r5900
3739 *r5900:
3740 // end-sanitize-r5900
3741 *r3900:
3742 // start-sanitize-tx19
3743 *tx19:
3744 // end-sanitize-tx19
3745 {
3746   do_srlv (SD_, RS, RT, RD);
3747 }
3748
3749
3750 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3751 "sub r<RD>, r<RS>, r<RT>"
3752 *mipsI,mipsII,mipsIII,mipsIV:
3753 *vr4100:
3754 *vr5000:
3755 // start-sanitize-vr4xxx
3756 *vr4121:
3757 // end-sanitize-vr4xxx
3758 // start-sanitize-vr4320
3759 *vr4320:
3760 // end-sanitize-vr4320
3761 // start-sanitize-cygnus
3762 *vr5400:
3763 // end-sanitize-cygnus
3764 // start-sanitize-r5900
3765 *r5900:
3766 // end-sanitize-r5900
3767 *r3900:
3768 // start-sanitize-tx19
3769 *tx19:
3770 // end-sanitize-tx19
3771 {
3772   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3773   {
3774     ALU32_BEGIN (GPR[RS]);
3775     ALU32_SUB (GPR[RT]);
3776     ALU32_END (GPR[RD]);
3777   }
3778   TRACE_ALU_RESULT (GPR[RD]);
3779 }
3780
3781
3782 :function:::void:do_subu:int rs, int rt, int rd
3783 {
3784   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3785   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3786   TRACE_ALU_RESULT (GPR[rd]);
3787 }
3788
3789 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3790 "subu r<RD>, r<RS>, r<RT>"
3791 *mipsI,mipsII,mipsIII,mipsIV:
3792 *vr4100:
3793 *vr5000:
3794 // start-sanitize-vr4xxx
3795 *vr4121:
3796 // end-sanitize-vr4xxx
3797 // start-sanitize-vr4320
3798 *vr4320:
3799 // end-sanitize-vr4320
3800 // start-sanitize-cygnus
3801 *vr5400:
3802 // end-sanitize-cygnus
3803 // start-sanitize-r5900
3804 *r5900:
3805 // end-sanitize-r5900
3806 *r3900:
3807 // start-sanitize-tx19
3808 *tx19:
3809 // end-sanitize-tx19
3810 {
3811   do_subu (SD_, RS, RT, RD);
3812 }
3813
3814
3815 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3816 "sw r<RT>, <OFFSET>(r<BASE>)"
3817 *mipsI,mipsII,mipsIII,mipsIV:
3818 *vr4100:
3819 // start-sanitize-vr4xxx
3820 *vr4121:
3821 // end-sanitize-vr4xxx
3822 // start-sanitize-tx19
3823 *tx19:
3824 // end-sanitize-tx19
3825 *r3900:
3826 // start-sanitize-vr4320
3827 *vr4320:
3828 // end-sanitize-vr4320
3829 *vr5000:
3830 // start-sanitize-cygnus
3831 *vr5400:
3832 // end-sanitize-cygnus
3833 // start-sanitize-r5900
3834 *r5900:
3835 // end-sanitize-r5900
3836 {
3837   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3838 }
3839
3840
3841 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3842 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3843 *mipsI,mipsII,mipsIII,mipsIV:
3844 *vr4100:
3845 *vr5000:
3846 // start-sanitize-vr4xxx
3847 *vr4121:
3848 // end-sanitize-vr4xxx
3849 // start-sanitize-vr4320
3850 *vr4320:
3851 // end-sanitize-vr4320
3852 // start-sanitize-cygnus
3853 *vr5400:
3854 // end-sanitize-cygnus
3855 *r3900:
3856 // start-sanitize-tx19
3857 *tx19:
3858 // end-sanitize-tx19
3859 {
3860   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3861 }
3862
3863
3864
3865 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3866 {
3867   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3868   address_word reverseendian = (ReverseEndian ? -1 : 0);
3869   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3870   unsigned int byte;
3871   unsigned int word;
3872   address_word paddr;
3873   int uncached;
3874   unsigned64 memval;
3875   address_word vaddr;
3876   int nr_lhs_bits;
3877   int nr_rhs_bits;
3878
3879   vaddr = base + offset;
3880   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3881   paddr = (paddr ^ (reverseendian & mask));
3882   if (BigEndianMem == 0)
3883     paddr = paddr & ~access;
3884
3885   /* compute where within the word/mem we are */
3886   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3887   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3888   nr_lhs_bits = 8 * byte + 8;
3889   nr_rhs_bits = 8 * access - 8 * byte;
3890   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3891   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3892            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3893            (long) ((unsigned64) paddr >> 32), (long) paddr,
3894            word, byte, nr_lhs_bits, nr_rhs_bits); */
3895
3896   if (word == 0)
3897     {
3898       memval = (rt >> nr_rhs_bits);
3899     }
3900   else
3901     {
3902       memval = (rt << nr_lhs_bits);
3903     }
3904   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3905            (long) ((unsigned64) rt >> 32), (long) rt,
3906            (long) ((unsigned64) memval >> 32), (long) memval); */
3907   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3908 }
3909
3910
3911 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3912 "swl r<RT>, <OFFSET>(r<BASE>)"
3913 *mipsI,mipsII,mipsIII,mipsIV:
3914 *vr4100:
3915 *vr5000:
3916 // start-sanitize-vr4xxx
3917 *vr4121:
3918 // end-sanitize-vr4xxx
3919 // start-sanitize-vr4320
3920 *vr4320:
3921 // end-sanitize-vr4320
3922 // start-sanitize-cygnus
3923 *vr5400:
3924 // end-sanitize-cygnus
3925 // start-sanitize-r5900
3926 *r5900:
3927 // end-sanitize-r5900
3928 *r3900:
3929 // start-sanitize-tx19
3930 *tx19:
3931 // end-sanitize-tx19
3932 {
3933   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3934 }
3935
3936
3937 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3938 {
3939   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3940   address_word reverseendian = (ReverseEndian ? -1 : 0);
3941   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3942   unsigned int byte;
3943   address_word paddr;
3944   int uncached;
3945   unsigned64 memval;
3946   address_word vaddr;
3947
3948   vaddr = base + offset;
3949   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3950   paddr = (paddr ^ (reverseendian & mask));
3951   if (BigEndianMem != 0)
3952     paddr &= ~access;
3953   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3954   memval = (rt << (byte * 8));
3955   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3956 }
3957
3958 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3959 "swr r<RT>, <OFFSET>(r<BASE>)"
3960 *mipsI,mipsII,mipsIII,mipsIV:
3961 *vr4100:
3962 *vr5000:
3963 // start-sanitize-vr4xxx
3964 *vr4121:
3965 // end-sanitize-vr4xxx
3966 // start-sanitize-vr4320
3967 *vr4320:
3968 // end-sanitize-vr4320
3969 // start-sanitize-cygnus
3970 *vr5400:
3971 // end-sanitize-cygnus
3972 // start-sanitize-r5900
3973 *r5900:
3974 // end-sanitize-r5900
3975 *r3900:
3976 // start-sanitize-tx19
3977 *tx19:
3978 // end-sanitize-tx19
3979 {
3980   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3981 }
3982
3983
3984 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3985 "sync":STYPE == 0
3986 "sync <STYPE>"
3987 *mipsII:
3988 *mipsIII:
3989 *mipsIV:
3990 *vr4100:
3991 *vr5000:
3992 // start-sanitize-vr4xxx
3993 *vr4121:
3994 // end-sanitize-vr4xxx
3995 // start-sanitize-vr4320
3996 *vr4320:
3997 // end-sanitize-vr4320
3998 // start-sanitize-cygnus
3999 *vr5400:
4000 // end-sanitize-cygnus
4001 // start-sanitize-r5900
4002 *r5900:
4003 // end-sanitize-r5900
4004 *r3900:
4005 // start-sanitize-tx19
4006 *tx19:
4007 // end-sanitize-tx19
4008 {
4009   SyncOperation (STYPE);
4010 }
4011
4012
4013 000000,20.CODE,001100:SPECIAL:32::SYSCALL
4014 "syscall <CODE>"
4015 *mipsI,mipsII,mipsIII,mipsIV:
4016 *vr4100:
4017 *vr5000:
4018 // start-sanitize-vr4xxx
4019 *vr4121:
4020 // end-sanitize-vr4xxx
4021 // start-sanitize-vr4320
4022 *vr4320:
4023 // end-sanitize-vr4320
4024 // start-sanitize-cygnus
4025 *vr5400:
4026 // end-sanitize-cygnus
4027 // start-sanitize-r5900
4028 *r5900:
4029 // end-sanitize-r5900
4030 *r3900:
4031 // start-sanitize-tx19
4032 *tx19:
4033 // end-sanitize-tx19
4034 {
4035   SignalException(SystemCall, instruction_0);
4036 }
4037
4038
4039 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
4040 "teq r<RS>, r<RT>"
4041 *mipsII:
4042 *mipsIII:
4043 *mipsIV:
4044 *vr4100:
4045 *vr5000:
4046 // start-sanitize-vr4xxx
4047 *vr4121:
4048 // end-sanitize-vr4xxx
4049 // start-sanitize-vr4320
4050 *vr4320:
4051 // end-sanitize-vr4320
4052 // start-sanitize-cygnus
4053 *vr5400:
4054 // end-sanitize-cygnus
4055 // start-sanitize-r5900
4056 *r5900:
4057 // end-sanitize-r5900
4058 // start-sanitize-tx19
4059 *tx19:
4060 // end-sanitize-tx19
4061 {
4062   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
4063     SignalException(Trap, instruction_0);
4064 }
4065
4066
4067 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
4068 "teqi r<RS>, <IMMEDIATE>"
4069 *mipsII:
4070 *mipsIII:
4071 *mipsIV:
4072 *vr4100:
4073 *vr5000:
4074 // start-sanitize-vr4xxx
4075 *vr4121:
4076 // end-sanitize-vr4xxx
4077 // start-sanitize-vr4320
4078 *vr4320:
4079 // end-sanitize-vr4320
4080 // start-sanitize-cygnus
4081 *vr5400:
4082 // end-sanitize-cygnus
4083 // start-sanitize-r5900
4084 *r5900:
4085 // end-sanitize-r5900
4086 // start-sanitize-tx19
4087 *tx19:
4088 // end-sanitize-tx19
4089 {
4090   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
4091     SignalException(Trap, instruction_0);
4092 }
4093
4094
4095 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
4096 "tge r<RS>, r<RT>"
4097 *mipsII:
4098 *mipsIII:
4099 *mipsIV:
4100 *vr4100:
4101 *vr5000:
4102 // start-sanitize-vr4xxx
4103 *vr4121:
4104 // end-sanitize-vr4xxx
4105 // start-sanitize-vr4320
4106 *vr4320:
4107 // end-sanitize-vr4320
4108 // start-sanitize-cygnus
4109 *vr5400:
4110 // end-sanitize-cygnus
4111 // start-sanitize-r5900
4112 *r5900:
4113 // end-sanitize-r5900
4114 // start-sanitize-tx19
4115 *tx19:
4116 // end-sanitize-tx19
4117 {
4118   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
4119     SignalException(Trap, instruction_0);
4120 }
4121
4122
4123 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
4124 "tgei r<RS>, <IMMEDIATE>"
4125 *mipsII:
4126 *mipsIII:
4127 *mipsIV:
4128 *vr4100:
4129 *vr5000:
4130 // start-sanitize-vr4xxx
4131 *vr4121:
4132 // end-sanitize-vr4xxx
4133 // start-sanitize-vr4320
4134 *vr4320:
4135 // end-sanitize-vr4320
4136 // start-sanitize-cygnus
4137 *vr5400:
4138 // end-sanitize-cygnus
4139 // start-sanitize-r5900
4140 *r5900:
4141 // end-sanitize-r5900
4142 // start-sanitize-tx19
4143 *tx19:
4144 // end-sanitize-tx19
4145 {
4146   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
4147     SignalException(Trap, instruction_0);
4148 }
4149
4150
4151 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
4152 "tgeiu r<RS>, <IMMEDIATE>"
4153 *mipsII:
4154 *mipsIII:
4155 *mipsIV:
4156 *vr4100:
4157 *vr5000:
4158 // start-sanitize-vr4xxx
4159 *vr4121:
4160 // end-sanitize-vr4xxx
4161 // start-sanitize-vr4320
4162 *vr4320:
4163 // end-sanitize-vr4320
4164 // start-sanitize-cygnus
4165 *vr5400:
4166 // end-sanitize-cygnus
4167 // start-sanitize-r5900
4168 *r5900:
4169 // end-sanitize-r5900
4170 // start-sanitize-tx19
4171 *tx19:
4172 // end-sanitize-tx19
4173 {
4174   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
4175     SignalException(Trap, instruction_0);
4176 }
4177
4178
4179 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
4180 "tgeu r<RS>, r<RT>"
4181 *mipsII:
4182 *mipsIII:
4183 *mipsIV:
4184 *vr4100:
4185 *vr5000:
4186 // start-sanitize-vr4xxx
4187 *vr4121:
4188 // end-sanitize-vr4xxx
4189 // start-sanitize-vr4320
4190 *vr4320:
4191 // end-sanitize-vr4320
4192 // start-sanitize-cygnus
4193 *vr5400:
4194 // end-sanitize-cygnus
4195 // start-sanitize-r5900
4196 *r5900:
4197 // end-sanitize-r5900
4198 // start-sanitize-tx19
4199 *tx19:
4200 // end-sanitize-tx19
4201 {
4202   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
4203     SignalException(Trap, instruction_0);
4204 }
4205
4206
4207 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
4208 "tlt r<RS>, r<RT>"
4209 *mipsII:
4210 *mipsIII:
4211 *mipsIV:
4212 *vr4100:
4213 *vr5000:
4214 // start-sanitize-vr4xxx
4215 *vr4121:
4216 // end-sanitize-vr4xxx
4217 // start-sanitize-vr4320
4218 *vr4320:
4219 // end-sanitize-vr4320
4220 // start-sanitize-cygnus
4221 *vr5400:
4222 // end-sanitize-cygnus
4223 // start-sanitize-r5900
4224 *r5900:
4225 // end-sanitize-r5900
4226 // start-sanitize-tx19
4227 *tx19:
4228 // end-sanitize-tx19
4229 {
4230   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
4231     SignalException(Trap, instruction_0);
4232 }
4233
4234
4235 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
4236 "tlti r<RS>, <IMMEDIATE>"
4237 *mipsII:
4238 *mipsIII:
4239 *mipsIV:
4240 *vr4100:
4241 *vr5000:
4242 // start-sanitize-vr4xxx
4243 *vr4121:
4244 // end-sanitize-vr4xxx
4245 // start-sanitize-vr4320
4246 *vr4320:
4247 // end-sanitize-vr4320
4248 // start-sanitize-cygnus
4249 *vr5400:
4250 // end-sanitize-cygnus
4251 // start-sanitize-r5900
4252 *r5900:
4253 // end-sanitize-r5900
4254 // start-sanitize-tx19
4255 *tx19:
4256 // end-sanitize-tx19
4257 {
4258   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
4259     SignalException(Trap, instruction_0);
4260 }
4261
4262
4263 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
4264 "tltiu r<RS>, <IMMEDIATE>"
4265 *mipsII:
4266 *mipsIII:
4267 *mipsIV:
4268 *vr4100:
4269 *vr5000:
4270 // start-sanitize-vr4xxx
4271 *vr4121:
4272 // end-sanitize-vr4xxx
4273 // start-sanitize-vr4320
4274 *vr4320:
4275 // end-sanitize-vr4320
4276 // start-sanitize-cygnus
4277 *vr5400:
4278 // end-sanitize-cygnus
4279 // start-sanitize-r5900
4280 *r5900:
4281 // end-sanitize-r5900
4282 // start-sanitize-tx19
4283 *tx19:
4284 // end-sanitize-tx19
4285 {
4286   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
4287     SignalException(Trap, instruction_0);
4288 }
4289
4290
4291 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
4292 "tltu r<RS>, r<RT>"
4293 *mipsII:
4294 *mipsIII:
4295 *mipsIV:
4296 *vr4100:
4297 *vr5000:
4298 // start-sanitize-vr4xxx
4299 *vr4121:
4300 // end-sanitize-vr4xxx
4301 // start-sanitize-vr4320
4302 *vr4320:
4303 // end-sanitize-vr4320
4304 // start-sanitize-cygnus
4305 *vr5400:
4306 // end-sanitize-cygnus
4307 // start-sanitize-r5900
4308 *r5900:
4309 // end-sanitize-r5900
4310 // start-sanitize-tx19
4311 *tx19:
4312 // end-sanitize-tx19
4313 {
4314   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
4315     SignalException(Trap, instruction_0);
4316 }
4317
4318
4319 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
4320 "tne r<RS>, r<RT>"
4321 *mipsII:
4322 *mipsIII:
4323 *mipsIV:
4324 *vr4100:
4325 *vr5000:
4326 // start-sanitize-vr4xxx
4327 *vr4121:
4328 // end-sanitize-vr4xxx
4329 // start-sanitize-vr4320
4330 *vr4320:
4331 // end-sanitize-vr4320
4332 // start-sanitize-cygnus
4333 *vr5400:
4334 // end-sanitize-cygnus
4335 // start-sanitize-r5900
4336 *r5900:
4337 // end-sanitize-r5900
4338 // start-sanitize-tx19
4339 *tx19:
4340 // end-sanitize-tx19
4341 {
4342   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
4343     SignalException(Trap, instruction_0);
4344 }
4345
4346
4347 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
4348 "tne r<RS>, <IMMEDIATE>"
4349 *mipsII:
4350 *mipsIII:
4351 *mipsIV:
4352 *vr4100:
4353 *vr5000:
4354 // start-sanitize-vr4xxx
4355 *vr4121:
4356 // end-sanitize-vr4xxx
4357 // start-sanitize-vr4320
4358 *vr4320:
4359 // end-sanitize-vr4320
4360 // start-sanitize-cygnus
4361 *vr5400:
4362 // end-sanitize-cygnus
4363 // start-sanitize-r5900
4364 *r5900:
4365 // end-sanitize-r5900
4366 // start-sanitize-tx19
4367 *tx19:
4368 // end-sanitize-tx19
4369 {
4370   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
4371     SignalException(Trap, instruction_0);
4372 }
4373
4374
4375 :function:::void:do_xor:int rs, int rt, int rd
4376 {
4377   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4378   GPR[rd] = GPR[rs] ^ GPR[rt];
4379   TRACE_ALU_RESULT (GPR[rd]);
4380 }
4381
4382 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
4383 "xor r<RD>, r<RS>, r<RT>"
4384 *mipsI,mipsII,mipsIII,mipsIV:
4385 *vr4100:
4386 *vr5000:
4387 // start-sanitize-vr4xxx
4388 *vr4121:
4389 // end-sanitize-vr4xxx
4390 // start-sanitize-vr4320
4391 *vr4320:
4392 // end-sanitize-vr4320
4393 // start-sanitize-cygnus
4394 *vr5400:
4395 // end-sanitize-cygnus
4396 // start-sanitize-r5900
4397 *r5900:
4398 // end-sanitize-r5900
4399 *r3900:
4400 // start-sanitize-tx19
4401 *tx19:
4402 // end-sanitize-tx19
4403 {
4404   do_xor (SD_, RS, RT, RD);
4405 }
4406
4407
4408 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
4409 {
4410   TRACE_ALU_INPUT2 (GPR[rs], immediate);
4411   GPR[rt] = GPR[rs] ^ immediate;
4412   TRACE_ALU_RESULT (GPR[rt]);
4413 }
4414
4415 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
4416 "xori r<RT>, r<RS>, <IMMEDIATE>"
4417 *mipsI,mipsII,mipsIII,mipsIV:
4418 *vr4100:
4419 *vr5000:
4420 // start-sanitize-vr4xxx
4421 *vr4121:
4422 // end-sanitize-vr4xxx
4423 // start-sanitize-vr4320
4424 *vr4320:
4425 // end-sanitize-vr4320
4426 // start-sanitize-cygnus
4427 *vr5400:
4428 // end-sanitize-cygnus
4429 // start-sanitize-r5900
4430 *r5900:
4431 // end-sanitize-r5900
4432 *r3900:
4433 // start-sanitize-tx19
4434 *tx19:
4435 // end-sanitize-tx19
4436 {
4437   do_xori (SD_, RS, RT, IMMEDIATE);
4438 }
4439
4440 \f
4441 //
4442 // MIPS Architecture:
4443 //
4444 //        FPU Instruction Set (COP1 & COP1X)
4445 //
4446
4447
4448 :%s::::FMT:int fmt
4449 {
4450   switch (fmt)
4451     {
4452     case fmt_single: return "s";
4453     case fmt_double: return "d";
4454     case fmt_word: return "w";
4455     case fmt_long: return "l";
4456     default: return "?";
4457     }
4458 }
4459
4460 :%s::::X:int x
4461 {
4462   switch (x)
4463     {
4464     case 0: return "f";
4465     case 1: return "t";
4466     default: return "?";
4467     }
4468 }
4469
4470 :%s::::TF:int tf
4471 {
4472   if (tf)
4473     return "t";
4474   else
4475     return "f";
4476 }
4477
4478 :%s::::ND:int nd
4479 {
4480   if (nd)
4481     return "l";
4482   else
4483     return "";
4484 }
4485
4486 :%s::::COND:int cond
4487 {
4488   switch (cond)
4489     {
4490     case 00: return "f";
4491     case 01: return "un";
4492     case 02: return "eq";
4493     case 03: return "ueq";
4494     case 04: return "olt";
4495     case 05: return "ult";
4496     case 06: return "ole";
4497     case 07: return "ule";
4498     case 010: return "sf";
4499     case 011: return "ngle";
4500     case 012: return "seq";
4501     case 013: return "ngl";
4502     case 014: return "lt";
4503     case 015: return "nge";
4504     case 016: return "le";
4505     case 017: return "ngt";
4506     default: return "?";
4507     }
4508 }
4509
4510
4511 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4512 "abs.%s<FMT> f<FD>, f<FS>"
4513 *mipsI,mipsII,mipsIII,mipsIV:
4514 *vr4100:
4515 *vr5000:
4516 // start-sanitize-vr4xxx
4517 *vr4121:
4518 // end-sanitize-vr4xxx
4519 // start-sanitize-vr4320
4520 *vr4320:
4521 // end-sanitize-vr4320
4522 // start-sanitize-cygnus
4523 *vr5400:
4524 // end-sanitize-cygnus
4525 *r3900:
4526 // start-sanitize-tx19
4527 *tx19:
4528 // end-sanitize-tx19
4529 {
4530   unsigned32 instruction = instruction_0;
4531   int destreg = ((instruction >> 6) & 0x0000001F);
4532   int fs = ((instruction >> 11) & 0x0000001F);
4533   int format = ((instruction >> 21) & 0x00000007);
4534   {
4535     if ((format != fmt_single) && (format != fmt_double))
4536       SignalException(ReservedInstruction,instruction);
4537     else
4538       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
4539   }
4540 }
4541
4542
4543
4544 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4545 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4546 *mipsI,mipsII,mipsIII,mipsIV:
4547 *vr4100:
4548 *vr5000:
4549 // start-sanitize-vr4xxx
4550 *vr4121:
4551 // end-sanitize-vr4xxx
4552 // start-sanitize-vr4320
4553 *vr4320:
4554 // end-sanitize-vr4320
4555 // start-sanitize-cygnus
4556 *vr5400:
4557 // end-sanitize-cygnus
4558 *r3900:
4559 // start-sanitize-tx19
4560 *tx19:
4561 // end-sanitize-tx19
4562 {
4563   unsigned32 instruction = instruction_0;
4564   int destreg = ((instruction >> 6) & 0x0000001F);
4565   int fs = ((instruction >> 11) & 0x0000001F);
4566   int ft = ((instruction >> 16) & 0x0000001F);
4567   int format = ((instruction >> 21) & 0x00000007);
4568   {
4569     if ((format != fmt_single) && (format != fmt_double))
4570       SignalException(ReservedInstruction, instruction);
4571     else
4572       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
4573   }
4574 }
4575
4576
4577
4578 // BC1F
4579 // BC1FL
4580 // BC1T
4581 // BC1TL
4582
4583 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4584 "bc1%s<TF>%s<ND> <OFFSET>"
4585 *mipsI,mipsII,mipsIII:
4586 // start-sanitize-r5900
4587 *r5900:
4588 // end-sanitize-r5900
4589 {
4590   check_branch_bug ();
4591   TRACE_BRANCH_INPUT (PREVCOC1());
4592   if (PREVCOC1() == TF)
4593     {
4594       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4595       TRACE_BRANCH_RESULT (dest);
4596       mark_branch_bug (dest);
4597       DELAY_SLOT (dest);
4598     }
4599   else if (ND)
4600     {
4601       TRACE_BRANCH_RESULT (0);
4602       NULLIFY_NEXT_INSTRUCTION ();
4603     }
4604   else
4605     {
4606       TRACE_BRANCH_RESULT (NIA);
4607     }
4608 }
4609
4610 // start-sanitize-vr4xxx
4611 // FIXME: vr4100,vr4320, and 4121 all should be in the
4612 // previous insn, but the renameing thing wasn't working
4613 // so I cheated -gavin
4614 // end-sanitize-vr4xxx
4615 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4616 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4617 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4618 *mipsIV:
4619 *vr5000:
4620 #*vr4100:
4621 // start-sanitize-vr4320
4622 //*vr4320:
4623 // end-sanitize-vr4320
4624 // start-sanitize-vr4xxx
4625 *vr4121:
4626 // end-sanitize-vr4xxx
4627 // start-sanitize-cygnus
4628 *vr5400:
4629 // end-sanitize-cygnus
4630 *r3900:
4631 // start-sanitize-tx19
4632 *tx19:
4633 // end-sanitize-tx19
4634 {
4635   check_branch_bug ();
4636   if (GETFCC(CC) == TF)
4637     {
4638       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4639       mark_branch_bug (dest);
4640       DELAY_SLOT (dest);
4641     }
4642   else if (ND)
4643     {
4644       NULLIFY_NEXT_INSTRUCTION ();
4645     }
4646 }
4647
4648
4649
4650
4651
4652
4653 // C.EQ.S
4654 // C.EQ.D
4655 // ...
4656
4657 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
4658 {
4659   if ((fmt != fmt_single) && (fmt != fmt_double))
4660     SignalException (ReservedInstruction, insn);
4661   else
4662     {
4663       int less;
4664       int equal;
4665       int unordered;
4666       int condition;
4667       unsigned64 ofs = ValueFPR (fs, fmt);
4668       unsigned64 oft = ValueFPR (ft, fmt);
4669       if (NaN (ofs, fmt) || NaN (oft, fmt))
4670         {
4671           if (FCSR & FP_ENABLE (IO))
4672             {
4673               FCSR |= FP_CAUSE (IO);
4674               SignalExceptionFPE ();
4675             }
4676           less = 0;
4677           equal = 0;
4678           unordered = 1;
4679         }
4680       else
4681         {
4682           less = Less (ofs, oft, fmt);
4683           equal = Equal (ofs, oft, fmt);
4684           unordered = 0;
4685         }
4686       condition = (((cond & (1 << 2)) && less)
4687                    || ((cond & (1 << 1)) && equal)
4688                    || ((cond & (1 << 0)) && unordered));
4689       SETFCC (cc, condition);
4690     }
4691 }
4692
4693 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
4694 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4695 *mipsI,mipsII,mipsIII:
4696 {
4697   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4698 }
4699
4700 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
4701 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4702 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4703 *mipsIV:
4704 *vr4100:
4705 *vr5000:
4706 // start-sanitize-vr4xxx
4707 *vr4121:
4708 // end-sanitize-vr4xxx
4709 // start-sanitize-vr4320
4710 *vr4320:
4711 // end-sanitize-vr4320
4712 // start-sanitize-cygnus
4713 *vr5400:
4714 // end-sanitize-cygnus
4715 *r3900:
4716 // start-sanitize-tx19
4717 *tx19:
4718 // end-sanitize-tx19
4719 {
4720   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4721 }
4722
4723
4724 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4725 "ceil.l.%s<FMT> f<FD>, f<FS>"
4726 *mipsIII:
4727 *mipsIV:
4728 *vr4100:
4729 *vr5000:
4730 // start-sanitize-vr4xxx
4731 *vr4121:
4732 // end-sanitize-vr4xxx
4733 // start-sanitize-vr4320
4734 *vr4320:
4735 // end-sanitize-vr4320
4736 // start-sanitize-cygnus
4737 *vr5400:
4738 // end-sanitize-cygnus
4739 // start-sanitize-r5900
4740 *r5900:
4741 // end-sanitize-r5900
4742 *r3900:
4743 // start-sanitize-tx19
4744 *tx19:
4745 // end-sanitize-tx19
4746 {
4747   unsigned32 instruction = instruction_0;
4748   int destreg = ((instruction >> 6) & 0x0000001F);
4749   int fs = ((instruction >> 11) & 0x0000001F);
4750   int format = ((instruction >> 21) & 0x00000007);
4751   {
4752     if ((format != fmt_single) && (format != fmt_double))
4753       SignalException(ReservedInstruction,instruction);
4754     else
4755       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4756   }
4757 }
4758
4759
4760 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4761 *mipsII:
4762 *mipsIII:
4763 *mipsIV:
4764 *vr4100:
4765 *vr5000:
4766 // start-sanitize-vr4xxx
4767 *vr4121:
4768 // end-sanitize-vr4xxx
4769 // start-sanitize-vr4320
4770 *vr4320:
4771 // end-sanitize-vr4320
4772 // start-sanitize-cygnus
4773 *vr5400:
4774 // end-sanitize-cygnus
4775 // start-sanitize-r5900
4776 *r5900:
4777 // end-sanitize-r5900
4778 *r3900:
4779 // start-sanitize-tx19
4780 *tx19:
4781 // end-sanitize-tx19
4782 {
4783   unsigned32 instruction = instruction_0;
4784   int destreg = ((instruction >> 6) & 0x0000001F);
4785   int fs = ((instruction >> 11) & 0x0000001F);
4786   int format = ((instruction >> 21) & 0x00000007);
4787   {
4788   if ((format != fmt_single) && (format != fmt_double))
4789    SignalException(ReservedInstruction,instruction);
4790   else
4791    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4792   }
4793 }
4794
4795
4796 // CFC1
4797 // CTC1
4798 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
4799 "c%s<X>c1 r<RT>, f<FS>"
4800 *mipsI:
4801 *mipsII:
4802 *mipsIII:
4803 {
4804   if (X)
4805     {
4806       if (FS == 0)
4807         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4808       else if (FS == 31)
4809         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4810       /* else NOP */
4811       PENDING_FILL(COCIDX,0); /* special case */
4812     }
4813   else
4814     { /* control from */
4815       if (FS == 0)
4816         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4817       else if (FS == 31)
4818         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4819       /* else NOP */
4820     }
4821 }
4822 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
4823 "c%s<X>c1 r<RT>, f<FS>"
4824 *mipsIV:
4825 *vr4100:
4826 *vr5000:
4827 // start-sanitize-vr4xxx
4828 *vr4121:
4829 // end-sanitize-vr4xxx
4830 // start-sanitize-vr4320
4831 *vr4320:
4832 // end-sanitize-vr4320
4833 // start-sanitize-cygnus
4834 *vr5400:
4835 // end-sanitize-cygnus
4836 *r3900:
4837 // start-sanitize-tx19
4838 *tx19:
4839 // end-sanitize-tx19
4840 {
4841   if (X)
4842     {
4843       /* control to */
4844       TRACE_ALU_INPUT1 (GPR[RT]);
4845       if (FS == 0)
4846         {
4847           FCR0 = VL4_8(GPR[RT]);
4848           TRACE_ALU_RESULT (FCR0);
4849         }
4850       else if (FS == 31)
4851         {
4852           FCR31 = VL4_8(GPR[RT]);
4853           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4854           TRACE_ALU_RESULT (FCR31);
4855         }
4856       else
4857         {
4858           TRACE_ALU_RESULT0 ();
4859         }
4860       /* else NOP */
4861     }
4862   else
4863     { /* control from */
4864       if (FS == 0)
4865         {
4866           TRACE_ALU_INPUT1 (FCR0);
4867           GPR[RT] = SIGNEXTEND (FCR0, 32);
4868         }
4869       else if (FS == 31)
4870         {
4871           TRACE_ALU_INPUT1 (FCR31);
4872           GPR[RT] = SIGNEXTEND (FCR31, 32);
4873         }
4874       TRACE_ALU_RESULT (GPR[RT]);
4875       /* else NOP */
4876     }
4877 }
4878
4879
4880 //
4881 // FIXME: Does not correctly differentiate between mips*
4882 //
4883 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4884 "cvt.d.%s<FMT> f<FD>, f<FS>"
4885 *mipsI,mipsII,mipsIII,mipsIV:
4886 *vr4100:
4887 *vr5000:
4888 // start-sanitize-vr4xxx
4889 *vr4121:
4890 // end-sanitize-vr4xxx
4891 // start-sanitize-vr4320
4892 *vr4320:
4893 // end-sanitize-vr4320
4894 // start-sanitize-cygnus
4895 *vr5400:
4896 // end-sanitize-cygnus
4897 *r3900:
4898 // start-sanitize-tx19
4899 *tx19:
4900 // end-sanitize-tx19
4901 {
4902   unsigned32 instruction = instruction_0;
4903   int destreg = ((instruction >> 6) & 0x0000001F);
4904   int fs = ((instruction >> 11) & 0x0000001F);
4905   int format = ((instruction >> 21) & 0x00000007);
4906   {
4907     if ((format == fmt_double) | 0)
4908       SignalException(ReservedInstruction,instruction);
4909     else
4910       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4911   }
4912 }
4913
4914
4915 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4916 "cvt.l.%s<FMT> f<FD>, f<FS>"
4917 *mipsIII:
4918 *mipsIV:
4919 *vr4100:
4920 *vr5000:
4921 // start-sanitize-vr4xxx
4922 *vr4121:
4923 // end-sanitize-vr4xxx
4924 // start-sanitize-vr4320
4925 *vr4320:
4926 // end-sanitize-vr4320
4927 // start-sanitize-cygnus
4928 *vr5400:
4929 // end-sanitize-cygnus
4930 *r3900:
4931 // start-sanitize-tx19
4932 *tx19:
4933 // end-sanitize-tx19
4934 {
4935   unsigned32 instruction = instruction_0;
4936   int destreg = ((instruction >> 6) & 0x0000001F);
4937   int fs = ((instruction >> 11) & 0x0000001F);
4938   int format = ((instruction >> 21) & 0x00000007);
4939   {
4940     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4941       SignalException(ReservedInstruction,instruction);
4942     else
4943       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4944   }
4945 }
4946
4947
4948 //
4949 // FIXME: Does not correctly differentiate between mips*
4950 //
4951 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4952 "cvt.s.%s<FMT> f<FD>, f<FS>"
4953 *mipsI,mipsII,mipsIII,mipsIV:
4954 *vr4100:
4955 *vr5000:
4956 // start-sanitize-vr4xxx
4957 *vr4121:
4958 // end-sanitize-vr4xxx
4959 // start-sanitize-vr4320
4960 *vr4320:
4961 // end-sanitize-vr4320
4962 // start-sanitize-cygnus
4963 *vr5400:
4964 // end-sanitize-cygnus
4965 *r3900:
4966 // start-sanitize-tx19
4967 *tx19:
4968 // end-sanitize-tx19
4969 {
4970   unsigned32 instruction = instruction_0;
4971   int destreg = ((instruction >> 6) & 0x0000001F);
4972   int fs = ((instruction >> 11) & 0x0000001F);
4973   int format = ((instruction >> 21) & 0x00000007);
4974   {
4975     if ((format == fmt_single) | 0)
4976       SignalException(ReservedInstruction,instruction);
4977     else
4978       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4979   }
4980 }
4981
4982
4983 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4984 "cvt.w.%s<FMT> f<FD>, f<FS>"
4985 *mipsI,mipsII,mipsIII,mipsIV:
4986 *vr4100:
4987 *vr5000:
4988 // start-sanitize-vr4xxx
4989 *vr4121:
4990 // end-sanitize-vr4xxx
4991 // start-sanitize-vr4320
4992 *vr4320:
4993 // end-sanitize-vr4320
4994 // start-sanitize-cygnus
4995 *vr5400:
4996 // end-sanitize-cygnus
4997 *r3900:
4998 // start-sanitize-tx19
4999 *tx19:
5000 // end-sanitize-tx19
5001 {
5002   unsigned32 instruction = instruction_0;
5003   int destreg = ((instruction >> 6) & 0x0000001F);
5004   int fs = ((instruction >> 11) & 0x0000001F);
5005   int format = ((instruction >> 21) & 0x00000007);
5006   {
5007     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
5008       SignalException(ReservedInstruction,instruction);
5009     else
5010       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
5011   }
5012 }
5013
5014
5015 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
5016 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
5017 *mipsI,mipsII,mipsIII,mipsIV:
5018 *vr4100:
5019 *vr5000:
5020 // start-sanitize-vr4xxx
5021 *vr4121:
5022 // end-sanitize-vr4xxx
5023 // start-sanitize-vr4320
5024 *vr4320:
5025 // end-sanitize-vr4320
5026 // start-sanitize-cygnus
5027 *vr5400:
5028 // end-sanitize-cygnus
5029 *r3900:
5030 // start-sanitize-tx19
5031 *tx19:
5032 // end-sanitize-tx19
5033 {
5034   unsigned32 instruction = instruction_0;
5035   int destreg = ((instruction >> 6) & 0x0000001F);
5036   int fs = ((instruction >> 11) & 0x0000001F);
5037   int ft = ((instruction >> 16) & 0x0000001F);
5038   int format = ((instruction >> 21) & 0x00000007);
5039   {
5040     if ((format != fmt_single) && (format != fmt_double))
5041       SignalException(ReservedInstruction,instruction);
5042     else
5043       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
5044   }
5045 }
5046
5047
5048 // DMFC1
5049 // DMTC1
5050 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
5051 "dm%s<X>c1 r<RT>, f<FS>"
5052 *mipsIII:
5053 {
5054   if (X)
5055     {
5056       if (SizeFGR() == 64)
5057         PENDING_FILL((FS + FGRIDX),GPR[RT]);
5058       else if ((FS & 0x1) == 0)
5059         {
5060           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
5061           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
5062         }
5063     }
5064   else
5065     {
5066       if (SizeFGR() == 64)
5067         PENDING_FILL(RT,FGR[FS]);
5068       else if ((FS & 0x1) == 0)
5069         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
5070       else
5071         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
5072     }
5073 }
5074 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
5075 "dm%s<X>c1 r<RT>, f<FS>"
5076 *mipsIV:
5077 *vr4100:
5078 *vr5000:
5079 // start-sanitize-vr4xxx
5080 *vr4121:
5081 // end-sanitize-vr4xxx
5082 // start-sanitize-vr4320
5083 *vr4320:
5084 // end-sanitize-vr4320
5085 // start-sanitize-cygnus
5086 *vr5400:
5087 // end-sanitize-cygnus
5088 // start-sanitize-r5900
5089 *r5900:
5090 // end-sanitize-r5900
5091 *r3900:
5092 // start-sanitize-tx19
5093 *tx19:
5094 // end-sanitize-tx19
5095 {
5096   if (X)
5097     {
5098       if (SizeFGR() == 64)
5099         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
5100       else if ((FS & 0x1) == 0)
5101         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
5102     }
5103   else
5104     {
5105       if (SizeFGR() == 64)
5106         GPR[RT] = FGR[FS];
5107       else if ((FS & 0x1) == 0)
5108         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
5109       else
5110         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
5111     }
5112 }
5113
5114
5115 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
5116 "floor.l.%s<FMT> f<FD>, f<FS>"
5117 *mipsIII:
5118 *mipsIV:
5119 *vr4100:
5120 *vr5000:
5121 // start-sanitize-vr4xxx
5122 *vr4121:
5123 // end-sanitize-vr4xxx
5124 // start-sanitize-vr4320
5125 *vr4320:
5126 // end-sanitize-vr4320
5127 // start-sanitize-cygnus
5128 *vr5400:
5129 // end-sanitize-cygnus
5130 // start-sanitize-r5900
5131 *r5900:
5132 // end-sanitize-r5900
5133 *r3900:
5134 // start-sanitize-tx19
5135 *tx19:
5136 // end-sanitize-tx19
5137 {
5138   unsigned32 instruction = instruction_0;
5139   int destreg = ((instruction >> 6) & 0x0000001F);
5140   int fs = ((instruction >> 11) & 0x0000001F);
5141   int format = ((instruction >> 21) & 0x00000007);
5142   {
5143     if ((format != fmt_single) && (format != fmt_double))
5144       SignalException(ReservedInstruction,instruction);
5145     else
5146       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
5147   }
5148 }
5149
5150
5151 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
5152 "floor.w.%s<FMT> f<FD>, f<FS>"
5153 *mipsII:
5154 *mipsIII:
5155 *mipsIV:
5156 *vr4100:
5157 *vr5000:
5158 // start-sanitize-vr4xxx
5159 *vr4121:
5160 // end-sanitize-vr4xxx
5161 // start-sanitize-vr4320
5162 *vr4320:
5163 // end-sanitize-vr4320
5164 // start-sanitize-cygnus
5165 *vr5400:
5166 // end-sanitize-cygnus
5167 // start-sanitize-r5900
5168 *r5900:
5169 // end-sanitize-r5900
5170 *r3900:
5171 // start-sanitize-tx19
5172 *tx19:
5173 // end-sanitize-tx19
5174 {
5175   unsigned32 instruction = instruction_0;
5176   int destreg = ((instruction >> 6) & 0x0000001F);
5177   int fs = ((instruction >> 11) & 0x0000001F);
5178   int format = ((instruction >> 21) & 0x00000007);
5179   {
5180     if ((format != fmt_single) && (format != fmt_double))
5181       SignalException(ReservedInstruction,instruction);
5182     else
5183       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
5184   }
5185 }
5186
5187
5188 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
5189 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
5190 *mipsII:
5191 *mipsIII:
5192 *mipsIV:
5193 *vr4100:
5194 *vr5000:
5195 // start-sanitize-vr4xxx
5196 *vr4121:
5197 // end-sanitize-vr4xxx
5198 // start-sanitize-vr4320
5199 *vr4320:
5200 // end-sanitize-vr4320
5201 // start-sanitize-cygnus
5202 *vr5400:
5203 // end-sanitize-cygnus
5204 *r3900:
5205 // start-sanitize-tx19
5206 *tx19:
5207 // end-sanitize-tx19
5208 {
5209   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
5210 }
5211
5212
5213 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
5214 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
5215 *mipsIV:
5216 *vr5000:
5217 // start-sanitize-vr4320
5218 *vr4320:
5219 // end-sanitize-vr4320
5220 // start-sanitize-cygnus
5221 *vr5400:
5222 // end-sanitize-cygnus
5223 {
5224   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
5225 }
5226
5227
5228
5229 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
5230 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
5231 *mipsI,mipsII,mipsIII,mipsIV:
5232 *vr4100:
5233 *vr5000:
5234 // start-sanitize-vr4xxx
5235 *vr4121:
5236 // end-sanitize-vr4xxx
5237 // start-sanitize-vr4320
5238 *vr4320:
5239 // end-sanitize-vr4320
5240 // start-sanitize-cygnus
5241 *vr5400:
5242 // end-sanitize-cygnus
5243 // start-sanitize-r5900
5244 *r5900:
5245 // end-sanitize-r5900
5246 *r3900:
5247 // start-sanitize-tx19
5248 *tx19:
5249 // end-sanitize-tx19
5250 {
5251   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
5252 }
5253
5254
5255 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
5256 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
5257 *mipsIV:
5258 *vr5000:
5259 // start-sanitize-vr4320
5260 *vr4320:
5261 // end-sanitize-vr4320
5262 // start-sanitize-cygnus
5263 *vr5400:
5264 // end-sanitize-cygnus
5265 {
5266   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
5267 }
5268
5269
5270
5271 //
5272 // FIXME: Not correct for mips*
5273 //
5274 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
5275 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
5276 *mipsIV:
5277 *vr5000:
5278 // start-sanitize-vr4320
5279 *vr4320:
5280 // end-sanitize-vr4320
5281 // start-sanitize-cygnus
5282 *vr5400:
5283 // end-sanitize-cygnus
5284 {
5285   unsigned32 instruction = instruction_0;
5286   int destreg = ((instruction >> 6) & 0x0000001F);
5287   int fs = ((instruction >> 11) & 0x0000001F);
5288   int ft = ((instruction >> 16) & 0x0000001F);
5289   int fr = ((instruction >> 21) & 0x0000001F);
5290   {
5291     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
5292   }
5293 }
5294
5295
5296 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
5297 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
5298 *mipsIV:
5299 *vr5000:
5300 // start-sanitize-vr4320
5301 *vr4320:
5302 // end-sanitize-vr4320
5303 // start-sanitize-cygnus
5304 *vr5400:
5305 // end-sanitize-cygnus
5306 {
5307   unsigned32 instruction = instruction_0;
5308   int destreg = ((instruction >> 6) & 0x0000001F);
5309   int fs = ((instruction >> 11) & 0x0000001F);
5310   int ft = ((instruction >> 16) & 0x0000001F);
5311   int fr = ((instruction >> 21) & 0x0000001F);
5312   {
5313     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
5314   }
5315 }
5316
5317
5318 // MFC1
5319 // MTC1
5320 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
5321 "m%s<X>c1 r<RT>, f<FS>"
5322 *mipsI:
5323 *mipsII:
5324 *mipsIII:
5325 {
5326   if (X)
5327     { /*MTC1*/
5328       if (SizeFGR() == 64)
5329         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
5330       else
5331         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
5332     }
5333   else /*MFC1*/
5334     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
5335 }
5336 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
5337 "m%s<X>c1 r<RT>, f<FS>"
5338 *mipsIV:
5339 *vr4100:
5340 *vr5000:
5341 // start-sanitize-vr4xxx
5342 *vr4121:
5343 // end-sanitize-vr4xxx
5344 // start-sanitize-vr4320
5345 *vr4320:
5346 // end-sanitize-vr4320
5347 // start-sanitize-cygnus
5348 *vr5400:
5349 // end-sanitize-cygnus
5350 *r3900:
5351 // start-sanitize-tx19
5352 *tx19:
5353 // end-sanitize-tx19
5354 {
5355   int fs = FS;
5356   if (X)
5357     /*MTC1*/
5358     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
5359   else /*MFC1*/
5360     GPR[RT] = SIGNEXTEND(FGR[FS],32);
5361 }
5362
5363
5364 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
5365 "mov.%s<FMT> f<FD>, f<FS>"
5366 *mipsI,mipsII,mipsIII,mipsIV:
5367 *vr4100:
5368 *vr5000:
5369 // start-sanitize-vr4xxx
5370 *vr4121:
5371 // end-sanitize-vr4xxx
5372 // start-sanitize-vr4320
5373 *vr4320:
5374 // end-sanitize-vr4320
5375 // start-sanitize-cygnus
5376 *vr5400:
5377 // end-sanitize-cygnus
5378 *r3900:
5379 // start-sanitize-tx19
5380 *tx19:
5381 // end-sanitize-tx19
5382 {
5383   unsigned32 instruction = instruction_0;
5384   int destreg = ((instruction >> 6) & 0x0000001F);
5385   int fs = ((instruction >> 11) & 0x0000001F);
5386   int format = ((instruction >> 21) & 0x00000007);
5387   {
5388     StoreFPR(destreg,format,ValueFPR(fs,format));
5389   }
5390 }
5391
5392
5393 // MOVF
5394 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
5395 "mov%s<TF> r<RD>, r<RS>, <CC>"
5396 *mipsIV:
5397 *vr5000:
5398 // start-sanitize-vr4320
5399 *vr4320:
5400 // end-sanitize-vr4320
5401 // start-sanitize-cygnus
5402 *vr5400:
5403 // end-sanitize-cygnus
5404 // start-sanitize-r5900
5405 *r5900:
5406 // end-sanitize-r5900
5407 {
5408   if (GETFCC(CC) == TF)
5409     GPR[RD] = GPR[RS];
5410 }
5411
5412
5413 // MOVF.fmt
5414 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
5415 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
5416 *mipsIV:
5417 *vr5000:
5418 // start-sanitize-vr4320
5419 *vr4320:
5420 // end-sanitize-vr4320
5421 // start-sanitize-cygnus
5422 *vr5400:
5423 // end-sanitize-cygnus
5424 // start-sanitize-r5900
5425 *r5900:
5426 // end-sanitize-r5900
5427 {
5428   unsigned32 instruction = instruction_0;
5429   int format = ((instruction >> 21) & 0x00000007);
5430   {
5431    if (GETFCC(CC) == TF)
5432      StoreFPR (FD, format, ValueFPR (FS, format));
5433    else
5434      StoreFPR (FD, format, ValueFPR (FD, format));
5435   }
5436 }
5437
5438
5439 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
5440 *mipsIV:
5441 *vr5000:
5442 // start-sanitize-vr4320
5443 *vr4320:
5444 // end-sanitize-vr4320
5445 // start-sanitize-cygnus
5446 *vr5400:
5447 // end-sanitize-cygnus
5448 // start-sanitize-r5900
5449 *r5900:
5450 // end-sanitize-r5900
5451 {
5452   unsigned32 instruction = instruction_0;
5453   int destreg = ((instruction >> 6) & 0x0000001F);
5454   int fs = ((instruction >> 11) & 0x0000001F);
5455   int format = ((instruction >> 21) & 0x00000007);
5456   {
5457     StoreFPR(destreg,format,ValueFPR(fs,format));
5458   }
5459 }
5460
5461
5462 // MOVT see MOVtf
5463
5464
5465 // MOVT.fmt see MOVtf.fmt
5466
5467
5468
5469 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
5470 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
5471 *mipsIV:
5472 *vr5000:
5473 // start-sanitize-vr4320
5474 *vr4320:
5475 // end-sanitize-vr4320
5476 // start-sanitize-cygnus
5477 *vr5400:
5478 // end-sanitize-cygnus
5479 // start-sanitize-r5900
5480 *r5900:
5481 // end-sanitize-r5900
5482 {
5483   unsigned32 instruction = instruction_0;
5484   int destreg = ((instruction >> 6) & 0x0000001F);
5485   int fs = ((instruction >> 11) & 0x0000001F);
5486   int format = ((instruction >> 21) & 0x00000007);
5487   {
5488    StoreFPR(destreg,format,ValueFPR(fs,format));
5489   }
5490 }
5491
5492
5493 // MSUB.fmt
5494 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
5495 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
5496 *mipsIV:
5497 *vr5000:
5498 // start-sanitize-vr4320
5499 *vr4320:
5500 // end-sanitize-vr4320
5501 // start-sanitize-cygnus
5502 *vr5400:
5503 // end-sanitize-cygnus
5504 // start-sanitize-r5900
5505 *r5900:
5506 // end-sanitize-r5900
5507 {
5508   unsigned32 instruction = instruction_0;
5509   int destreg = ((instruction >> 6) & 0x0000001F);
5510   int fs = ((instruction >> 11) & 0x0000001F);
5511   int ft = ((instruction >> 16) & 0x0000001F);
5512   int fr = ((instruction >> 21) & 0x0000001F);
5513   {
5514     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
5515   }
5516 }
5517
5518
5519 // MSUB.fmt
5520 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
5521 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
5522 *mipsIV:
5523 *vr5000:
5524 // start-sanitize-vr4320
5525 *vr4320:
5526 // end-sanitize-vr4320
5527 // start-sanitize-cygnus
5528 *vr5400:
5529 // end-sanitize-cygnus
5530 // start-sanitize-r5900
5531 *r5900:
5532 // end-sanitize-r5900
5533 {
5534   unsigned32 instruction = instruction_0;
5535   int destreg = ((instruction >> 6) & 0x0000001F);
5536   int fs = ((instruction >> 11) & 0x0000001F);
5537   int ft = ((instruction >> 16) & 0x0000001F);
5538   int fr = ((instruction >> 21) & 0x0000001F);
5539   {
5540    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
5541   }
5542 }
5543
5544
5545 // MTC1 see MxC1
5546
5547
5548 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
5549 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
5550 *mipsI,mipsII,mipsIII,mipsIV:
5551 *vr4100:
5552 *vr5000:
5553 // start-sanitize-vr4xxx
5554 *vr4121:
5555 // end-sanitize-vr4xxx
5556 // start-sanitize-vr4320
5557 *vr4320:
5558 // end-sanitize-vr4320
5559 // start-sanitize-cygnus
5560 *vr5400:
5561 // end-sanitize-cygnus
5562 *r3900:
5563 // start-sanitize-tx19
5564 *tx19:
5565 // end-sanitize-tx19
5566 {
5567   unsigned32 instruction = instruction_0;
5568   int destreg = ((instruction >> 6) & 0x0000001F);
5569   int fs = ((instruction >> 11) & 0x0000001F);
5570   int ft = ((instruction >> 16) & 0x0000001F);
5571   int format = ((instruction >> 21) & 0x00000007);
5572   {
5573     if ((format != fmt_single) && (format != fmt_double))
5574       SignalException(ReservedInstruction,instruction);
5575     else
5576       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
5577   }
5578 }
5579
5580
5581 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
5582 "neg.%s<FMT> f<FD>, f<FS>"
5583 *mipsI,mipsII,mipsIII,mipsIV:
5584 *vr4100:
5585 *vr5000:
5586 // start-sanitize-vr4xxx
5587 *vr4121:
5588 // end-sanitize-vr4xxx
5589 // start-sanitize-vr4320
5590 *vr4320:
5591 // end-sanitize-vr4320
5592 // start-sanitize-cygnus
5593 *vr5400:
5594 // end-sanitize-cygnus
5595 *r3900:
5596 // start-sanitize-tx19
5597 *tx19:
5598 // end-sanitize-tx19
5599 {
5600   unsigned32 instruction = instruction_0;
5601   int destreg = ((instruction >> 6) & 0x0000001F);
5602   int fs = ((instruction >> 11) & 0x0000001F);
5603   int format = ((instruction >> 21) & 0x00000007);
5604   {
5605     if ((format != fmt_single) && (format != fmt_double))
5606       SignalException(ReservedInstruction,instruction);
5607     else
5608       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
5609   }
5610 }
5611
5612
5613 // NMADD.fmt
5614 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
5615 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
5616 *mipsIV:
5617 *vr5000:
5618 // start-sanitize-vr4320
5619 *vr4320:
5620 // end-sanitize-vr4320
5621 // start-sanitize-cygnus
5622 *vr5400:
5623 // end-sanitize-cygnus
5624 {
5625   unsigned32 instruction = instruction_0;
5626   int destreg = ((instruction >> 6) & 0x0000001F);
5627   int fs = ((instruction >> 11) & 0x0000001F);
5628   int ft = ((instruction >> 16) & 0x0000001F);
5629   int fr = ((instruction >> 21) & 0x0000001F);
5630   {
5631    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5632   }
5633 }
5634
5635
5636 // NMADD.fmt
5637 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
5638 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
5639 *mipsIV:
5640 *vr5000:
5641 // start-sanitize-vr4320
5642 *vr4320:
5643 // end-sanitize-vr4320
5644 // start-sanitize-cygnus
5645 *vr5400:
5646 // end-sanitize-cygnus
5647 {
5648   unsigned32 instruction = instruction_0;
5649   int destreg = ((instruction >> 6) & 0x0000001F);
5650   int fs = ((instruction >> 11) & 0x0000001F);
5651   int ft = ((instruction >> 16) & 0x0000001F);
5652   int fr = ((instruction >> 21) & 0x0000001F);
5653   {
5654    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5655   }
5656 }
5657
5658
5659 // NMSUB.fmt
5660 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
5661 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
5662 *mipsIV:
5663 *vr5000:
5664 // start-sanitize-vr4320
5665 *vr4320:
5666 // end-sanitize-vr4320
5667 // start-sanitize-cygnus
5668 *vr5400:
5669 // end-sanitize-cygnus
5670 {
5671   unsigned32 instruction = instruction_0;
5672   int destreg = ((instruction >> 6) & 0x0000001F);
5673   int fs = ((instruction >> 11) & 0x0000001F);
5674   int ft = ((instruction >> 16) & 0x0000001F);
5675   int fr = ((instruction >> 21) & 0x0000001F);
5676   {
5677    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5678   }
5679 }
5680
5681
5682 // NMSUB.fmt
5683 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
5684 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
5685 *mipsIV:
5686 *vr5000:
5687 // start-sanitize-vr4320
5688 *vr4320:
5689 // end-sanitize-vr4320
5690 // start-sanitize-cygnus
5691 *vr5400:
5692 // end-sanitize-cygnus
5693 {
5694   unsigned32 instruction = instruction_0;
5695   int destreg = ((instruction >> 6) & 0x0000001F);
5696   int fs = ((instruction >> 11) & 0x0000001F);
5697   int ft = ((instruction >> 16) & 0x0000001F);
5698   int fr = ((instruction >> 21) & 0x0000001F);
5699   {
5700     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5701   }
5702 }
5703
5704
5705 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
5706 "prefx <HINT>, r<INDEX>(r<BASE>)"
5707 *mipsIV:
5708 *vr5000:
5709 // start-sanitize-vr4320
5710 *vr4320:
5711 // end-sanitize-vr4320
5712 // start-sanitize-cygnus
5713 *vr5400:
5714 // end-sanitize-cygnus
5715 {
5716   unsigned32 instruction = instruction_0;
5717   int fs = ((instruction >> 11) & 0x0000001F);
5718   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5719   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5720   {
5721     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5722     address_word paddr;
5723     int uncached;
5724     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5725       Prefetch(uncached,paddr,vaddr,isDATA,fs);
5726   }
5727 }
5728
5729 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5730 *mipsIV:
5731 "recip.%s<FMT> f<FD>, f<FS>"
5732 *vr5000:
5733 // start-sanitize-vr4320
5734 *vr4320:
5735 // end-sanitize-vr4320
5736 // start-sanitize-cygnus
5737 *vr5400:
5738 // end-sanitize-cygnus
5739 {
5740   unsigned32 instruction = instruction_0;
5741   int destreg = ((instruction >> 6) & 0x0000001F);
5742   int fs = ((instruction >> 11) & 0x0000001F);
5743   int format = ((instruction >> 21) & 0x00000007);
5744   {
5745   if ((format != fmt_single) && (format != fmt_double))
5746    SignalException(ReservedInstruction,instruction);
5747   else
5748    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5749   }
5750 }
5751
5752
5753 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5754 "round.l.%s<FMT> f<FD>, f<FS>"
5755 *mipsIII:
5756 *mipsIV:
5757 *vr4100:
5758 *vr5000:
5759 // start-sanitize-vr4xxx
5760 *vr4121:
5761 // end-sanitize-vr4xxx
5762 // start-sanitize-vr4320
5763 *vr4320:
5764 // end-sanitize-vr4320
5765 // start-sanitize-cygnus
5766 *vr5400:
5767 // end-sanitize-cygnus
5768 // start-sanitize-r5900
5769 *r5900:
5770 // end-sanitize-r5900
5771 *r3900:
5772 // start-sanitize-tx19
5773 *tx19:
5774 // end-sanitize-tx19
5775 {
5776   unsigned32 instruction = instruction_0;
5777   int destreg = ((instruction >> 6) & 0x0000001F);
5778   int fs = ((instruction >> 11) & 0x0000001F);
5779   int format = ((instruction >> 21) & 0x00000007);
5780   {
5781     if ((format != fmt_single) && (format != fmt_double))
5782       SignalException(ReservedInstruction,instruction);
5783     else
5784       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5785   }
5786 }
5787
5788
5789 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5790 "round.w.%s<FMT> f<FD>, f<FS>"
5791 *mipsII:
5792 *mipsIII:
5793 *mipsIV:
5794 *vr4100:
5795 *vr5000:
5796 // start-sanitize-vr4xxx
5797 *vr4121:
5798 // end-sanitize-vr4xxx
5799 // start-sanitize-vr4320
5800 *vr4320:
5801 // end-sanitize-vr4320
5802 // start-sanitize-cygnus
5803 *vr5400:
5804 // end-sanitize-cygnus
5805 // start-sanitize-r5900
5806 *r5900:
5807 // end-sanitize-r5900
5808 *r3900:
5809 // start-sanitize-tx19
5810 *tx19:
5811 // end-sanitize-tx19
5812 {
5813   unsigned32 instruction = instruction_0;
5814   int destreg = ((instruction >> 6) & 0x0000001F);
5815   int fs = ((instruction >> 11) & 0x0000001F);
5816   int format = ((instruction >> 21) & 0x00000007);
5817   {
5818   if ((format != fmt_single) && (format != fmt_double))
5819    SignalException(ReservedInstruction,instruction);
5820   else
5821    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5822   }
5823 }
5824
5825
5826 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5827 *mipsIV:
5828 "rsqrt.%s<FMT> f<FD>, f<FS>"
5829 *vr5000:
5830 // start-sanitize-vr4320
5831 *vr4320:
5832 // end-sanitize-vr4320
5833 // start-sanitize-cygnus
5834 *vr5400:
5835 // end-sanitize-cygnus
5836 {
5837   unsigned32 instruction = instruction_0;
5838   int destreg = ((instruction >> 6) & 0x0000001F);
5839   int fs = ((instruction >> 11) & 0x0000001F);
5840   int format = ((instruction >> 21) & 0x00000007);
5841   {
5842   if ((format != fmt_single) && (format != fmt_double))
5843    SignalException(ReservedInstruction,instruction);
5844   else
5845    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5846   }
5847 }
5848
5849
5850 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5851 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5852 *mipsII:
5853 *mipsIII:
5854 *mipsIV:
5855 *vr4100:
5856 *vr5000:
5857 // start-sanitize-vr4xxx
5858 *vr4121:
5859 // end-sanitize-vr4xxx
5860 // start-sanitize-vr4320
5861 *vr4320:
5862 // end-sanitize-vr4320
5863 // start-sanitize-cygnus
5864 *vr5400:
5865 // end-sanitize-cygnus
5866 *r3900:
5867 // start-sanitize-tx19
5868 *tx19:
5869 // end-sanitize-tx19
5870 {
5871   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5872 }
5873
5874
5875 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5876 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5877 *mipsIV:
5878 *vr5000:
5879 // start-sanitize-vr4320
5880 *vr4320:
5881 // end-sanitize-vr4320
5882 // start-sanitize-cygnus
5883 *vr5400:
5884 // end-sanitize-cygnus
5885 {
5886   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5887 }
5888
5889
5890 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5891 "sqrt.%s<FMT> f<FD>, f<FS>"
5892 *mipsII:
5893 *mipsIII:
5894 *mipsIV:
5895 *vr4100:
5896 *vr5000:
5897 // start-sanitize-vr4xxx
5898 *vr4121:
5899 // end-sanitize-vr4xxx
5900 // start-sanitize-vr4320
5901 *vr4320:
5902 // end-sanitize-vr4320
5903 // start-sanitize-cygnus
5904 *vr5400:
5905 // end-sanitize-cygnus
5906 *r3900:
5907 // start-sanitize-tx19
5908 *tx19:
5909 // end-sanitize-tx19
5910 {
5911   unsigned32 instruction = instruction_0;
5912   int destreg = ((instruction >> 6) & 0x0000001F);
5913   int fs = ((instruction >> 11) & 0x0000001F);
5914   int format = ((instruction >> 21) & 0x00000007);
5915   {
5916     if ((format != fmt_single) && (format != fmt_double))
5917       SignalException(ReservedInstruction,instruction);
5918     else
5919       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5920   }
5921 }
5922
5923
5924 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5925 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5926 *mipsI,mipsII,mipsIII,mipsIV:
5927 *vr4100:
5928 *vr5000:
5929 // start-sanitize-vr4xxx
5930 *vr4121:
5931 // end-sanitize-vr4xxx
5932 // start-sanitize-vr4320
5933 *vr4320:
5934 // end-sanitize-vr4320
5935 // start-sanitize-cygnus
5936 *vr5400:
5937 // end-sanitize-cygnus
5938 *r3900:
5939 // start-sanitize-tx19
5940 *tx19:
5941 // end-sanitize-tx19
5942 {
5943   unsigned32 instruction = instruction_0;
5944   int destreg = ((instruction >> 6) & 0x0000001F);
5945   int fs = ((instruction >> 11) & 0x0000001F);
5946   int ft = ((instruction >> 16) & 0x0000001F);
5947   int format = ((instruction >> 21) & 0x00000007);
5948   {
5949     if ((format != fmt_single) && (format != fmt_double))
5950       SignalException(ReservedInstruction,instruction);
5951     else
5952       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5953   }
5954 }
5955
5956
5957
5958 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5959 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5960 *mipsI,mipsII,mipsIII,mipsIV:
5961 *vr4100:
5962 *vr5000:
5963 // start-sanitize-vr4xxx
5964 *vr4121:
5965 // end-sanitize-vr4xxx
5966 // start-sanitize-vr4320
5967 *vr4320:
5968 // end-sanitize-vr4320
5969 // start-sanitize-cygnus
5970 *vr5400:
5971 // end-sanitize-cygnus
5972 // start-sanitize-r5900
5973 *r5900:
5974 // end-sanitize-r5900
5975 *r3900:
5976 // start-sanitize-tx19
5977 *tx19:
5978 // end-sanitize-tx19
5979 {
5980   unsigned32 instruction = instruction_0;
5981   signed_word offset = EXTEND16 (OFFSET);
5982   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5983   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5984   {
5985     address_word vaddr = ((uword64)op1 + offset);
5986     address_word paddr;
5987     int uncached;
5988     if ((vaddr & 3) != 0)
5989       {
5990         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5991       }
5992     else
5993       {
5994         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5995           {
5996             uword64 memval = 0;
5997             uword64 memval1 = 0;
5998             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5999             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
6000             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
6001             unsigned int byte;
6002             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
6003             byte = ((vaddr & mask) ^ bigendiancpu);
6004             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
6005             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
6006           }
6007       }
6008   }
6009 }
6010
6011
6012 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
6013 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
6014 *mipsIV:
6015 *vr5000:
6016 // start-sanitize-vr4320
6017 *vr4320:
6018 // end-sanitize-vr4320
6019 // start-sanitize-cygnus
6020 *vr5400:
6021 // end-sanitize-cygnus
6022 {
6023   unsigned32 instruction = instruction_0;
6024   int fs = ((instruction >> 11) & 0x0000001F);
6025   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
6026   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
6027   {
6028    address_word vaddr = ((unsigned64)op1 + op2);
6029    address_word paddr;
6030    int uncached;
6031    if ((vaddr & 3) != 0)
6032      {
6033        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
6034      }
6035    else
6036    {
6037     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
6038     {
6039      unsigned64 memval = 0;
6040      unsigned64 memval1 = 0;
6041      unsigned64 mask = 0x7;
6042      unsigned int byte;
6043      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
6044      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
6045      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
6046       {
6047        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
6048       }
6049     }
6050    }
6051   }
6052 }
6053
6054
6055 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
6056 "trunc.l.%s<FMT> f<FD>, f<FS>"
6057 *mipsIII:
6058 *mipsIV:
6059 *vr4100:
6060 *vr5000:
6061 // start-sanitize-vr4xxx
6062 *vr4121:
6063 // end-sanitize-vr4xxx
6064 // start-sanitize-vr4320
6065 *vr4320:
6066 // end-sanitize-vr4320
6067 // start-sanitize-cygnus
6068 *vr5400:
6069 // end-sanitize-cygnus
6070 // start-sanitize-r5900
6071 *r5900:
6072 // end-sanitize-r5900
6073 *r3900:
6074 // start-sanitize-tx19
6075 *tx19:
6076 // end-sanitize-tx19
6077 {
6078   unsigned32 instruction = instruction_0;
6079   int destreg = ((instruction >> 6) & 0x0000001F);
6080   int fs = ((instruction >> 11) & 0x0000001F);
6081   int format = ((instruction >> 21) & 0x00000007);
6082   {
6083   if ((format != fmt_single) && (format != fmt_double))
6084    SignalException(ReservedInstruction,instruction);
6085   else
6086    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
6087   }
6088 }
6089
6090
6091 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
6092 "trunc.w.%s<FMT> f<FD>, f<FS>"
6093 *mipsII:
6094 *mipsIII:
6095 *mipsIV:
6096 *vr4100:
6097 *vr5000:
6098 // start-sanitize-vr4xxx
6099 *vr4121:
6100 // end-sanitize-vr4xxx
6101 // start-sanitize-vr4320
6102 *vr4320:
6103 // end-sanitize-vr4320
6104 // start-sanitize-cygnus
6105 *vr5400:
6106 // end-sanitize-cygnus
6107 // start-sanitize-r5900
6108 *r5900:
6109 // end-sanitize-r5900
6110 *r3900:
6111 // start-sanitize-tx19
6112 *tx19:
6113 // end-sanitize-tx19
6114 {
6115   unsigned32 instruction = instruction_0;
6116   int destreg = ((instruction >> 6) & 0x0000001F);
6117   int fs = ((instruction >> 11) & 0x0000001F);
6118   int format = ((instruction >> 21) & 0x00000007);
6119   {
6120   if ((format != fmt_single) && (format != fmt_double))
6121    SignalException(ReservedInstruction,instruction);
6122   else
6123    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
6124   }
6125 }
6126
6127 \f
6128 //
6129 // MIPS Architecture:
6130 //
6131 //        System Control Instruction Set (COP0)
6132 //
6133
6134
6135 010000,01000,00000,16.OFFSET:COP0:32::BC0F
6136 "bc0f <OFFSET>"
6137 *mipsI,mipsII,mipsIII,mipsIV:
6138 *vr4100:
6139 *vr5000:
6140 // start-sanitize-vr4xxx
6141 *vr4121:
6142 // end-sanitize-vr4xxx
6143 // start-sanitize-vr4320
6144 *vr4320:
6145 // end-sanitize-vr4320
6146 // start-sanitize-cygnus
6147 *vr5400:
6148 // end-sanitize-cygnus
6149
6150
6151 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
6152 "bc0fl <OFFSET>"
6153 *mipsI,mipsII,mipsIII,mipsIV:
6154 *vr4100:
6155 *vr5000:
6156 // start-sanitize-vr4xxx
6157 *vr4121:
6158 // end-sanitize-vr4xxx
6159 // start-sanitize-vr4320
6160 *vr4320:
6161 // end-sanitize-vr4320
6162 // start-sanitize-cygnus
6163 *vr5400:
6164 // end-sanitize-cygnus
6165
6166
6167 010000,01000,00001,16.OFFSET:COP0:32::BC0T
6168 "bc0t <OFFSET>"
6169 *mipsI,mipsII,mipsIII,mipsIV:
6170 *vr4100:
6171 // start-sanitize-vr4xxx
6172 *vr4121:
6173 // end-sanitize-vr4xxx
6174
6175
6176 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
6177 "bc0tl <OFFSET>"
6178 *mipsI,mipsII,mipsIII,mipsIV:
6179 *vr4100:
6180 *vr5000:
6181 // start-sanitize-vr4xxx
6182 *vr4121:
6183 // end-sanitize-vr4xxx
6184 // start-sanitize-vr4320
6185 *vr4320:
6186 // end-sanitize-vr4320
6187 // start-sanitize-cygnus
6188 *vr5400:
6189 // end-sanitize-cygnus
6190
6191
6192 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
6193 *mipsIII:
6194 *mipsIV:
6195 *vr4100:
6196 *vr5000:
6197 // start-sanitize-vr4xxx
6198 *vr4121:
6199 // end-sanitize-vr4xxx
6200 // start-sanitize-vr4320
6201 *vr4320:
6202 // end-sanitize-vr4320
6203 // start-sanitize-cygnus
6204 *vr5400:
6205 // end-sanitize-cygnus
6206 *r3900:
6207 // start-sanitize-tx19
6208 *tx19:
6209 // end-sanitize-tx19
6210 {
6211   unsigned32 instruction = instruction_0;
6212   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
6213   int hint = ((instruction >> 16) & 0x0000001F);
6214   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
6215   {
6216     address_word vaddr = (op1 + offset);
6217     address_word paddr;
6218     int uncached;
6219     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
6220       CacheOp(hint,vaddr,paddr,instruction);
6221   }
6222 }
6223
6224
6225 010000,10000,000000000000000,111001:COP0:32::DI
6226 "di"
6227 *mipsI,mipsII,mipsIII,mipsIV:
6228 *vr4100:
6229 *vr5000:
6230 // start-sanitize-vr4xxx
6231 *vr4121:
6232 // end-sanitize-vr4xxx
6233 // start-sanitize-vr4320
6234 *vr4320:
6235 // end-sanitize-vr4320
6236 // start-sanitize-cygnus
6237 *vr5400:
6238 // end-sanitize-cygnus
6239
6240
6241 010000,10000,000000000000000,111000:COP0:32::EI
6242 "ei"
6243 *mipsI,mipsII,mipsIII,mipsIV:
6244 *vr4100:
6245 *vr5000:
6246 // start-sanitize-vr4xxx
6247 *vr4121:
6248 // end-sanitize-vr4xxx
6249 // start-sanitize-vr4320
6250 *vr4320:
6251 // end-sanitize-vr4320
6252 // start-sanitize-cygnus
6253 *vr5400:
6254 // end-sanitize-cygnus
6255
6256
6257 010000,10000,000000000000000,011000:COP0:32::ERET
6258 "eret"
6259 *mipsIII:
6260 *mipsIV:
6261 *vr4100:
6262 *vr5000:
6263 // start-sanitize-vr4xxx
6264 *vr4121:
6265 // end-sanitize-vr4xxx
6266 // start-sanitize-vr4320
6267 *vr4320:
6268 // end-sanitize-vr4320
6269 // start-sanitize-cygnus
6270 *vr5400:
6271 // end-sanitize-cygnus
6272 // start-sanitize-r5900
6273 *r5900:
6274 // end-sanitize-r5900
6275 {
6276   if (SR & status_ERL)
6277     {
6278       /* Oops, not yet available */
6279       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
6280       NIA = EPC;
6281       SR &= ~status_ERL;
6282     }
6283   else
6284     {
6285       NIA = EPC;
6286       SR &= ~status_EXL;
6287     }
6288 }
6289
6290
6291 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
6292 "mfc0 r<RT>, r<RD> # <REGX>"
6293 *mipsI,mipsII,mipsIII,mipsIV:
6294 *r3900:
6295 *vr4100:
6296 *vr5000:
6297 // start-sanitize-vr4xxx
6298 *vr4121:
6299 // end-sanitize-vr4xxx
6300 // start-sanitize-vr4320
6301 *vr4320:
6302 // end-sanitize-vr4320
6303 // start-sanitize-cygnus
6304 *vr5400:
6305 // end-sanitize-cygnus
6306 // start-sanitize-r5900
6307 *r5900:
6308 // end-sanitize-r5900
6309 {
6310   TRACE_ALU_INPUT0 ();
6311   DecodeCoproc (instruction_0);
6312   TRACE_ALU_RESULT (GPR[RT]);
6313 }
6314
6315 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
6316 "mtc0 r<RT>, r<RD> # <REGX>"
6317 *mipsI,mipsII,mipsIII,mipsIV:
6318 // start-sanitize-tx19
6319 *tx19:
6320 // end-sanitize-tx19
6321 *r3900:
6322 *vr4100:
6323 // start-sanitize-vr4xxx
6324 *vr4121:
6325 // end-sanitize-vr4xxx
6326 // start-sanitize-vr4320
6327 *vr4320:
6328 // end-sanitize-vr4320
6329 *vr5000:
6330 // start-sanitize-cygnus
6331 *vr5400:
6332 // end-sanitize-cygnus
6333 // start-sanitize-r5900
6334 *r5900:
6335 // end-sanitize-r5900
6336 {
6337   DecodeCoproc (instruction_0);
6338 }
6339
6340
6341 010000,10000,000000000000000,010000:COP0:32::RFE
6342 "rfe"
6343 *mipsI,mipsII,mipsIII,mipsIV:
6344 // start-sanitize-tx19
6345 *tx19:
6346 // end-sanitize-tx19
6347 *r3900:
6348 *vr4100:
6349 // start-sanitize-vr4xxx
6350 *vr4121:
6351 // end-sanitize-vr4xxx
6352 // start-sanitize-vr4320
6353 *vr4320:
6354 // end-sanitize-vr4320
6355 *vr5000:
6356 // start-sanitize-cygnus
6357 *vr5400:
6358 // end-sanitize-cygnus
6359 // start-sanitize-r5900
6360 *r5900:
6361 // end-sanitize-r5900
6362 {
6363   DecodeCoproc (instruction_0);
6364 }
6365
6366
6367 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
6368 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
6369 *mipsI,mipsII,mipsIII,mipsIV:
6370 *vr4100:
6371 // start-sanitize-vr4xxx
6372 *vr4121:
6373 // end-sanitize-vr4xxx
6374 // start-sanitize-r5900
6375 *r5900:
6376 // end-sanitize-r5900
6377 *r3900:
6378 // start-sanitize-tx19
6379 *tx19:
6380 // end-sanitize-tx19
6381 {
6382   DecodeCoproc (instruction_0);
6383 }
6384
6385
6386
6387 010000,10000,000000000000000,001000:COP0:32::TLBP
6388 "tlbp"
6389 *mipsI,mipsII,mipsIII,mipsIV:
6390 *vr4100:
6391 *vr5000:
6392 // start-sanitize-vr4xxx
6393 *vr4121:
6394 // end-sanitize-vr4xxx
6395 // start-sanitize-vr4320
6396 *vr4320:
6397 // end-sanitize-vr4320
6398 // start-sanitize-cygnus
6399 *vr5400:
6400 // end-sanitize-cygnus
6401
6402
6403 010000,10000,000000000000000,000001:COP0:32::TLBR
6404 "tlbr"
6405 *mipsI,mipsII,mipsIII,mipsIV:
6406 *vr4100:
6407 *vr5000:
6408 // start-sanitize-vr4xxx
6409 *vr4121:
6410 // end-sanitize-vr4xxx
6411 // start-sanitize-vr4320
6412 *vr4320:
6413 // end-sanitize-vr4320
6414 // start-sanitize-cygnus
6415 *vr5400:
6416 // end-sanitize-cygnus
6417
6418
6419 010000,10000,000000000000000,000010:COP0:32::TLBWI
6420 "tlbwi"
6421 *mipsI,mipsII,mipsIII,mipsIV:
6422 *vr4100:
6423 *vr5000:
6424 // start-sanitize-vr4xxx
6425 *vr4121:
6426 // end-sanitize-vr4xxx
6427 // start-sanitize-vr4320
6428 *vr4320:
6429 // end-sanitize-vr4320
6430 // start-sanitize-cygnus
6431 *vr5400:
6432 // end-sanitize-cygnus
6433
6434
6435 010000,10000,000000000000000,000110:COP0:32::TLBWR
6436 "tlbwr"
6437 *mipsI,mipsII,mipsIII,mipsIV:
6438 *vr4100:
6439 *vr5000:
6440 // start-sanitize-vr4xxx
6441 *vr4121:
6442 // end-sanitize-vr4xxx
6443 // start-sanitize-vr4320
6444 *vr4320:
6445 // end-sanitize-vr4320
6446 // start-sanitize-cygnus
6447 *vr5400:
6448 // end-sanitize-cygnus
6449
6450 \f
6451 :include:::m16.igen
6452 // start-sanitize-cygnus
6453 :include:64,f::mdmx.igen
6454 // end-sanitize-cygnus
6455 // start-sanitize-r5900
6456 :include::r5900:r5900.igen
6457 // end-sanitize-r5900
6458 :include:::tx.igen
6459 :include:::vr.igen
6460 \f
6461 // start-sanitize-cygnus-never
6462
6463 // // FIXME FIXME FIXME What is this instruction?
6464 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
6465 // *mipsI:
6466 // *mipsII:
6467 // *mipsIII:
6468 // *mipsIV:
6469 // // start-sanitize-r5900
6470 // *r5900:
6471 // // end-sanitize-r5900
6472 // *r3900:
6473 // // start-sanitize-tx19
6474 // *tx19:
6475 // // end-sanitize-tx19
6476 // {
6477 //   unsigned32 instruction = instruction_0;
6478 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
6479 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
6480 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
6481 //   {
6482 //     if (CoProcPresent(3))
6483 //       SignalException(CoProcessorUnusable);
6484 //     else
6485 //       SignalException(ReservedInstruction,instruction);
6486 //   }
6487 // }
6488
6489 // end-sanitize-cygnus-never
6490 // start-sanitize-cygnus-never
6491
6492 // // FIXME FIXME FIXME What is this?
6493 // 11100,******,00001:RR:16::SDBBP
6494 // *mips16:
6495 // {
6496 //   unsigned32 instruction = instruction_0;
6497 //   if (have_extendval)
6498 //     SignalException (ReservedInstruction, instruction);
6499 //   {
6500 //     SignalException(DebugBreakPoint,instruction);
6501 //   }
6502 // }
6503
6504 // end-sanitize-cygnus-never
6505 // start-sanitize-cygnus-never
6506
6507 // // FIXME FIXME FIXME What is this?
6508 // 000000,********************,001110:SPECIAL:32::SDBBP
6509 // *r3900:
6510 // {
6511 //   unsigned32 instruction = instruction_0;
6512 //   {
6513 //     SignalException(DebugBreakPoint,instruction);
6514 //   }
6515 // }
6516
6517 // end-sanitize-cygnus-never