sim/mips/micromips.igen

   1 // Simulator definition for the micromips ASE.
   2 // Copyright (C) 2005-2015 Free Software Foundation, Inc.
   3 // Contributed by Imagination Technologies, Ltd.
   4 // Written by Andrew Bennett <andrew.bennett@imgtec.com>
   5 //
   6 // This file is part of the MIPS sim.
   7 //
   8 // This program is free software; you can redistribute it and/or modify
   9 // it under the terms of the GNU General Public License as published by
  10 // the Free Software Foundation; either version 3 of the License, or
  11 // (at your option) any later version.
  12 //
  13 // This program is distributed in the hope that it will be useful,
  14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 // GNU General Public License for more details.
  17 //
  18 // You should have received a copy of the GNU General Public License
  19 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20
  21 :compute:::int:TBASE:BASE:((BASE < 2) ? (16 + BASE) \: BASE)
  22 :compute:::int:TRD:RD:((RD < 2) ? (16 + RD) \: RD)
  23 :compute:::int:TRS:RS:((RS < 2) ? (16 + RS) \: RS)
  24 :compute:::int:TRT:RT:((RT < 2) ? (16 + RT) \: RT)
  25 :compute:::int:TRT_S:RT_S:((RT_S == 1 ) ? 17 \: RT_S)
  26 :compute:::int:ERT:RT:(compute_movep_src_reg (SD_, RT))
  27 :compute:::int:ERS:RS:(compute_movep_src_reg (SD_, RS))
  28
  29 :compute:::int:IMM_DEC1:IMMEDIATE:((IMMEDIATE == 7) ? -1 \: ((IMMEDIATE == 0) ? 1 \: IMMEDIATE << 2))
  30 :compute:::int:IMM_DEC2:IMMEDIATE:((IMMEDIATE < 8) ? IMMEDIATE \: (IMMEDIATE - 16))
  31 :compute:::int:IMM_DEC3:IMMEDIATE:((IMMEDIATE < 2) ? IMMEDIATE + 256 \: ((IMMEDIATE < 256) ? IMMEDIATE \: ((IMMEDIATE < 510) ? IMMEDIATE - 512 \: IMMEDIATE - 768)))
  32 :compute:::int:IMM_DEC4:IMMEDIATE:(compute_andi16_imm (SD_, IMMEDIATE))
  33 :compute:::int:IMM_DEC5:IMMEDIATE:((IMMEDIATE < 15) ? IMMEDIATE \: -1)
  34 :compute:::int:IMM_DEC6:IMMEDIATE:((IMMEDIATE < 127) ? IMMEDIATE \: -1)
  35
  36 :compute:::int:SHIFT_DEC:SHIFT:((SHIFT == 0) ? 8 \: SHIFT)
  37
  38 :compute:::int:IMM_SHIFT_1BIT:IMMEDIATE:(IMMEDIATE << 1)
  39 :compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)
  40
  41 :function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size
  42 {
  43   instruction_word delay_insn;
  44   sim_events_slip (SD, 1);
  45   DSPC = CIA;
  46   CIA = nia;
  47   STATE |= simDELAYSLOT;
  48   ENGINE_ISSUE_PREFIX_HOOK();
  49   micromips_instruction_decode (SD, CPU, CIA, delayslot_instruction_size);
  50   STATE &= ~simDELAYSLOT;
  51   return target;
  52 }
  53
  54 :function:::address_word:process_isa_mode:address_word target
  55 {
  56   SD->isa_mode = target & 0x1;
  57   return (target & (-(1 << 1)));
  58 }
  59
  60 :function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size
  61 {
  62   GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
  63   return (process_isa_mode (SD_,
  64         delayslot_micromips (SD_, GPR[rs], nia, delayslot_instruction_size)));
  65 }
  66
  67 :function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size
  68 {
  69   RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
  70   return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);
  71 }
  72
  73
  74 :function:::unsigned32:compute_movep_src_reg:int reg
  75 {
  76   switch(reg)
  77     {
  78     case 0: return 0;
  79     case 1: return 17;
  80     case 2: return 2;
  81     case 3: return 3;
  82     case 4: return 16;
  83     case 5: return 18;
  84     case 6: return 19;
  85     case 7: return 20;
  86     default: return 0;
  87     }
  88 }
  89
  90 :function:::unsigned32:compute_andi16_imm:int encoded_imm
  91 {
  92   switch (encoded_imm)
  93     {
  94     case 0: return 128;
  95     case 1: return 1;
  96     case 2: return 2;
  97     case 3: return 3;
  98     case 4: return 4;
  99     case 5: return 7;
 100     case 6: return 8;
 101     case 7: return 15;
 102     case 8: return 16;
 103     case 9: return 31;
 104     case 10: return 32;
 105     case 11: return 63;
 106     case 12: return 64;
 107     case 13: return 255;
 108     case 14: return 32768;
 109     case 15: return 65535;
 110     default: return 0;
 111     }
 112 }
 113
 114 :function:::FP_formats:convert_fmt_micromips:int fmt
 115 {
 116   switch (fmt)
 117     {
 118     case 0: return fmt_single;
 119     case 1: return fmt_double;
 120     case 2: return fmt_ps;
 121     default: return fmt_unknown;
 122     }
 123 }
 124
 125 :function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt
 126 {
 127   switch (fmt)
 128     {
 129     case 0: return fmt_single;
 130     case 1: return fmt_word;
 131     case 2: return fmt_long;
 132     default: return fmt_unknown;
 133     }
 134 }
 135
 136
 137 :function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt
 138 {
 139   switch (fmt)
 140     {
 141     case 0: return fmt_double;
 142     case 1: return fmt_word;
 143     case 2: return fmt_long;
 144     default: return fmt_unknown;
 145     }
 146 }
 147
 148
 149 011011,3.RD,6.IMMEDIATE,1:POOL16E:16::ADDIUR1SP
 150 "addiur1sp r<TRD>, <IMMEDIATE>"
 151 *micromips32:
 152 *micromips64:
 153 {
 154   do_addiu (SD_, SPIDX, TRD, IMMEDIATE << 2);
 155 }
 156
 157
 158 011011,3.RD,3.RS,3.IMMEDIATE,0:POOL16E:16::ADDIUR2
 159 "addiur2 r<TRD>, r<TRS>, <IMM_DEC1>"
 160 *micromips32:
 161 *micromips64:
 162 {
 163   do_addiu (SD_, TRS, TRD, IMM_DEC1);
 164 }
 165
 166
 167 010011,5.RD,4.IMMEDIATE,0:POOL16D:16::ADDIUS5
 168 "addius5 r<RD>, <IMM_DEC2>"
 169 *micromips32:
 170 *micromips64:
 171 {
 172   do_addiu (SD_, RD, RD, IMM_DEC2);
 173 }
 174
 175
 176 010011,9.IMMEDIATE,1:POOL16D:16::ADDIUSP
 177 "addiusp <IMM_DEC3>"
 178 *micromips32:
 179 *micromips64:
 180 {
 181   do_addiu (SD_, SPIDX, SPIDX, IMM_DEC3 << 2);
 182 }
 183
 184
 185 000001,3.RD,3.RT,3.RS,0:POOL16A:16::ADDU16
 186 "addu16 r<TRD>, r<TRS>, r<TRT>"
 187 *micromips32:
 188 *micromips64:
 189 {
 190   do_addu (SD_, TRS, TRT, TRD);
 191 }
 192
 193
 194 001011,3.RD,3.RS,4.IMMEDIATE:MICROMIPS:16::ANDI16
 195 "andi16 r<TRD>, r<TRS>, <IMM_DEC4>"
 196 *micromips32:
 197 *micromips64:
 198 {
 199   do_andi (SD_, TRS, TRD, IMM_DEC4);
 200 }
 201
 202
 203 010001,0010,3.RT,3.RS:POOL16C:16::AND16
 204 "and16 r<TRT>, r<TRS>"
 205 *micromips32:
 206 *micromips64:
 207 {
 208   do_and (SD_, TRS, TRT, TRT);
 209 }
 210
 211
 212 110011,10.IMMEDIATE:MICROMIPS:16::B16
 213 "b16 <IMMEDIATE>"
 214 *micromips32:
 215 *micromips64:
 216 {
 217   NIA = delayslot_micromips (SD_, NIA + (EXTEND11 (IMMEDIATE << 1)),
 218                                   NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 219 }
 220
 221
 222 100011,3.RS,7.IMMEDIATE:MICROMIPS:16::BEQZ16
 223 "beqz16 r<TRS>, <IMMEDIATE>"
 224 *micromips32:
 225 *micromips64:
 226 {
 227   if (GPR[TRS] == 0)
 228     NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),
 229                                     NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 230 }
 231
 232
 233 101011,3.RS,7.IMMEDIATE:MICROMIPS:16::BNEZ16
 234 "bnez16 r<TRS>, <IMMEDIATE>"
 235 *micromips32:
 236 *micromips64:
 237 {
 238   if (GPR[TRS] != 0)
 239     NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),
 240                                     NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 241 }
 242
 243
 244 010001,101000,4.CODE:POOL16C:16::BREAK16
 245 "break16 %#lx<CODE>"
 246 *micromips32:
 247 *micromips64:
 248 {
 249   do_break16 (SD_, instruction_0);
 250 }
 251
 252
 253 010001,01110,5.RS:POOL16C:16::JALR16
 254 "jalr16 r<RS>"
 255 *micromips32:
 256 *micromips64:
 257 {
 258   NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
 259 }
 260
 261
 262 010001,01111,5.RS:POOL16C:16::JALRS16
 263 "jalrs16 r<RS>"
 264 *micromips32:
 265 *micromips64:
 266 {
 267   NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
 268 }
 269
 270
 271 010001,01100,5.RS:POOL16C:16::JR16
 272 "jr16 r<RS>"
 273 *micromips32:
 274 *micromips64:
 275 {
 276   NIA = process_isa_mode (SD_,
 277         delayslot_micromips (SD_, GPR[RS], NIA, MICROMIPS_DELAYSLOT_SIZE_ANY));
 278 }
 279
 280
 281 010001,11000,5.IMMEDIATE:POOL16C:16::JRADDIUSP
 282 "jraddiusp <IMMEDIATE>"
 283 *micromips32:
 284 *micromips64:
 285 {
 286   address_word temp = RA;
 287   do_addiu (SD_, SPIDX, SPIDX, IMMEDIATE << 2);
 288   NIA = process_isa_mode (SD_, temp);
 289 }
 290
 291
 292 010001,01101,5.RS:POOL16C:16::JRC
 293 "jrc r<RS>"
 294 *micromips32:
 295 *micromips64:
 296 {
 297   NIA = process_isa_mode (SD_, GPR[RS]);
 298 }
 299
 300
 301 000010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LBU16
 302 "lbu16 r<TRT>, <IMM_DEC5>(r<TBASE>)"
 303 *micromips32:
 304 *micromips64:
 305 {
 306   /* LBU can have a negative offset.  As the offset argument to do_load is
 307      unsigned we need to do the address calcuation before the function call so
 308      that the load address has been correctly calculated */
 309
 310   GPR[TRT] = do_load (SD_, AccessLength_BYTE, GPR[TBASE] + IMM_DEC5, 0);
 311 }
 312
 313
 314 001010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LHU16
 315 "lhu16 r<TRT>, <IMM_SHIFT_1BIT>(r<TBASE>)"
 316 *micromips32:
 317 *micromips64:
 318 {
 319   GPR[TRT] = do_load (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT);
 320 }
 321
 322
 323 111011,3.RD,7.IMMEDIATE:MICROMIPS:16::LI16
 324 "li16 r<TRD>, <IMM_DEC6>"
 325 *micromips32:
 326 *micromips64:
 327 {
 328   GPR[TRD] = IMM_DEC6;
 329 }
 330
 331
 332 011010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LW16
 333 "lw16 r<TRT>, <IMM_SHIFT_2BIT>(r<TBASE>)"
 334 *micromips32:
 335 *micromips64:
 336 {
 337   GPR[TRT] = EXTEND32 (
 338         do_load (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT));
 339 }
 340
 341 :%s::::LWMREGS:int lwmregs
 342 *micromips32:
 343 *micromips64:
 344 {
 345   if (lwmregs == 3)
 346     return "s0, s1, s2, s3, ra";
 347   else if (lwmregs == 2)
 348     return "s0, s1, s2, ra";
 349   else if (lwmregs == 1)
 350     return "s0, s1, ra";
 351   else if (lwmregs == 0)
 352     return "s0, ra";
 353   else
 354     return "";
 355 }
 356
 357 010001,0100,2.LWMREGS,4.IMMEDIATE:POOL16C:16::LWM16
 358 "lwm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"
 359 *micromips32:
 360 *micromips64:
 361 {
 362   int address = GPR[SPIDX] + IMM_SHIFT_2BIT;
 363   int reg_offset;
 364
 365   for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)
 366     GPR[16 + reg_offset] = EXTEND32 (
 367         do_load (SD_, AccessLength_WORD, address, reg_offset * 4));
 368
 369   RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address, reg_offset * 4));
 370 }
 371
 372
 373 011001,3.RT,7.IMMEDIATE:MICROMIPS:16::LWGP
 374 "lwgp r<TRT>, <IMM_SHIFT_2BIT>(gp)"
 375 *micromips32:
 376 *micromips64:
 377 {
 378   GPR[TRT] = EXTEND32 (
 379         do_load (SD_, AccessLength_WORD, GPR[28], IMM_SHIFT_2BIT));
 380 }
 381
 382
 383 010010,5.RT,5.IMMEDIATE:MICROMIPS:16::LWSP
 384 "lwsp r<RT>, <IMM_SHIFT_2BIT>(sp)"
 385 *micromips32:
 386 *micromips64:
 387 {
 388   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT));
 389 }
 390
 391
 392 010001,10000,5.RD:POOL16C:16::MFHI16
 393 "mfhi16 r<RD>"
 394 *micromips32:
 395 *micromips64:
 396 {
 397   do_mfhi (SD_, RD);
 398 }
 399
 400
 401 010001,10010,5.RD:POOL16C:16::MFLO16
 402 "mflo16 r<RD>"
 403 *micromips32:
 404 *micromips64:
 405 {
 406   do_mflo (SD_, RD);
 407 }
 408
 409
 410 000011,5.RD,5.RS:MICROMIPS:16::MOVE16
 411 "nop":RD==0&&RS==0
 412 "move16 r<RD>, r<RS>"
 413 *micromips32:
 414 *micromips64:
 415 {
 416   GPR[RD] = GPR[RS];
 417 }
 418
 419
 420 :%s::::DESTREGS:int regs
 421 *micromips32:
 422 *micromips64:
 423 {
 424   switch (regs)
 425     {
 426     case 0: return "a1, a2,";
 427     case 1: return "a1, a3,";
 428     case 2: return "a2, a3,";
 429     case 3: return "a0, s5,";
 430     case 4: return "a0, s6,";
 431     case 5: return "a0, a1,";
 432     case 6: return "a0, a2,";
 433     case 7: return "a0, a3,";
 434     default: return "";
 435     }
 436 }
 437
 438 100001,3.DESTREGS,3.RT,3.RS,0:MICROMIPS:16::MOVEP
 439 "movep %s<DESTREGS> r<ERS>, r<ERT>"
 440 *micromips32:
 441 *micromips64:
 442 {
 443   int rd;
 444   int re;
 445   int dest = DESTREGS;
 446
 447   if (dest == 0 || dest == 1)
 448     rd = 5;
 449   else if (dest == 2)
 450     rd = 6;
 451   else
 452     rd = 4;
 453
 454   if (dest == 0 || dest == 6)
 455     re = 6;
 456   else if (dest == 1 || dest == 2 || dest == 7)
 457     re = 7;
 458   else if (dest == 3)
 459     re = 21;
 460   else if (dest == 4)
 461     re = 22;
 462   /* assume dest is 5 */
 463   else
 464     re = 5;
 465
 466   GPR[rd] = GPR[ERS];
 467   GPR[re] = GPR[ERT];
 468 }
 469
 470
 471 010001,0000,3.RT,3.RS:POOL16C:16::NOT16
 472 "not16 r<TRT>, r<TRS>"
 473 *micromips32:
 474 *micromips64:
 475 {
 476   do_nor (SD_, 0, TRS, TRT);
 477 }
 478
 479
 480 010001,0011,3.RT,3.RS:POOL16C:16::OR16
 481 "or16 r<TRT>, r<TRS>"
 482 *micromips32:
 483 *micromips64:
 484 {
 485   do_or (SD_, TRS, TRT, TRT);
 486 }
 487
 488
 489 100010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SB16
 490 "sb16 r<TRT_S>, <IMMEDIATE>(r<TBASE>)"
 491 *micromips32:
 492 *micromips64:
 493 {
 494   do_store (SD_, AccessLength_BYTE, GPR[TBASE], IMMEDIATE, GPR[TRT_S]);
 495 }
 496
 497
 498 010001,101100,4.CODE:POOL16C:16::SDBBP16
 499 "sdbbp16 %#lx<CODE>"
 500 *micromips32:
 501 *micromips64:
 502 {
 503   SignalException (DebugBreakPoint, instruction_0);
 504 }
 505
 506
 507 101010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SH16
 508 "sh16 r<TRT_S>, <IMM_SHIFT_1BIT>(r<TBASE>)"
 509 *micromips32:
 510 *micromips64:
 511 {
 512   do_store (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT, GPR[TRT_S]);
 513 }
 514
 515
 516 001001,3.RD,3.RT,3.SHIFT,0:POOL16B:16::SLL16
 517 "sll16 r<TRD>, r<TRT>, <SHIFT_DEC>"
 518 *micromips32:
 519 *micromips64:
 520 {
 521   do_sll (SD_, TRT, TRD, SHIFT_DEC);
 522 }
 523
 524
 525 001001,3.RD,3.RT,3.SHIFT,1:POOL16B:16::SRL16
 526 "srl16 r<TRD>, r<TRT>, <SHIFT_DEC>"
 527 *micromips32:
 528 *micromips64:
 529 {
 530   do_srl (SD_, TRT, TRD, SHIFT_DEC);
 531 }
 532
 533
 534 000001,3.RD,3.RT,3.RS,1:POOL16A:16::SUBU16
 535 "subu16 r<TRD>, r<TRS>, r<TRT>"
 536 *micromips32:
 537 *micromips64:
 538 {
 539   do_subu (SD_, TRS, TRT, TRD);
 540 }
 541
 542
 543 111010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SW16
 544 "sw16 r<TRT_S>, <IMM_SHIFT_2BIT>(r<TBASE>)"
 545 *micromips32:
 546 *micromips64:
 547 {
 548   do_store (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT, GPR[TRT_S]);
 549 }
 550
 551
 552 110010,5.RT,5.IMMEDIATE:MICROMIPS:16::SWSP
 553 "swsp r<RT>, <IMM_SHIFT_2BIT>(sp)"
 554 *micromips32:
 555 *micromips64:
 556 {
 557   do_store (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT, GPR[RT]);
 558 }
 559
 560
 561 010001,0101,2.LWMREGS,4.IMMEDIATE:POOL16C:16::SWM16
 562 "swm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"
 563 *micromips32:
 564 *micromips64:
 565 {
 566   int address = GPR[SPIDX] + IMM_SHIFT_2BIT;
 567   int reg_offset;
 568
 569   for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)
 570     do_store (SD_, AccessLength_WORD, address, reg_offset * 4,
 571         GPR[16 + reg_offset]);
 572
 573   do_store (SD_, AccessLength_WORD, address, reg_offset * 4, RA);
 574 }
 575
 576
 577 010001,0001,3.RT,3.RS:POOL16C:16::XOR16
 578 "xor16 r<TRT>, r<TRS>"
 579 *micromips32:
 580 *micromips64:
 581 {
 582   do_xor (SD_, TRS, TRT, TRT);
 583 }
 584
 585
 586 000000,5.RT,5.RS,5.RD,00100,010000:POOL32A:32::ADD
 587 "add r<RD>, r<RS>, r<RT>"
 588 *micromips32:
 589 *micromips64:
 590 {
 591   do_add (SD_, RS, RT, RD);
 592 }
 593
 594
 595 000100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDI
 596 "addi r<RT>, r<RS>, <IMMEDIATE>"
 597 *micromips32:
 598 *micromips64:
 599 {
 600   do_addi (SD_, RS, RT, IMMEDIATE);
 601 }
 602
 603
 604 001100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDIU
 605 "li r<RT>, <IMMEDIATE>":RS==0
 606 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 607 *micromips32:
 608 *micromips64:
 609 {
 610   do_addiu (SD_, RS, RT, IMMEDIATE);
 611 }
 612
 613
 614 011110,3.RS,23.IMMEDIATE:MICROMIPS:32::ADDIUPC
 615 "addiupc r<TRS>, <IMM_SHIFT_2BIT>"
 616 *micromips32:
 617 *micromips64:
 618 {
 619   GPR[TRS] = EXTEND32 ((CIA & ~3) + EXTEND25 (IMM_SHIFT_2BIT));
 620 }
 621
 622
 623 000000,5.RT,5.RS,5.RD,00101,010000:POOL32A:32::ADDU
 624 "addu r<RD>, r<RS>, r<RT>"
 625 *micromips32:
 626 *micromips64:
 627 {
 628   do_addu (SD_, RS, RT, RD);
 629 }
 630
 631
 632 000000,5.RT,5.RS,5.RD,01001,010000:POOL32A:32::AND
 633 "and r<RD>, r<RS>, r<RT>"
 634 *micromips32:
 635 *micromips64:
 636 {
 637   do_and (SD_, RS, RT, RD);
 638 }
 639
 640
 641 110100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ANDI
 642 "andi r<RT>, r<RS>, <IMMEDIATE>"
 643 *micromips32:
 644 *micromips64:
 645 {
 646   do_andi (SD_, RS, RT, IMMEDIATE);
 647 }
 648
 649
 650 010000,1110,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32,f::BC1a
 651 "bc1%s<TF> <IMMEDIATE>":CC == 0
 652 "bc1%s<TF> <CC>, <IMMEDIATE>"
 653 *micromips32:
 654 *micromips64:
 655 {
 656   check_fpu (SD_);
 657   if (GETFCC(CC) == TF)
 658     {
 659       address_word dest = NIA + (EXTEND16 (IMMEDIATE) << 1);
 660       NIA = delayslot_micromips (SD_, dest, NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 661     }
 662 }
 663
 664
 665 010000,1010,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32::BC2a
 666 "bc2%s<TF> <CC>, <IMMEDIATE>":CC == 0
 667 "bc2%s<TF> <CC>, <IMMEDIATE>"
 668 *micromips32:
 669 *micromips64:
 670
 671
 672 100101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BEQ
 673 "b <IMMEDIATE>":RT == 0 && RS == 0
 674 "beq r<RS>, r<RT>, <IMMEDIATE>"
 675 *micromips32:
 676 *micromips64:
 677 {
 678   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 679   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 680     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 681                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 682 }
 683
 684 010000,00010,5.RS,16.IMMEDIATE:POOL32I:32::BGEZ
 685 "bgez r<RS>, <IMMEDIATE>"
 686 *micromips32:
 687 *micromips64:
 688 {
 689   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 690   if ((signed_word) GPR[RS] >= 0)
 691     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 692                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 693 }
 694
 695
 696 010000,00111,5.RS,16.IMMEDIATE:POOL32I:32::BEQZC
 697 "beqzc r<RS>, <IMMEDIATE>"
 698 *micromips32:
 699 *micromips64:
 700 {
 701   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 702   if (GPR[RS] == 0)
 703     NIA = NIA + offset;
 704 }
 705
 706
 707 010000,00011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZAL
 708 "bal <IMMEDIATE>":RS == 0
 709 "bgezal r<RS>, <IMMEDIATE>"
 710 *micromips32:
 711 *micromips64:
 712 {
 713   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 714   if (RS == 31)
 715     Unpredictable ();
 716   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;
 717   if ((signed_word) GPR[RS] >= 0)
 718     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 719                                MICROMIPS_DELAYSLOT_SIZE_32);
 720 }
 721
 722
 723 010000,00110,5.RS,16.IMMEDIATE:POOL32I:32::BGTZ
 724 "bgtz r<RS>, <IMMEDIATE>"
 725 *micromips32:
 726 *micromips64:
 727 {
 728   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 729   if ((signed_word) GPR[RS] > 0)
 730     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 731                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 732 }
 733
 734
 735 010000,10011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZALS
 736 "bal <IMMEDIATE>":RS == 0
 737 "bgezals r<RS>, <IMMEDIATE>"
 738 *micromips32:
 739 *micromips64:
 740 {
 741   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 742   if (RS == 31)
 743     Unpredictable ();
 744   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;
 745   if ((signed_word) GPR[RS] >= 0)
 746     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 747                                MICROMIPS_DELAYSLOT_SIZE_16);
 748 }
 749
 750
 751 010000,00100,5.RS,16.IMMEDIATE:POOL32I:32::BLEZ
 752 "blez r<RS>, <IMMEDIATE>"
 753 *micromips32:
 754 *micromips64:
 755 {
 756   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 757   /* NOTE: The branch occurs AFTER the next instruction has been
 758      executed */
 759   if ((signed_word) GPR[RS] <= 0)
 760     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 761                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 762 }
 763
 764
 765 010000,00000,5.RS,16.IMMEDIATE:POOL32I:32::BLTZ
 766 "bltz r<RS>, <IMMEDIATE>"
 767 *micromips32:
 768 *micromips64:
 769 {
 770   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 771   if ((signed_word) GPR[RS] < 0)
 772     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 773                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 774 }
 775
 776
 777 010000,00001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZAL
 778 "bltzal r<RS>, <IMMEDIATE>"
 779 *micromips32:
 780 *micromips64:
 781 {
 782   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 783   if (RS == 31)
 784     Unpredictable ();
 785   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;
 786   /* NOTE: The branch occurs AFTER the next instruction has been
 787      executed */
 788   if ((signed_word) GPR[RS] < 0)
 789     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 790                                MICROMIPS_DELAYSLOT_SIZE_32);
 791 }
 792
 793 010000,10001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZALS
 794 "bltzals r<RS>, <IMMEDIATE>"
 795 *micromips32:
 796 *micromips64:
 797 {
 798   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 799   if (RS == 31)
 800     Unpredictable ();
 801   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;
 802   if ((signed_word) GPR[RS] < 0)
 803     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 804                                MICROMIPS_DELAYSLOT_SIZE_16);
 805 }
 806
 807
 808 101101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BNE
 809 "bne r<RS>, r<RT>, <IMMEDIATE>"
 810 *micromips32:
 811 *micromips64:
 812 {
 813   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 814   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 815     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 816                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 817 }
 818
 819
 820 010000,00101,5.RS,16.IMMEDIATE:POOL32I:32::BNEZC
 821 "bnezc r<RS>, <IMMEDIATE>"
 822 *micromips32:
 823 *micromips64:
 824 {
 825   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 826   if ((signed_word) GPR[RS] != 0)
 827     NIA = NIA + offset;
 828 }
 829
 830
 831 000000,20.CODE,000111:POOL32A:32::BREAK
 832 "break %#lx<CODE>"
 833 *micromips32:
 834 *micromips64:
 835 {
 836   do_break (SD_, instruction_0);
 837 }
 838
 839
 840 001000,5.OP,5.BASE,0110,12.IMMEDIATE:POOL32B:32::CACHE
 841 "cache <OP>, <IMMEDIATE>(r<BASE>)"
 842 *micromips32:
 843 *micromips64:
 844 {
 845   address_word base = GPR[BASE];
 846   address_word offset = EXTEND12 (IMMEDIATE);
 847   address_word vaddr = loadstore_ea (SD_, base, offset);
 848   address_word paddr;
 849   int uncached;
 850   if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
 851                           isTARGET, isREAL))
 852     CacheOp (OP, vaddr, paddr, instruction_0);
 853 }
 854
 855
 856 011000,5.OP,5.BASE,1010011,9.IMMEDIATE:POOL32C:32::CACHEE
 857 "cachee <OP>, <IMMEDIATE>(r<BASE>)"
 858 *micromips32:
 859 *micromips64:
 860
 861
 862 010101,5.RT,5.FS,0001000000,111011:POOL32F:32,f::CFC1
 863 "cfc1 r<RT>, f<FS>"
 864 *micromips32:
 865 *micromips64:
 866 {
 867   do_cfc1 (SD_, RT, FS);
 868 }
 869
 870
 871 000000,5.RT,5.IMPL,1100110100,111100:POOL32A:32::CFC2
 872 "cfc2 r<RT>, <IMPL>"
 873 *micromips32:
 874 *micromips64:
 875
 876
 877 000000,5.RT,5.RS,0100101100,111100:POOL32A:32::CLO
 878 "clo r<RT>, r<RS>"
 879 *micromips32:
 880 *micromips64:
 881 {
 882   do_clo (SD_, RT, RS);
 883 }
 884
 885
 886 000000,5.RT,5.RS,0101101100,111100:POOL32A:32::CLZ
 887 "clz r<RT>, r<RS>"
 888 *micromips32:
 889 *micromips64:
 890 {
 891   do_clz (SD_, RT, RS);
 892 }
 893
 894
 895 000000,23.COFUN,010:POOL32A:32::COP2
 896 "cop2 <COFUN>"
 897 *micromips32:
 898 *micromips64:
 899
 900
 901 010101,5.RT,5.FS,0001100000,111011:POOL32F:32,f::CTC1
 902 "ctc1 r<RT>, f<FS>"
 903 *micromips32:
 904 *micromips64:
 905 {
 906   do_ctc1 (SD_, RT, FS);
 907 }
 908
 909
 910 000000,5.RT,5.IMPL,1101110100,111100:POOL32A:32::CTC2
 911 "ctc2 r<RT>, <IMPL>"
 912 *micromips32:
 913 *micromips64:
 914
 915
 916 000000,00000000001110001101,111100:POOL32A:32::DERET
 917 "deret"
 918 *micromips32:
 919 *micromips64:
 920
 921
 922 000000,00000,5.RS,0100011101,111100:POOL32A:32::DI
 923 "di":RS == 0
 924 "di r<RS>"
 925 *micromips32:
 926 *micromips64:
 927 {
 928   do_di (SD_, RS);
 929 }
 930
 931 000000,5.RT,5.RS,1010101100,111100:POOL32A:32::DIV
 932 "div r<RS>, r<RT>"
 933 *micromips32:
 934 *micromips64:
 935 {
 936   do_div (SD_, RS, RT);
 937 }
 938
 939
 940 000000,5.RT,5.RS,1011101100,111100:POOL32A:32::DIVU
 941 "divu r<RS>, r<RT>"
 942 *micromips32:
 943 *micromips64:
 944 {
 945   do_divu (SD_, RS, RT);
 946 }
 947
 948
 949 000000,00000000000001100000,000000:POOL32A:32::EHB
 950 "ehb"
 951 *micromips32:
 952 *micromips64:
 953
 954
 955 000000,00000,5.RS,0101011101,111100:POOL32A:32::EI
 956 "ei":RS == 0
 957 "ei r<RS>"
 958 *micromips32:
 959 *micromips64:
 960 {
 961   do_ei (SD_, RS);
 962 }
 963
 964 000000,00000000001111001101,111100:POOL32A:32::ERET
 965 "eret"
 966 *micromips32:
 967 *micromips64:
 968 {
 969   if (SR & status_ERL)
 970     {
 971       /* Oops, not yet available */
 972       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
 973       NIA = EPC;
 974       SR &= ~status_ERL;
 975     }
 976   else
 977     {
 978       NIA = EPC;
 979       SR &= ~status_EXL;
 980     }
 981 }
 982
 983
 984 000000,5.RT,5.RS,5.MSBD,5.LSB,101100:POOL32A:32::EXT
 985 "ext r<RT>, r<RS>, <LSB>, <MSBD+1>"
 986 *micromips32:
 987 *micromips64:
 988 {
 989   do_ext (SD_, RT, RS, LSB, MSBD);
 990 }
 991
 992
 993 000000,5.RT,5.RS,5.MSBD,5.LSB,001100:POOL32A:32::INS
 994 "ins r<RT>, r<RS>, <LSB>, <MSBD-LSB+1>"
 995 *micromips32:
 996 *micromips64:
 997 {
 998   do_ins (SD_, RT, RS, LSB, MSBD);
 999 }
1000
1001
1002 110101,26.IMMEDIATE:MICROMIPS:32::J
1003 "j <IMM_SHIFT_1BIT>"
1004 *micromips32:
1005 *micromips64:
1006 {
1007   address_word region = (NIA & MASK (63, 27));
1008   NIA = delayslot_micromips (SD_, region | (IMM_SHIFT_1BIT), NIA,
1009                              MICROMIPS_DELAYSLOT_SIZE_ANY);
1010 }
1011
1012
1013 111101,26.IMMEDIATE:MICROMIPS:32::JAL
1014 "jal <IMM_SHIFT_1BIT>"
1015 *micromips32:
1016 *micromips64:
1017 {
1018   /* NOTE: The region used is that of the delay slot and NOT the
1019      current instruction */
1020   address_word region = (NIA & MASK (63, 27));
1021   NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA,
1022                           MICROMIPS_DELAYSLOT_SIZE_32);
1023 }
1024
1025
1026 011101,26.IMMEDIATE:MICROMIPS:32::JALS
1027 "jals <IMM_SHIFT_1BIT>"
1028 *micromips32:
1029 *micromips64:
1030 {
1031   address_word region = (NIA & MASK (63, 27));
1032   NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA,
1033                           MICROMIPS_DELAYSLOT_SIZE_16);
1034 }
1035
1036 000000,5.RT!0,5.RS,0000111100,111100:POOL32A:32::JALR
1037 "jalr r<RS>":RT == 31
1038 "jalr r<RT>, r<RS>"
1039 *micromips32:
1040 *micromips64:
1041 {
1042   if (RS == RT)
1043     Unpredictable ();
1044   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1045 }
1046
1047 000000,5.RT,5.RS,0100111100,111100:POOL32A:32::JALRS
1048 "jalrs r<RT>, r<RS>"
1049 *micromips32:
1050 *micromips64:
1051 {
1052   if (RS == RT)
1053     Unpredictable ();
1054   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
1055 }
1056
1057
1058 111100,26.IMMEDIATE:MICROMIPS:32::JALX
1059 "jalx <IMM_SHIFT_2BIT>"
1060 *micromips32:
1061 *micromips64:
1062 {
1063   address_word region = (NIA & MASK (63, 26));
1064   NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_2BIT)) | ISA_MODE_MIPS32,
1065                           NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1066   SD->isa_mode = ISA_MODE_MIPS32;
1067 }
1068
1069 000000,00000,5.RS,0000111100,111100:POOL32A:32::JR
1070 "jr r<RS>"
1071 *micromips32:
1072 *micromips64:
1073 {
1074   NIA = process_isa_mode (SD_,
1075                           delayslot_micromips (SD_, GPR[RS], NIA,
1076                                                MICROMIPS_DELAYSLOT_SIZE_32));
1077 }
1078
1079
1080 000000,5.RT,5.RS,0001111100,111100:POOL32A:32::JALR.HB
1081 "jalr.hb r<RT>, r<RS>"
1082 *micromips32:
1083 *micromips64:
1084 {
1085   if (RS == RT)
1086     Unpredictable ();
1087   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1088 }
1089
1090
1091 000000,5.RT,5.RS,0101111100,111100:POOL32A:32::JALRS.HB
1092 "jalrs.hb r<RT>, r<RS>"
1093 *micromips32:
1094 *micromips64:
1095 {
1096   if (RS == RT)
1097     Unpredictable ();
1098   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
1099 }
1100
1101
1102 000000,00000,5.RS,0111111100,111100:POOL32A:32::JR.HB
1103 "jr.hb r<RS>"
1104 *micromips32:
1105 *micromips64:
1106 {
1107   NIA = process_isa_mode (SD_,
1108                           delayslot_micromips (SD_, GPR[RS], NIA,
1109                                                MICROMIPS_DELAYSLOT_SIZE_32));
1110 }
1111
1112
1113 000111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LB
1114 "lb r<RT>, <IMMEDIATE>(r<BASE>)"
1115 *micromips32:
1116 *micromips64:
1117 {
1118   do_lb (SD_, RT, IMMEDIATE, BASE);
1119 }
1120
1121
1122 011000,5.RT,5.BASE,0110100,9.IMMEDIATE:POOL32C:32::LBE
1123 "lbe r<RT>, <IMMEDIATE>(r<BASE>)"
1124 *micromips32:
1125 *micromips64:
1126
1127
1128 000101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LBU
1129 "lbu r<RT>, <IMMEDIATE>(r<BASE>)"
1130 *micromips32:
1131 *micromips64:
1132 {
1133   do_lbu (SD_, RT, IMMEDIATE, BASE);
1134 }
1135
1136
1137 011000,5.RT,5.BASE,0110000,9.IMMEDIATE:POOL32C:32::LBUE
1138 "lbue r<RT>, <IMMEDIATE>(r<BASE>)"
1139 *micromips32:
1140 *micromips64:
1141
1142
1143 101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1a
1144 "ldc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1145 *micromips32:
1146 {
1147   check_fpu (SD_);
1148   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (IMMEDIATE)));
1149 }
1150
1151
1152 101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1b
1153 "ldc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1154 *micromips64:
1155 {
1156   check_fpu (SD_);
1157   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
1158                           EXTEND16 (IMMEDIATE)));
1159 }
1160
1161
1162 001000,5.RT,5.BASE,0010,12.IMMEDIATE:POOL32B:32::LDC2
1163 "ldc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1164 *micromips32:
1165 *micromips64:
1166
1167
1168 001111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LH
1169 "lh r<RT>, <IMMEDIATE>(r<BASE>)"
1170 *micromips32:
1171 *micromips64:
1172 {
1173   do_lh (SD_, RT, IMMEDIATE, BASE);
1174 }
1175
1176
1177 011000,5.RT,5.BASE,0110101,9.IMMEDIATE:POOL32C:32::LHE
1178 "lhe r<RT>, <IMMEDIATE>(r<BASE>)"
1179 *micromips32:
1180 *micromips64:
1181
1182
1183 001101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LHU
1184 "lhu r<RT>, <IMMEDIATE>(r<BASE>)"
1185 *micromips32:
1186 *micromips64:
1187 {
1188   do_lhu (SD_, RT, IMMEDIATE, BASE);
1189 }
1190
1191
1192 011000,5.RT,5.BASE,0110001,9.IMMEDIATE:POOL32C:32::LHUE
1193 "lhue r<RT>, <IMMEDIATE>(r<BASE>)"
1194 *micromips32:
1195 *micromips64:
1196
1197
1198 011000,5.RT,5.BASE,0011,12.IMMEDIATE:POOL32C:32::LL
1199 "ll r<RT>, <IMMEDIATE>(r<BASE>)"
1200 *micromips32:
1201 *micromips64:
1202 {
1203   do_ll (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1204 }
1205
1206
1207 011000,5.RT,5.BASE,0110110,9.IMMEDIATE:POOL32C:32::LLE
1208 "lle r<RT>, <IMMEDIATE>(r<BASE>)"
1209 *micromips32:
1210 *micromips64:
1211
1212
1213 010000,01101,5.RS,16.IMMEDIATE:POOL32I:32::LUI
1214 "lui r<RS>, <IMMEDIATE>"
1215 *micromips32:
1216 *micromips64:
1217 {
1218   do_lui (SD_, RS, IMMEDIATE);
1219 }
1220
1221
1222 010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:32,f::LUXC1
1223 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
1224 *micromips32:
1225 {
1226   do_luxc1_32 (SD_, FD, INDEX, BASE);
1227 }
1228
1229
1230 010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:64,f::LUXC1
1231 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
1232 *micromips64:
1233 {
1234   check_fpu (SD_);
1235   check_u64 (SD_, instruction_0);
1236   do_luxc1_64 (SD_, FD, INDEX, BASE);
1237 }
1238
1239
1240 111111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LW
1241 "lw r<RT>, <IMMEDIATE>(r<BASE>)"
1242 *micromips32:
1243 *micromips64:
1244 {
1245   do_lw (SD_, RT, IMMEDIATE, BASE);
1246 }
1247
1248
1249 100111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LWC1
1250 "lwc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1251 *micromips32:
1252 *micromips64:
1253 {
1254   do_lwc1 (SD_, FT, IMMEDIATE, BASE);
1255 }
1256
1257
1258 001000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32B:32::LWC2
1259 "lwc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1260 *micromips32:
1261 *micromips64:
1262
1263
1264 011000,5.RT,5.BASE,0110111,9.IMMEDIATE:POOL32C:32::LWE
1265 "lwe r<RT>, <IMMEDIATE>(r<BASE>)"
1266 *micromips32:
1267 *micromips64:
1268
1269
1270 011000,5.RT,5.BASE,0110011,9.IMMEDIATE:POOL32C:32::LWEE
1271 "lwee r<RT>, <IMMEDIATE>(r<BASE>)"
1272 *micromips32:
1273 *micromips64:
1274
1275
1276 011000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32C:32::LWL
1277 "lwl r<RT>, <IMMEDIATE>(r<BASE>)"
1278 *micromips32:
1279 *micromips64:
1280 {
1281   do_lwl (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1282 }
1283
1284
1285 011000,5.RT,5.BASE,0110010,9.IMMEDIATE:POOL32C:32::LWLE
1286 "lwle r<RT>, <IMMEDIATE>(r<BASE>)"
1287 *micromips32:
1288 *micromips64:
1289
1290 :%s::::LWM32REGS:int lwmregs
1291 *micromips32:
1292 *micromips64:
1293 {
1294   if (lwmregs & 0x10)
1295     {
1296       switch(lwmregs & 0xf)
1297         {
1298         case 0:
1299           return "ra";
1300         case 1:
1301           return "s0, ra";
1302         case 2:
1303           return "s0, s1, ra";
1304         case 3:
1305           return "s0, s1, s2, ra";
1306         case 4:
1307           return "s0, s1, s2, s3, ra";
1308         case 5:
1309           return "s0, s1, s2, s3, s4, ra";
1310         case 6:
1311           return "s0, s1, s2, s3, s4, s5, ra";
1312         case 7:
1313           return "s0, s1, s2, s3, s4, s5, s6, ra";
1314         case 8:
1315           return "s0, s1, s2, s3, s4, s5, s6, s7, ra";
1316         case 9:
1317           return "s0, s1, s2, s3, s4, s5, s6, s7, s8, ra";
1318         default:
1319           return "";
1320         }
1321     }
1322   else
1323     {
1324       switch(lwmregs & 0xf)
1325         {
1326         case 1:
1327           return "s0";
1328         case 2:
1329           return "s0, s1";
1330         case 3:
1331           return "s0, s1, s2";
1332         case 4:
1333           return "s0, s1, s2, s3";
1334         case 5:
1335           return "s0, s1, s2, s3, s4";
1336         case 6:
1337           return "s0, s1, s2, s3, s4, s5";
1338         case 7:
1339           return "s0, s1, s2, s3, s4, s5, s6";
1340         case 8:
1341           return "s0, s1, s2, s3, s4, s5, s6, s7";
1342         case 9:
1343           return "s0, s1, s2, s3, s4, s5, s6, s7, s8";
1344         default:
1345           return "";
1346         }
1347     }
1348 }
1349
1350 001000,5.LWM32REGS,5.BASE,0101,12.IMMEDIATE:POOL32B:32::LWM32
1351 "lwm32 %s<LWM32REGS>, <IMMEDIATE>(r<BASE>)"
1352 *micromips32:
1353 *micromips64:
1354 {
1355   int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE);
1356   int reg_offset;
1357   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
1358     {
1359       int dst = (reg_offset == 8) ? 30 : 16 + reg_offset;
1360       GPR[dst] = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base,
1361                                     4 * reg_offset));
1362     }
1363
1364   if (LWM32REGS & 0x10)
1365     RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base,
1366                             4 * reg_offset));
1367 }
1368
1369
1370 001000,5.RD,5.BASE,0001,12.IMMEDIATE:POOL32B:32::LWP
1371 "lwp r<RD>, <IMMEDIATE>(r<BASE>)"
1372 *micromips32:
1373 *micromips64:
1374 {
1375   if (BASE == RD || RD == 31)
1376     Unpredictable ();
1377   else
1378     {
1379       do_lw (SD_, RD, EXTEND12 (IMMEDIATE), BASE);
1380       do_lw (SD_, RD + 1, EXTEND12 (IMMEDIATE) + 4, BASE);
1381     }
1382 }
1383
1384
1385 011000,5.RT,5.BASE,0001,12.IMMEDIATE:POOL32C:32::LWR
1386 "lwr r<RT>, <IMMEDIATE>(r<BASE>)"
1387 *micromips32:
1388 *micromips64:
1389 {
1390   do_lwr (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1391 }
1392
1393
1394 011000,5.RT,5.BASE,1110,12.IMMEDIATE:POOL32C:32::LWU
1395 "lwu r<RT>, <IMMEDIATE>(r<BASE>)"
1396 *micromips32:
1397 *micromips64:
1398 {
1399   do_lwu (SD_, RT, IMMEDIATE, BASE, instruction_0);
1400 }
1401
1402
1403 010101,5.INDEX,5.BASE,5.FD,00001,001000:POOL32F:32,f::LWXC1
1404 "lwxc1 f<FD>, <INDEX>(r<BASE>)"
1405 *micromips32:
1406 *micromips64:
1407 {
1408   do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0);
1409 }
1410
1411
1412 000000,5.INDEX,5.BASE,5.RD,00100,011000:POOL32A:32::LWXS
1413 "lwxs r<RD>, r<INDEX>(r<BASE>)"
1414 *micromips32:
1415 *micromips64:
1416 {
1417   GPR[RD] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE],
1418                                GPR[INDEX] * 4));
1419 }
1420
1421
1422 000000,5.RT,5.RS,1100101100,111100:POOL32A:32::MADD
1423 "madd r<RS>, r<RT>"
1424 *micromips32:
1425 *micromips64:
1426 {
1427   do_madd (SD_, RS, RT);
1428 }
1429
1430
1431 000000,5.RT,5.RS,1101101100,111100:POOL32A:32::MADDU
1432 "maddu r<RS>, r<RT>"
1433 *micromips32:
1434 *micromips64:
1435 {
1436   do_maddu (SD_, RS, RT);
1437 }
1438
1439
1440 000000,5.RT,5.RS,00,3.SEL,00011,111100:POOL32A:32::MFC0
1441 "mfc0 r<RS>, r<RT>": SEL == 0
1442 "mfc0 r<RS>, r<RT>, <SEL>"
1443 *micromips32:
1444 *micromips64:
1445 {
1446   DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RS, SEL);
1447 }
1448
1449
1450 010101,5.RT,5.FS,0010000000,111011:POOL32F:32,f::MFC1
1451 "mfc1 r<RT>, f<FS>"
1452 *micromips32:
1453 *micromips64:
1454 {
1455   do_mfc1b (SD_, RT, FS);
1456 }
1457
1458
1459 000000,5.RT,5.IMPL,0100110100,111100:POOL32A:32::MFC2
1460 "mfc2 r<RT>, <IMPL>"
1461 *micromips32:
1462 *micromips64:
1463
1464
1465 010101,5.RT,5.FS,0011000000,111011:POOL32F:32,f::MFHC1
1466 "mfhc1 r<RT>, f<FS>"
1467 *micromips32:
1468 *micromips64:
1469 {
1470   do_mfhc1 (SD_, RT, FS);
1471 }
1472
1473
1474 000000,5.RT,5.IMPL,1000110100,111100:POOL32A:32::MFHC2
1475 "mfhc2 r<RT>, <IMPL>"
1476 *micromips32:
1477 *micromips64:
1478
1479
1480 000000,00000,5.RS,0000110101,111100:POOL32A:32::MFHI
1481 "mfhi r<RS>"
1482 *micromips32:
1483 *micromips64:
1484 {
1485   do_mfhi (SD_, RS);
1486 }
1487
1488
1489 000000,00000,5.RS,0001110101,111100:POOL32A:32::MFLO
1490 "mflo r<RS>"
1491 *micromips32:
1492 *micromips64:
1493 {
1494   do_mflo (SD_, RS);
1495 }
1496
1497
1498 // MOVF
1499 // MOVT
1500 010101,5.RT,5.RS,3.CC,0,1.TF,00101,111011:POOL32F:32::MOVtf
1501 "mov%s<TF> r<RT>, r<RS>, CC"
1502 *micromips32:
1503 *micromips64:
1504 {
1505   do_movtf (SD_, TF, RT, RS, CC);
1506 }
1507
1508
1509 000000,5.RT,5.RS,5.RD,00000,011000:POOL32A:32::MOVN
1510 "movn r<RD>, r<RS>, r<RT>"
1511 *micromips32:
1512 *micromips64:
1513 {
1514   do_movn (SD_, RD, RS, RT);
1515 }
1516
1517
1518 000000,5.RT,5.RS,5.RD,00001,011000:POOL32A:32::MOVZ
1519 "movz r<RD>, r<RS>, r<RT>"
1520 *micromips32:
1521 *micromips64:
1522 {
1523   do_movz (SD_, RD, RS, RT);
1524 }
1525
1526
1527 000000,5.RT,5.RS,1110101100,111100:POOL32A:32::MSUB
1528 "msub r<RS>, r<RT>"
1529 *micromips32:
1530 *micromips64:
1531 {
1532   do_msub (SD_, RS, RT);
1533 }
1534
1535
1536 000000,5.RT,5.RS,1111101100,111100:POOL32A:32::MSUBU
1537 "msubu r<RS>, r<RT>"
1538 *micromips32:
1539 *micromips64:
1540 {
1541   do_msubu (SD_, RS, RT);
1542 }
1543
1544
1545 000000,5.RT,5.RS,00,3.SEL,01011,111100:POOL32A:32::MTC0
1546 "mtc0 r<RS>, r<RT>": SEL == 0
1547 "mtc0 r<RS>, r<RT>, <SEL>"
1548 *micromips32:
1549 *micromips64:
1550 {
1551   DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RS, SEL);
1552 }
1553
1554
1555 010101,5.RT,5.FS,0010100000,111011:POOL32F:32,f::MTC1
1556 "mtc1 r<RT>, f<FS>"
1557 *micromips32:
1558 *micromips64:
1559 {
1560   do_mtc1b (SD_, RT, FS);
1561 }
1562
1563
1564 000000,5.RT,5.IMPL,0101110100,111100:POOL32A:32::MTC2
1565 "mtc2 r<RT>, <IMPL>"
1566 *micromips32:
1567 *micromips64:
1568
1569
1570 010101,5.RT,5.FS,0011100000,111011:POOL32F:32,f::MTHC1
1571 "mthc1 r<RT>, f<FS>"
1572 *micromips32:
1573 *micromips64:
1574 {
1575   do_mthc1 (SD_, RT, FS);
1576 }
1577
1578
1579 000000,5.RT,5.IMPL,1001110100,111100:POOL32A:32::MTHC2
1580 "mthc2 r<RT>, <IMPL>"
1581 *micromips32:
1582 *micromips64:
1583
1584
1585 000000,00000,5.RS,0010110101,111100:POOL32A:32::MTHI
1586 "mthi r<RS>"
1587 *micromips32:
1588 *micromips64:
1589 {
1590   do_mthi (SD_, RS);
1591 }
1592
1593
1594 000000,00000,5.RS,0011110101,111100:POOL32A:32::MTLO
1595 "mtlo r<RS>"
1596 *micromips32:
1597 *micromips64:
1598 {
1599   do_mtlo (SD_, RS);
1600 }
1601
1602
1603 000000,5.RT,5.RS,5.RD,01000,010000:POOL32A:32::MUL
1604 "mul r<RD>, r<RS>, r<RT>"
1605 *micromips32:
1606 *micromips64:
1607 {
1608   do_mul (SD_, RD, RS, RT);
1609 }
1610
1611
1612 000000,5.RT,5.RS,1000101100,111100:POOL32A:32::MULT
1613 "mult r<RS>, r<RT>"
1614 *micromips32:
1615 *micromips64:
1616 {
1617   do_mult (SD_, RS, RT, 0);
1618 }
1619
1620
1621 000000,5.RT,5.RS,1001101100,111100:POOL32A:32::MULTU
1622 "multu r<RS> r<RT>"
1623 *micromips32:
1624 *micromips64:
1625 {
1626   do_multu (SD_, RS, RT, 0);
1627 }
1628
1629
1630 000000,00000000000000000000,000000:POOL32A:32::NOP
1631 "nop"
1632 *micromips32:
1633 *micromips64:
1634 {
1635 }
1636
1637
1638 000000,5.RT,5.RS,5.RD,01011,010000:POOL32A:32::NOR
1639 "nor r<RD>, r<RS>, r<RT>"
1640 *micromips32:
1641 *micromips64:
1642 {
1643   do_nor (SD_, RS, RT, RD);
1644 }
1645
1646
1647 000000,5.RT,5.RS,5.RD,01010,010000:POOL32A:32::OR
1648 "or r<RD>, r<RS>, r<RT>"
1649 *micromips32:
1650 *micromips64:
1651 {
1652   do_or (SD_, RS, RT, RD);
1653 }
1654
1655
1656 010100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ORI
1657 "ori r<RT>, r<RS>, <IMMEDIATE>"
1658 *micromips32:
1659 *micromips64:
1660 {
1661   do_ori (SD_, RS, RT, IMMEDIATE);
1662 }
1663
1664
1665 000000,00000000000010100000,000000:POOL32A:32::PAUSE
1666 "pause"
1667 *micromips32:
1668 *micromips64:
1669
1670
1671 011000,5.HINT,5.BASE,0010,12.IMMEDIATE:POOL32C:32::PREF
1672 "pref <HINT>, <IMMEDIATE>(r<BASE>)"
1673 *micromips32:
1674 *micromips64:
1675 {
1676   do_pref (SD_, HINT, EXTEND12 (IMMEDIATE), BASE);
1677 }
1678
1679
1680 011000,5.HINT,5.BASE,1010010,9.IMMEDIATE:POOL32C:32::PREFE
1681 "prefe <HINT>, <IMMEDIATE>(r<BASE>)"
1682 *micromips32:
1683 *micromips64:
1684
1685
1686 010101,5.INDEX,5.BASE,5.HINT,00110,100000:POOL32F:32::PREFX
1687 "prefx <HINT>, r<INDEX>(r<BASE>)"
1688 *micromips32:
1689 *micromips64:
1690 {
1691   do_prefx (SD_, HINT, INDEX, BASE);
1692 }
1693
1694 000000,5.RT,5.RS,0110101100,111100:POOL32A:32::RDHWR
1695 "rdhwr r<RS>, r<RT>"
1696 *micromips32:
1697 *micromips64:
1698 {
1699   do_rdhwr (SD_, RT, RS);
1700 }
1701
1702 000000,5.RT,5.RS,1110000101,111100:POOL32A:32::RDPGPR
1703 "rdpgpr r<RS>, r<RT>"
1704 *micromips32:
1705 *micromips64:
1706
1707
1708 000000,5.RT,5.RS,5.SHIFT,00011,000000:POOL32A:32::ROTR
1709 "rotr r<RT>, r<RS>, <SHIFT>"
1710 *micromips32:
1711 *micromips64:
1712 {
1713   GPR[RT] = do_ror (SD_, GPR[RS], SHIFT);
1714 }
1715
1716
1717 000000,5.RT,5.RS,5.RD,00011,010000:POOL32A:32::ROTRV
1718 "rotrv r<RD>, r<RT>, r<RS>"
1719 *micromips32:
1720 *micromips64:
1721 {
1722   GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
1723 }
1724
1725
1726 000110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SB
1727 "sb r<RT>, <IMMEDIATE>(r<BASE>)"
1728 *micromips32:
1729 *micromips64:
1730 {
1731   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]);
1732 }
1733
1734
1735 011000,5.RT,5.BASE,1010101,9.IMMEDIATE:POOL32C:32::SBE
1736 "sbe r<RT>, <IMMEDIATE>(r<BASE>)"
1737 *micromips32:
1738 *micromips64:
1739
1740
1741 011000,5.RT,5.BASE,1011,12.IMMEDIATE:POOL32C:32::SC
1742 "sc r<RT>, <IMMEDIATE>(r<BASE>)"
1743 *micromips32:
1744 *micromips64:
1745 {
1746   do_sc (SD_, RT, EXTEND12 (IMMEDIATE), BASE, instruction_0);
1747 }
1748
1749
1750 011000,5.RT,5.BASE,1010110,9.IMMEDIATE:POOL32C:32::SCE
1751 "sce r<RT>, <IMMEDIATE>(r<BASE>)"
1752 *micromips32:
1753 *micromips64:
1754
1755
1756 000000,10.CODE,1101101101,111100:POOL32A:32::SDBBP
1757 "sdbbp %#lx<CODE>"
1758 *micromips32:
1759 *micromips64:
1760 {
1761   SignalException (DebugBreakPoint, instruction_0);
1762 }
1763
1764
1765 101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1a
1766 "sdc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1767 *micromips32:
1768 {
1769   do_sdc1 (SD_, FT, IMMEDIATE, BASE);
1770 }
1771
1772
1773 101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1b
1774 "sdc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1775 *micromips64:
1776 {
1777   check_fpu (SD_);
1778   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (IMMEDIATE),
1779             COP_SD (1, FT));
1780 }
1781
1782
1783 001000,5.RT,5.BASE,1010,12.IMMEDIATE:MICROMIPS:32::SDC2
1784 "sdc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1785 *micromips32:
1786 *micromips64:
1787
1788
1789 000000,5.RT,5.RS,0010101100,111100:POOL32A:32::SEB
1790 "seb r<RT>, r<RS>"
1791 *micromips32:
1792 *micromips64:
1793 {
1794   do_seb (SD_, RT, RS);
1795 }
1796
1797
1798 000000,5.RT,5.RS,0011101100,111100:POOL32A:32::SEH
1799 "seh r<RT>, r<RS>"
1800 *micromips32:
1801 *micromips64:
1802 {
1803   do_seh (SD_, RT, RS);
1804 }
1805
1806
1807 001110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SH
1808 "sh r<RT>, <IMMEDIATE>(r<BASE>)"
1809 *micromips32:
1810 *micromips64:
1811 {
1812   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (IMMEDIATE),
1813             GPR[RT]);
1814 }
1815
1816
1817 011000,5.RT,5.BASE,1010100,9.IMMEDIATE:POOL32C:32::SHE
1818 "she r<RT>, <IMMEDIATE>(r<BASE>)"
1819 *micromips32:
1820 *micromips64:
1821
1822
1823 000000,5.RT!0,5.RS!0,5.SHIFT,00000,000000:POOL32A:32::SLL
1824 "sll r<RT>, r<RS>, <SHIFT>"
1825 *micromips32:
1826 *micromips64:
1827 {
1828   do_sll (SD_, RS, RT, SHIFT);
1829 }
1830
1831
1832 000000,5.RT,5.RS,5.RD,00000,010000:POOL32A:32::SLLV
1833 "sllv r<RD>, r<RT>, r<RS>"
1834 *micromips32:
1835 *micromips64:
1836 {
1837   do_sllv (SD_, RS, RT, RD);
1838 }
1839
1840
1841 000000,5.RT,5.RS,5.RD,01101,010000:POOL32A:32::SLT
1842 "slt r<RD>, r<RS>, r<RT>"
1843 *micromips32:
1844 *micromips64:
1845 {
1846   do_slt (SD_, RS, RT, RD);
1847 }
1848
1849
1850 100100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTI
1851 "slti r<RT>, r<RS>, <IMMEDIATE>"
1852 *micromips32:
1853 *micromips64:
1854 {
1855   do_slti (SD_, RS, RT, IMMEDIATE);
1856 }
1857
1858
1859 101100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTIU
1860 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
1861 *micromips32:
1862 *micromips64:
1863 {
1864   do_sltiu (SD_, RS, RT, IMMEDIATE);
1865 }
1866
1867
1868 000000,5.RT,5.RS,5.RD,01110,010000:POOL32A:32::SLTU
1869 "sltu r<RD>, r<RS>, r<RT>"
1870 *micromips32:
1871 *micromips64:
1872 {
1873   do_sltu (SD_, RS, RT, RD);
1874 }
1875
1876
1877 000000,5.RT,5.RS,5.SHIFT,00010,000000:POOL32A:32::SRA
1878 "sra r<RT>, r<RS>, <SHIFT>"
1879 *micromips32:
1880 *micromips64:
1881 {
1882   do_sra (SD_, RS, RT, SHIFT);
1883 }
1884
1885
1886 000000,5.RT,5.RS,5.RD,00010,010000:POOL32A:32::SRAV
1887 "srav r<RD>, r<RT>, r<RS>"
1888 *micromips32:
1889 *micromips64:
1890 {
1891   do_srav (SD_, RS, RT, RD);
1892 }
1893
1894
1895 000000,5.RT,5.RS,5.SHIFT,00001,000000:POOL32A:32::SRL
1896 "srl r<RT>, r<RS>, <SHIFT>"
1897 *micromips32:
1898 *micromips64:
1899 {
1900   do_srl (SD_, RS, RT, SHIFT);
1901 }
1902
1903
1904 000000,5.RT,5.RS,5.RD,00001,010000:POOL32A:32::SRLV
1905 "srlv r<RD>, r<RT>, r<RS>"
1906 *micromips32:
1907 *micromips64:
1908 {
1909   do_srlv (SD_, RS, RT, RD);
1910 }
1911
1912
1913 000000,00000000000000100000,000000:POOL32A:32::SSNOP
1914 "ssnop"
1915 *micromips32:
1916 *micromips64:
1917 {
1918 }
1919
1920
1921 000000,5.RT,5.RS,5.RD,00110,010000:POOL32A:32::SUB
1922 "sub r<RD>, r<RS>, r<RT>"
1923 *micromips32:
1924 *micromips64:
1925 {
1926   do_sub (SD_, RD, RS, RT);
1927 }
1928
1929
1930 000000,5.RT,5.RS,5.RD,00111,010000:POOL32A:32::SUBU
1931 "subu r<RD>, r<RS>, r<RT>"
1932 *micromips32:
1933 *micromips64:
1934 {
1935   do_subu (SD_, RS, RT, RD);
1936 }
1937
1938
1939 010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:32,f::SUXC1
1940 "suxc1 f<FD>, r<INDEX>(r<BASE>)"
1941 *micromips32:
1942 {
1943   do_suxc1_32 (SD_, FD, INDEX, BASE);
1944 }
1945
1946
1947 010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:64,f::SUXC1
1948 "suxc1 f<FD>, r<INDEX>(r<BASE>)"
1949 *micromips64:
1950 {
1951   check_fpu (SD_);
1952   check_u64 (SD_, instruction_0);
1953   do_suxc1_64 (SD_, FD, INDEX, BASE);
1954 }
1955
1956 111110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SW
1957 "sw r<RT>, <IMMEDIATE>(r<BASE>)"
1958 *micromips32:
1959 *micromips64:
1960 {
1961   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]);
1962 }
1963
1964
1965 100110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SWC1
1966 "swc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1967 *micromips32:
1968 *micromips64:
1969 {
1970   do_swc1 (SD_, FT, IMMEDIATE, BASE, instruction_0);
1971 }
1972
1973
1974 001000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32B:32::SWC2
1975 "swc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1976 *micromips32:
1977 *micromips64:
1978
1979
1980 011000,5.RT,5.BASE,1010111,9.IMMEDIATE:POOL32C:32::SWE
1981 "swe r<RT>, <IMMEDIATE>(r<BASE>)"
1982 *micromips32:
1983 *micromips64:
1984
1985
1986 011000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32C:32::SWL
1987 "swl r<RT>, <IMMEDIATE>(r<BASE>)"
1988 *micromips32:
1989 *micromips64:
1990 {
1991   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE),
1992                  GPR[RT]);
1993 }
1994
1995
1996 011000,5.RT,5.BASE,1010000,9.IMMEDIATE:POOL32C:32::SWLE
1997 "swle r<RT>, <IMMEDIATE>(r<BASE>)"
1998 *micromips32:
1999 *micromips64:
2000
2001
2002 001000,5.LWM32REGS,5.BASE,1101,12.IMMEDIATE:POOL32B:32::SWM32
2003 "swm32 %s<LWM32REGS>, <IMMEDIATE>(r<BASE>)"
2004 *micromips32:
2005 *micromips64:
2006 {
2007   int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE);
2008   int reg_offset;
2009   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2010     {
2011       int src = (reg_offset == 8) ? 30 : 16 + reg_offset;
2012       do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset,
2013                 GPR[src]);
2014     }
2015
2016   if (LWM32REGS & 0x10)
2017     do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset, RA);
2018 }
2019
2020
2021 001000,5.RS1,5.BASE,1001,12.IMMEDIATE:POOL32B:32::SWP
2022 "swp r<RS1>, <IMMEDIATE>(r<BASE>)"
2023 *micromips32:
2024 *micromips64:
2025 {
2026   if (RS1 == 31)
2027     Unpredictable ();
2028   else
2029     {
2030       do_sw (SD_, RS1, EXTEND12 (IMMEDIATE), BASE);
2031       do_sw (SD_, RS1 + 1, EXTEND12 (IMMEDIATE) + 4, BASE);
2032     }
2033 }
2034
2035
2036 011000,5.RT,5.BASE,1001,12.IMMEDIATE:POOL32C:32::SWR
2037 "swr r<RT>, <IMMEDIATE>(r<BASE>)"
2038 *micromips32:
2039 *micromips64:
2040 {
2041   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE),
2042                   GPR[RT]);
2043 }
2044
2045
2046 011000,5.RT,5.BASE,1010001,9.IMMEDIATE:POOL32C:32::SWRE
2047 "swre r<RT>, <IMMEDIATE>(r<BASE>)"
2048 *micromips32:
2049 *micromips64:
2050
2051
2052 010101,5.INDEX,5.BASE,5.FD,00010,001000:POOL32F:32,f::SWXC1
2053 "swxc1 f<FD>, r<INDEX>(r<BASE>)"
2054 *micromips32:
2055 *micromips64:
2056 {
2057   do_swxc1 (SD_, FD, INDEX, BASE, instruction_0);
2058 }
2059
2060
2061 000000,00000,5.STYPE,0110101101,111100:POOL32A:32::SYNC
2062 "sync <STYPE>"
2063 *micromips32:
2064 *micromips64:
2065 {
2066   SyncOperation (STYPE);
2067 }
2068
2069
2070 010000,10000,5.BASE,16.IMMEDIATE:POOL32I:32::SYNCI
2071 "synci <IMMEDIATE>(r<BASE>)"
2072 *micromips32:
2073 *micromips64:
2074 {
2075 }
2076
2077 000000,10.CODE,1000101101,111100:POOL32A:32::SYSCALL
2078 "syscall %#lx<CODE>"
2079 *micromips32:
2080 *micromips64:
2081 {
2082   SignalException (SystemCall, instruction_0);
2083 }
2084
2085
2086 000000,5.RT,5.RS,4.CODE,000000,111100:POOL32A:32::TEQ
2087 "teq r<RS>, r<RT>"
2088 *micromips32:
2089 *micromips64:
2090 {
2091   do_teq (SD_, RS, RT, instruction_0);
2092 }
2093
2094
2095 010000,01110,5.RS,16.IMMEDIATE:POOL32I:32::TEQI
2096 "teqi r<RS>, <IMMEDIATE>"
2097 *micromips32:
2098 *micromips64:
2099 {
2100   do_teqi (SD_, RS, IMMEDIATE, instruction_0);
2101 }
2102
2103
2104 000000,5.RT,5.RS,4.CODE,001000,111100:POOL32A:32::TGE
2105 "tge r<RS>, r<RT>"
2106 *micromips32:
2107 *micromips64:
2108 {
2109   do_tge (SD_, RS, RT, instruction_0);
2110 }
2111
2112
2113 010000,01001,5.RS,16.IMMEDIATE:POOL32I:32::TGEI
2114 "tgei r<RS>, <IMMEDIATE>"
2115 *micromips32:
2116 *micromips64:
2117 {
2118   do_tgei (SD_, RS, IMMEDIATE, instruction_0);
2119 }
2120
2121
2122 010000,01011,5.RS,16.IMMEDIATE:POOL32I:32::TGEIU
2123 "tgeiu r<RS>, <IMMEDIATE>"
2124 *micromips32:
2125 *micromips64:
2126 {
2127   do_tgeiu (SD_, RS, IMMEDIATE, instruction_0);
2128 }
2129
2130
2131 000000,5.RT,5.RS,4.CODE,010000,111100:POOL32A:32::TGEU
2132 "tgeu r<RS>, r<RT>"
2133 *micromips32:
2134 *micromips64:
2135 {
2136   do_tgeu (SD_, RS, RT, instruction_0);
2137 }
2138
2139
2140 000000,00000000000000001101,111100:POOL32A:32::TLBP
2141 "tlbp"
2142 *micromips32:
2143 *micromips64:
2144
2145
2146 000000,00000000000001001101,111100:POOL32A:32::TLBR
2147 "tlbr"
2148 *micromips32:
2149 *micromips64:
2150
2151
2152 000000,00000000000010001101,111100:POOL32A:32::TLBWI
2153 "tlbwi"
2154 *micromips32:
2155 *micromips64:
2156
2157
2158 000000,00000000000011001101,111100:POOL32A:32::TLBWR
2159 "tlbwr"
2160 *micromips32:
2161 *micromips64:
2162
2163
2164 000000,5.RT,5.RS,4.CODE,100000,111100:POOL32A:32::TLT
2165 "tlt r<RS>, r<RT>, %#lx<CODE>"
2166 *micromips32:
2167 *micromips64:
2168 {
2169   do_tlt (SD_, RS, RT, instruction_0);
2170 }
2171
2172
2173 010000,01000,5.RS,16.IMMEDIATE:POOL32I:32::TLTI
2174 "tlti r<RS>, <IMMEDIATE>"
2175 *micromips32:
2176 *micromips64:
2177 {
2178   do_tlti (SD_, RS, IMMEDIATE, instruction_0);
2179 }
2180
2181
2182 010000,01010,5.RS,16.IMMEDIATE:POOL32I:32::TLTIU
2183 "tltiu r<RS>, <IMMEDIATE>"
2184 *micromips32:
2185 *micromips64:
2186 {
2187   do_tltiu (SD_, RS, IMMEDIATE, instruction_0);
2188 }
2189
2190
2191 000000,5.RT,5.RS,4.CODE,101000,111100:POOL32A:32::TLTU
2192 "tltu r<RS>, r<RT>"
2193 *micromips32:
2194 *micromips64:
2195 {
2196   do_tltu (SD_, RS, RT, instruction_0);
2197 }
2198
2199
2200 000000,5.RT,5.RS,4.CODE,110000,111100:POOL32A:32::TNE
2201 "tne r<RS>, r<RT>"
2202 *micromips32:
2203 *micromips64:
2204 {
2205   do_tne (SD_, RS, RT, instruction_0);
2206 }
2207
2208
2209 010000,01100,5.RS,16.IMMEDIATE:POOL32I:32::TNEI
2210 "tnei r<RS>, <IMMEDIATE>"
2211 *micromips32:
2212 *micromips64:
2213 {
2214   do_tnei (SD_, RS, IMMEDIATE, instruction_0);
2215 }
2216
2217
2218 000000,10.CODE,1001001101,111100:POOL32A:32::WAIT
2219 "wait"
2220 *micromips32:
2221 *micromips64:
2222
2223
2224 000000,5.RT,5.RS,1111000101,111100:POOL32A:32::WRPGPR
2225 "wrpgpr r<RS>, r<RT>"
2226 *micromips32:
2227 *micromips64:
2228
2229
2230 000000,5.RT,5.RS,0111101100,111100:POOL32A:32::WSBH
2231 "wsbh r<RT>, r<RS>"
2232 *micromips32:
2233 *micromips64:
2234 {
2235   do_wsbh (SD_, RT, RS);
2236 }
2237
2238
2239 000000,5.RT,5.RS,5.RD,01100,010000:POOL32A:32::XOR
2240 "xor r<RD>, r<RS>, r<RT>"
2241 *micromips32:
2242 *micromips64:
2243 {
2244   do_xor (SD_, RS, RT, RD);
2245 }
2246
2247
2248 011100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::XORI
2249 "xori r<RT>, r<RS>, <IMMEDIATE>"
2250 *micromips32:
2251 *micromips64:
2252 {
2253   do_xori (SD_, RS, RT, IMMEDIATE);
2254 }
2255
2256
2257 :%s::::FMT_MICROMIPS:int fmt
2258 {
2259   switch (fmt)
2260     {
2261     case 0: return "s";
2262     case 1: return "d";
2263     case 2: return "ps";
2264     default: return "?";
2265     }
2266 }
2267
2268
2269 :%s::::FMT_MICROMIPS_CVT_D:int fmt
2270 {
2271   switch (fmt)
2272     {
2273     case 0: return "s";
2274     case 1: return "w";
2275     case 2: return "l";
2276     default: return "?";
2277     }
2278 }
2279
2280
2281 :%s::::FMT_MICROMIPS_CVT_S:int fmt
2282 {
2283   switch (fmt)
2284     {
2285     case 0: return "d";
2286     case 1: return "w";
2287     case 2: return "l";
2288     default: return "?";
2289     }
2290 }
2291
2292
2293 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0001101,111011:POOL32F:32,f::ABS.fmt
2294 "abs.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2295 *micromips32:
2296 *micromips64:
2297 {
2298   do_abs_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2299               instruction_0);
2300 }
2301
2302
2303 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,110000:POOL32F:32,f::ADD.fmt
2304 "add.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2305 *micromips32:
2306 *micromips64:
2307 {
2308   do_add_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2309               instruction_0);
2310 }
2311
2312
2313 010101,5.FT,5.FS,5.FD,5.RS,011001:POOL32F:32,f::ALNV.PS
2314 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
2315 *micromips32:
2316 *micromips64:
2317 {
2318   do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0);
2319 }
2320
2321
2322 010101,5.FT,5.FS,3.CC,0,2.FMT_MICROMIPS!3,4.COND,111100:POOL32F:32,f::C.cond.fmt
2323 "c.%s<COND>.%s<FMT_MICROMIPS> f<FS>, f<FT>":CC == 0
2324 "c.%s<COND>.%s<FMT_MICROMIPS> <CC>, f<FS>, f<FT>"
2325 *micromips32:
2326 *micromips64:
2327 {
2328   do_c_cond_fmt (SD_, COND, convert_fmt_micromips (SD_, FMT_MICROMIPS), CC,
2329                  FS, FT, instruction_0);
2330 }
2331
2332
2333 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001100,111011:POOL32F:32,f::CEIL.L.fmt
2334 "ceil.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2335 *micromips32:
2336 *micromips64:
2337 {
2338   do_ceil_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS, instruction_0);
2339 }
2340
2341
2342 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01101100,111011:POOL32F:32,f::CEIL.W.fmt
2343 "ceil.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2344 *micromips32:
2345 *micromips64:
2346 {
2347   do_ceil_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS, instruction_0);
2348 }
2349
2350
2351 010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_D!3,1001101,111011:POOL32F:32,f::CVT.D.fmt
2352 "cvt.d.%s<FMT_MICROMIPS_CVT_D> f<FT>, f<FS>"
2353 *micromips32:
2354 *micromips64:
2355 {
2356   do_cvt_d_fmt (SD_, convert_fmt_micromips_cvt_d (SD_, FMT_MICROMIPS_CVT_D),
2357                 FT, FS, instruction_0);
2358 }
2359
2360
2361 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00000100,111011:POOL32F:32,f::CVT.L.fmt
2362 "cvt.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2363 *micromips32:
2364 *micromips64:
2365 {
2366   do_cvt_l_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0);
2367 }
2368
2369
2370 010101,5.FT,5.FS,5.FD,00110,000000:POOL32F:32,f::CVT.PS.S
2371 "cvt.ps.s f<FD>, f<FS>, f<FT>"
2372 *micromips32:
2373 *micromips64:
2374 {
2375   do_cvt_ps_s (SD_, FD, FS, FT, instruction_0);
2376 }
2377
2378
2379 010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_S!3,1101101,111011:POOL32F:32,f::CVT.S.fmt
2380 "cvt.s.%s<FMT_MICROMIPS_CVT_S> f<FT>, f<FS>"
2381 *micromips32:
2382 *micromips64:
2383 {
2384   do_cvt_s_fmt (SD_, convert_fmt_micromips_cvt_s (SD_, FMT_MICROMIPS_CVT_S),
2385                 FT, FS, instruction_0);
2386 }
2387
2388
2389 010101,5.FT,5.FS,00,10000100,111011:POOL32F:32,f::CVT.S.PL
2390 "cvt.s.pl f<FT>, f<FS>"
2391 *micromips32:
2392 *micromips64:
2393 {
2394   do_cvt_s_pl (SD_, FT, FS, instruction_0);
2395 }
2396
2397
2398 010101,5.FT,5.FS,00,10100100,111011:POOL32F:32,f::CVT.S.PU
2399 "cvt.s.pu f<FT>, f<FS>"
2400 *micromips32:
2401 *micromips64:
2402 {
2403   do_cvt_s_pu (SD_, FT, FS, instruction_0);
2404 }
2405
2406
2407 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00100100,111011:POOL32F:32,f::CVT.W.fmt
2408 "cvt.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2409 *micromips32:
2410 *micromips64:
2411 {
2412   do_cvt_w_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0);
2413 }
2414
2415
2416 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!2!3,11,110000:POOL32F:32,f::DIV.fmt
2417 "div.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2418 *micromips32:
2419 *micromips64:
2420 {
2421   do_div_fmt (SD_, FMT_MICROMIPS, FD, FS, FT, instruction_0);
2422 }
2423
2424
2425 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001100,111011:POOL32F:32,f::FLOOR.L.fmt
2426 "floor.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2427 *micromips32:
2428 *micromips64:
2429 {
2430   do_floor_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2431 }
2432
2433
2434 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101100,111011:POOL32F:32,f::FLOOR.W.fmt
2435 "floor.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2436 *micromips32:
2437 *micromips64:
2438 {
2439   do_floor_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2440 }
2441
2442
2443 010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MADD.fmt
2444 "madd.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2445 *micromips32:
2446 *micromips64:
2447 {
2448   do_madd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2449                FT, instruction_0);
2450 }
2451
2452 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0000001,111011:POOL32F:32,f::MOV.fmt
2453 "mov.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2454 *micromips32:
2455 *micromips64:
2456 {
2457   do_mov_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2458               instruction_0);
2459 }
2460
2461
2462 010101,5.FT,5.FS,3.CC,00,2.FMT_MICROMIPS!3,00,1.TF,100000:POOL32F:32,f::MOVtf.fmt
2463 "mov%s<TF>.%s<FMT_MICROMIPS> f<FT>, f<FS>, <CC>"
2464 *micromips32:
2465 *micromips64:
2466 {
2467   do_movtf_fmt (SD_, TF, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT,
2468                 FS, CC);
2469 }
2470
2471
2472 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,111000:POOL32F:32,f::MOVN.fmt
2473 "movn.%s<FMT_MICROMIPS> f<FD>, f<FS>, r<FT>"
2474 *micromips32:
2475 *micromips64:
2476 {
2477   do_movn_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT);
2478 }
2479
2480 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,111000:POOL32F:32,f::MOVZ.fmt
2481 "movz.%s<FMT_MICROMIPS> f<FD>, f<FS>, r<FT>"
2482 *micromips32:
2483 *micromips64:
2484 {
2485   do_movz_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT);
2486 }
2487
2488
2489 010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MSUB.fmt
2490 "msub.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2491 *micromips32:
2492 *micromips64:
2493 {
2494   do_msub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2495                FT, instruction_0);
2496 }
2497
2498 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,10,110000:POOL32F:32,f::MUL.fmt
2499 "mul.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2500 *micromips32:
2501 *micromips64:
2502 {
2503   do_mul_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2504               instruction_0);
2505 }
2506
2507
2508 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0101101,111011:POOL32F:32,f::NEG.fmt
2509 "neg.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2510 *micromips32:
2511 *micromips64:
2512 {
2513   do_neg_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2514               instruction_0);
2515 }
2516
2517
2518 010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMADD.fmt
2519 "nmadd.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2520 *micromips32:
2521 *micromips64:
2522 {
2523   do_nmadd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2524                 FT, instruction_0);
2525 }
2526
2527 010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMSUB.fmt
2528 "nmsub.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2529 *micromips32:
2530 *micromips64:
2531 {
2532   do_nmsub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2533                 FT, instruction_0);
2534 }
2535
2536
2537 010101,5.FT,5.FS,5.FD,00010,000000:POOL32F:32,f::PLL.PS
2538 "pll.ps f<FD>, f<FS>, f<FT>"
2539 *micromips32:
2540 *micromips64:
2541 {
2542   do_pll_ps (SD_, FD, FS, FT, instruction_0);
2543 }
2544
2545
2546 010101,5.FT,5.FS,5.FD,00011,000000:POOL32F:32,f::PLU.PS
2547 "plu.ps f<FD>, f<FS>, f<FT>"
2548 *micromips32:
2549 *micromips64:
2550 {
2551   do_plu_ps (SD_, FD, FS, FT, instruction_0);
2552 }
2553
2554
2555 010101,5.FT,5.FS,5.FD,00100,000000:POOL32F:32,f::PUL.PS
2556 "pul.ps f<FD>, f<FS>, f<FT>"
2557 *micromips32:
2558 *micromips64:
2559 {
2560   do_pul_ps (SD_, FD, FS, FT, instruction_0);
2561 }
2562
2563
2564 010101,5.FT,5.FS,5.FD,00101,000000:POOL32F:32,f::PUU.PS
2565 "puu.ps f<FD>, f<FS>, f<FT>"
2566 *micromips32:
2567 *micromips64:
2568 {
2569   do_puu_ps (SD_, FD, FS, FT, instruction_0);
2570 }
2571
2572
2573 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001000,111011:POOL32F:32,f::RECIP.fmt
2574 "recip.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2575 *micromips32:
2576 *micromips64:
2577 {
2578   do_recip_fmt (SD_, FMT_MICROMIPS, FT, FS);
2579 }
2580
2581
2582 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11001100,111011:POOL32F:32,f::ROUND.L.fmt
2583 "round.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2584 *micromips32:
2585 *micromips64:
2586 {
2587   do_round_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2588 }
2589
2590
2591 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11101100,111011:POOL32F:32,f::ROUND.W.fmt
2592 "round.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2593 *micromips32:
2594 *micromips64:
2595 {
2596   do_round_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2597 }
2598
2599
2600 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001000,111011:POOL32F:32,f::RSQRT.fmt
2601 "rsqrt.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2602 *micromips32:
2603 *micromips64:
2604 {
2605   do_rsqrt_fmt (SD_, FMT_MICROMIPS, FT, FS);
2606 }
2607
2608
2609 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101000,111011:POOL32F:32,f::SQRT.fmt
2610 "sqrt.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2611 *micromips32:
2612 *micromips64:
2613 {
2614   do_sqrt_fmt (SD_, FMT_MICROMIPS, FT, FS);
2615 }
2616
2617
2618 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,110000:POOL32F:32,f::SUB.fmt
2619 "sub.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2620 *micromips32:
2621 *micromips64:
2622 {
2623   do_sub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2624               instruction_0);
2625 }
2626
2627
2628 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10001100,111011:POOL32F:32,f::TRUNC.L.fmt
2629 "trunc.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2630 *micromips32:
2631 *micromips64:
2632 {
2633   do_trunc_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2634 }
2635
2636
2637 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10101100,111011:POOL32F:32,f::TRUNC.W.fmt
2638 "trunc.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2639 *micromips32:
2640 *micromips64:
2641 {
2642   do_trunc_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2643 }
2644
2645 001000,5.LWM32REGS,5.BASE,0111,12.OFFSET:POOL32B:64::LDM
2646 "ldm %s<LWM32REGS>, <OFFSET>(r<BASE>)"
2647 *micromips64:
2648 {
2649   int address_base = GPR[BASE] + EXTEND12 (OFFSET);
2650   int reg_offset;
2651   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2652     {
2653       int dst = (reg_offset == 8) ? 30 : 16 + reg_offset;
2654       GPR[dst] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base,
2655                                     8 * reg_offset));
2656     }
2657
2658   if (LWM32REGS & 0x10)
2659     RA = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base,
2660                             8 * reg_offset));
2661 }
2662
2663 001000,5.RD,5.BASE,0100,12.OFFSET:POOL32B:64::LDP
2664 "ldp r<RD>, <OFFSET>(r<BASE>)"
2665 *micromips64:
2666 {
2667   if (BASE == RD || RD == 31)
2668     Unpredictable ();
2669   else
2670     {
2671       check_u64 (SD_, instruction_0);
2672       GPR[RD] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
2673                                    EXTEND12 (OFFSET)));
2674       GPR[RD + 1] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
2675                                        EXTEND12 (OFFSET) + 8));
2676     }
2677 }
2678
2679 001000,5.LWM32REGS,5.BASE,1111,12.OFFSET:POOL32B:64::SDM
2680 "sdm %s<LWM32REGS>, <OFFSET>(r<BASE>)"
2681 *micromips64:
2682 {
2683   int address_base = GPR[BASE] + EXTEND12 (OFFSET);
2684   int reg_offset;
2685   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2686     {
2687       int src = (reg_offset == 8) ? 30 : 16 + reg_offset;
2688       do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset,
2689                 GPR[src]);
2690     }
2691
2692   if (LWM32REGS & 0x10)
2693     do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset, RA);
2694 }
2695
2696 001000,5.RD,5.BASE,1100,12.OFFSET:POOL32B:64::SDP
2697 "sdp r<RD>, <OFFSET>(r<BASE>)"
2698 *micromips64:
2699 {
2700   if (RD == 31)
2701     Unpredictable ();
2702   else
2703     {
2704       check_u64 (SD_, instruction_0);
2705       do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
2706                 GPR[RD]);
2707       do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET) + 8,
2708                 GPR[RD + 1]);
2709     }
2710 }
2711
2712 010110,5.RT,5.RS,5.RD,00,100010000:POOL32S:64::DADD
2713 "dadd r<RD>, r<RS>, r<RT>"
2714 *micromips64:
2715 {
2716   check_u64 (SD_, instruction_0);
2717   do_dadd (SD_, RD, RS, RT);
2718 }
2719
2720 010110,5.RT,5.RS,10.IMMEDIATE,011100:POOL32S:64::DADDI
2721 "daddi r<RT>, r<RS>, <IMMEDIATE>"
2722 *micromips64:
2723 {
2724   check_u64 (SD_, instruction_0);
2725   do_daddi (SD_, RT, RS, IMMEDIATE);
2726 }
2727
2728 010111,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:64::DADDIU
2729 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
2730 *micromips64:
2731 {
2732   check_u64 (SD_, instruction_0);
2733   do_daddiu (SD_, RS, RT, IMMEDIATE);
2734 }
2735
2736 010110,5.RT,5.RS,5.RD,00,101010000:POOL32S:64::DADDU
2737 "daddu r<RD>, r<RS>, r<RT>"
2738 *micromips64:
2739 {
2740   check_u64 (SD_, instruction_0);
2741   do_daddu (SD_, RS, RT, RD);
2742 }
2743
2744 010110,5.RT,5.RS,0100101100,111100:POOL32S:64::DCLO
2745 "dclo r<RT>, r<RS>"
2746 *micromips64:
2747 {
2748   check_u64 (SD_, instruction_0);
2749   do_dclo (SD_, RT, RS);
2750 }
2751
2752 010110,5.RT,5.RS,0101101100,111100:POOL32S:64::DCLZ
2753 "dclz r<RT>, r<RS>"
2754 *micromips64:
2755 {
2756   check_u64 (SD_, instruction_0);
2757   do_dclz (SD_, RT, RS);
2758 }
2759
2760 010110,5.RT,5.RS,1010101100,111100:POOL32S:64::DDIV
2761 "ddiv r<RS>, r<RT>"
2762 *micromips64:
2763 {
2764   check_u64 (SD_, instruction_0);
2765   do_ddiv (SD_, RS, RT);
2766 }
2767
2768 010110,5.RT,5.RS,1011101100,111100:POOL32S:64::DDIVU
2769 "ddivu r<RS>, r<RT>"
2770 *micromips64:
2771 {
2772   check_u64 (SD_, instruction_0);
2773   do_ddivu (SD_, RS, RT);
2774 }
2775
2776 010110,5.RT,5.RS,5.SIZE,5.LSB,101100:POOL32S:64::DEXT
2777 "dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
2778 *micromips64:
2779 {
2780   check_u64 (SD_, instruction_0);
2781   do_dext (SD_, RT, RS, LSB, SIZE);
2782 }
2783
2784 010110,5.RT,5.RS,5.SIZE,5.LSB,100100:POOL32S:64::DEXTM
2785 "dextm r<RT>, r<RS>, <LSB>, <SIZE+33>"
2786 *micromips64:
2787 {
2788   check_u64 (SD_, instruction_0);
2789   do_dextm (SD_, RT, RS, LSB, SIZE);
2790 }
2791
2792 010110,5.RT,5.RS,5.SIZE,5.LSB,010100:POOL32S:64::DEXTU
2793 "dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>"
2794 *micromips64:
2795 {
2796   check_u64 (SD_, instruction_0);
2797   do_dextu (SD_, RT, RS, LSB, SIZE);
2798 }
2799
2800 010110,5.RT,5.RS,5.MSB,5.LSB,001100:POOL32S:64::DINS
2801 "dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
2802 *micromips64:
2803 {
2804   check_u64 (SD_, instruction_0);
2805   do_dins (SD_, RT, RS, LSB, MSB);
2806 }
2807
2808 010110,5.RT,5.RS,5.MSB,5.LSB,000100:POOL32S:64::DINSM
2809 "dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>"
2810 *micromips64:
2811 {
2812   check_u64 (SD_, instruction_0);
2813   do_dinsm (SD_, RT, RS, LSB, MSB);
2814 }
2815
2816 010110,5.RT,5.RS,5.MSB,5.LSB,110100:POOL32S:64::DINSU
2817 "dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>"
2818 *micromips64:
2819 {
2820   check_u64 (SD_, instruction_0);
2821   do_dinsu (SD_, RT, RS, LSB, MSB);
2822 }
2823
2824 010110,5.RT,5.RS,00,3.SEL,00011,111100:POOL32S:64::DMFC0
2825 "dmfc0 r<RT>, r<RS>": SEL == 0
2826 "dmfc0 r<RT>, r<RS>, <SEL>"
2827 *micromips64:
2828 {
2829   check_u64 (SD_, instruction_0);
2830   DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RS, SEL);
2831 }
2832
2833 010101,5.RT,5.FS,00,10010000,111011:POOL32F:64::DMFC1
2834 "dmfc1 r<RT>, f<FS>"
2835 *micromips64:
2836 {
2837   check_fpu (SD_);
2838   check_u64 (SD_, instruction_0);
2839   do_dmfc1b (SD_, RT, FS);
2840 }
2841
2842 010110,5.RT,5.RS,00,3.SEL,01011,111100:POOL32S:64::DMTC0
2843 "dmtc0 r<RT>, r<RS>": SEL == 0
2844 "dmtc0 r<RT>, r<RS>, <SEL>"
2845 *micromips64:
2846 {
2847   check_u64 (SD_, instruction_0);
2848   DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RS, SEL);
2849 }
2850
2851 010101,5.RT,5.FS,00,10110000,111011:POOL32F:64::DMTC1
2852 "dmtc1 r<RT>, f<FS>"
2853 *micromips64:
2854 {
2855   check_fpu (SD_);
2856   check_u64 (SD_, instruction_0);
2857   do_dmtc1b (SD_, RT, FS);
2858 }
2859
2860 010110,5.RT,5.RS,1000101100,111100:POOL32S:64::DMULT
2861 "dmult r<RS>, r<RT>"
2862 *micromips64:
2863 {
2864   check_u64 (SD_, instruction_0);
2865   do_dmult (SD_, RS, RT, 0);
2866 }
2867
2868 010110,5.RT,5.RS,1001101100,111100:POOL32S:64::DMULTU
2869 "dmultu r<RS>, r<RT>"
2870 *micromips64:
2871 {
2872   check_u64 (SD_, instruction_0);
2873   do_dmultu (SD_, RS, RT, 0);
2874 }
2875
2876 010110,5.RT,5.RS,5.SA,00,011000000:POOL32S:64::DROTR
2877 "drotr r<RT>, r<RS>, <SA>"
2878 *micromips64:
2879 {
2880   check_u64 (SD_, instruction_0);
2881   GPR[RT] = do_dror (SD_, GPR[RS], SA);
2882 }
2883
2884 010110,5.RT,5.RS,5.SA,00,011001000:POOL32S:64::DROTR32
2885 "drotr32 r<RT>, r<RS>, <SA+32>"
2886 *micromips64:
2887 {
2888   check_u64 (SD_, instruction_0);
2889   GPR[RT] = do_dror (SD_, GPR[RS], SA + 32);
2890 }
2891
2892 010110,5.RT,5.RS,5.RD,00,011010000:POOL32S:64::DROTRV
2893 "drotrv r<RD>, r<RT>, r<RS>"
2894 *micromips64:
2895 {
2896   check_u64 (SD_, instruction_0);
2897   GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
2898 }
2899
2900 010110,5.RT,5.RS,0111101100,111100:POOL32S:64::DSBH
2901 "dsbh r<RT>, r<RS>"
2902 *micromips64:
2903 {
2904   check_u64 (SD_, instruction_0);
2905   do_dsbh (SD_, RT, RS);
2906 }
2907
2908 010110,5.RT,5.RS,1111101100,111100:POOL32S:64::DSHD
2909 "dshd r<RT>, r<RS>"
2910 *micromips64:
2911 {
2912   check_u64 (SD_, instruction_0);
2913   do_dshd (SD_, RS, RT);
2914 }
2915
2916 010110,5.RT,5.RS,5.SA,00,000000000:POOL32S:64::DSLL
2917 "dsll r<RT>, r<RS>, <SA>"
2918 *micromips64:
2919 {
2920   check_u64 (SD_, instruction_0);
2921   do_dsll (SD_, RS, RT, SA);
2922 }
2923
2924 010110,5.RT,5.RS,5.SA,00,000001000:POOL32S:64::DSLL32
2925 "dsll32 r<RT>, r<RS>, <SA>"
2926 *micromips64:
2927 {
2928   check_u64 (SD_, instruction_0);
2929   do_dsll32 (SD_, RT, RS, SA);
2930 }
2931
2932 010110,5.RT,5.RS,5.RD,00,000010000:POOL32S:64::DSLLV
2933 "dsllv r<RD>, r<RT>, r<RS>"
2934 *micromips64:
2935 {
2936   check_u64 (SD_, instruction_0);
2937   do_dsllv (SD_, RS, RT, RD);
2938 }
2939
2940 010110,5.RT,5.RS,5.SA,00,010000000:POOL32S:64::DSRA
2941 "dsra r<RT>, r<RS>, <SA>"
2942 *micromips64:
2943 {
2944   check_u64 (SD_, instruction_0);
2945   do_dsra (SD_, RS, RT, SA);
2946 }
2947
2948 010110,5.RT,5.RS,5.SA,00,010001000:POOL32S:64::DSRA32
2949 "dsra32 r<RT>, r<RS>, <SA>"
2950 *micromips64:
2951 {
2952   check_u64 (SD_, instruction_0);
2953   do_dsra32 (SD_, RT, RS, SA);
2954 }
2955
2956 010110,5.RT,5.RS,5.RD,00,010010000:POOL32S:64::DSRAV
2957 "dsrav r<RD>, r<RS>, r<RT>"
2958 *micromips64:
2959 {
2960   check_u64 (SD_, instruction_0);
2961   do_dsrav (SD_, RS, RT, RD);
2962 }
2963
2964 010110,5.RT,5.RS,5.SA,00,001000000:POOL32S:64::DSRL
2965 "dsrl r<RT>, r<RS>, <SA>"
2966 *micromips64:
2967 {
2968   check_u64 (SD_, instruction_0);
2969   do_dsrl (SD_, RS, RT, SA);
2970 }
2971
2972 010110,5.RT,5.RS,5.SA,00,001001000:POOL32S:64::DSRL32
2973 "dsrl32 r<RT>, r<RS>, <SA>"
2974 *micromips64:
2975 {
2976   check_u64 (SD_, instruction_0);
2977   do_dsrl32 (SD_, RT, RS, SA);
2978 }
2979
2980 010110,5.RT,5.RS,5.RD,00,001010000:POOL32S:64::DSRLV
2981 "dsrlv r<RD>, r<RT>, r<RS>"
2982 *micromips64:
2983 {
2984   check_u64 (SD_, instruction_0);
2985   do_dsrlv (SD_, RS, RT, RD);
2986 }
2987
2988 010110,5.RT,5.RS,5.RD,00,110001000:POOL32S:64::DSUB
2989 "dsub r<RD>, r<RS>, r<RT>"
2990 *micromips64:
2991 {
2992   check_u64 (SD_, instruction_0);
2993   do_dsub (SD_, RD, RS, RT);
2994 }
2995
2996 010110,5.RT,5.RS,5.RD,00,111001000:POOL32S:64::DSUBU
2997 "dsubu r<RD>, r<RS>, r<RT>"
2998 *micromips64:
2999 {
3000   check_u64 (SD_, instruction_0);
3001   do_dsubu (SD_, RS, RT, RD);
3002 }
3003
3004 110111,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::LD
3005 "ld r<RT>, <OFFSET>(r<BASE>)"
3006 *micromips64:
3007 {
3008   check_u64 (SD_, instruction_0);
3009   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3010                                EXTEND16 (OFFSET)));
3011 }
3012
3013 011000,5.RT,5.BASE,0100,12.OFFSET:POOL32C:64::LDL
3014 "ldl r<RT>, <OFFSET>(r<BASE>)"
3015 *micromips64:
3016 {
3017   check_u64 (SD_, instruction_0);
3018   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3019                           EXTEND12 (OFFSET), GPR[RT]);
3020 }
3021
3022 011000,5.RT,5.BASE,0101,12.OFFSET:POOL32C:64::LDR
3023 "ldr r<RT>, <OFFSET>(r<BASE>)"
3024 *micromips64:
3025 {
3026   check_u64 (SD_, instruction_0);
3027   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3028                            EXTEND12 (OFFSET), GPR[RT]);
3029 }
3030
3031 010101,5.INDEX,5.BASE,5.FD,00,011001000:POOL32F:64,f::LDXC1
3032 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3033 *micromips64:
3034 {
3035   check_fpu (SD_);
3036   check_u64 (SD_, instruction_0);
3037   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3038 }
3039
3040 011000,5.RT,5.BASE,0111,12.OFFSET:POOL32C:64::LLD
3041 "lld r<RT>, <OFFSET>(r<BASE>)"
3042 *micromips64:
3043 {
3044   check_u64 (SD_, instruction_0);
3045   do_lld (SD_, RT, OFFSET, BASE);
3046 }
3047
3048 011000,5.RT,5.BASE,1111,12.OFFSET:POOL32C:64::SCD
3049 "scd r<RT>, <OFFSET>(r<BASE>)"
3050 *micromips64:
3051 {
3052   check_u64 (SD_, instruction_0);
3053   do_scd (SD_, RT, OFFSET, BASE);
3054 }
3055
3056 110110,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::SD
3057 "sd r<RT>, <OFFSET>(r<BASE>)"
3058 *micromips64:
3059 {
3060   check_u64 (SD_, instruction_0);
3061   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET),
3062             GPR[RT]);
3063 }
3064
3065 011000,5.RT,5.BASE,1100,12.OFFSET:POOL32C:64::SDL
3066 "sdl r<RT>, <OFFSET>(r<BASE>)"
3067 *micromips64:
3068 {
3069   check_u64 (SD_, instruction_0);
3070   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
3071                  GPR[RT]);
3072 }
3073
3074 011000,5.RT,5.BASE,1101,12.OFFSET:POOL32C:64::SDR
3075 "sdr r<RT>, <OFFSET>(r<BASE>)"
3076 *micromips64:
3077 {
3078   check_u64 (SD_, instruction_0);
3079   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
3080                   GPR[RT]);
3081 }
3082
3083 010101,5.INDEX,5.BASE,5.FD,00,100001000:POOL32F:64,f::SDXC1
3084 "sdxc1 f<FD>, r<INDEX>(r<BASE>)"
3085 *micromips64:
3086 {
3087   check_fpu (SD_);
3088   check_u64 (SD_, instruction_0);
3089   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX],
3090             COP_SD (1, FD));
3091 }