3 // Simulator definition for the MIPS16e instructions.
4 // Copyright (C) 2005 Free Software Foundation, Inc.
5 // Contributed by Nigel Stephens (nigel@mips.com) and
6 // David Ung (davidu@mips.com) of MIPS Technologies.
8 // This file is part of GDB, the GNU debugger.
10 // This program is free software; you can redistribute it and/or modify
11 // it under the terms of the GNU General Public License as published by
12 // the Free Software Foundation; either version 2, or (at your option)
15 // This program is distributed in the hope that it will be useful,
16 // but WITHOUT ANY WARRANTY; without even the implied warranty of
17 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 // GNU General Public License for more details.
20 // You should have received a copy of the GNU General Public License along
21 // with this program; if not, write to the Free Software Foundation, Inc.,
22 // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 11101,3.RX,100,10001:RR:16::SEB
29 TRACE_ALU_INPUT1 (GPR[TRX]);
30 GPR[TRX] = EXTEND8 (GPR[TRX]);
31 TRACE_ALU_RESULT (GPR[TRX]);
35 11101,3.RX,101,10001:RR:16::SEH
39 TRACE_ALU_INPUT1 (GPR[TRX]);
40 GPR[TRX] = EXTEND16 (GPR[TRX]);
41 TRACE_ALU_RESULT (GPR[TRX]);
44 11101,3.RX,110,10001:RR:16::SEW
48 check_u64 (SD_, instruction_0);
49 TRACE_ALU_INPUT1 (GPR[TRX]);
50 GPR[TRX] = EXTEND32 (GPR[TRX]);
51 TRACE_ALU_RESULT (GPR[TRX]);
54 11101,3.RX,000,10001:RR:16::ZEB
58 TRACE_ALU_INPUT1 (GPR[TRX]);
59 GPR[TRX] = (unsigned_word)(unsigned8)(GPR[TRX]);
60 TRACE_ALU_RESULT (GPR[TRX]);
63 11101,3.RX,001,10001:RR:16::ZEH
67 TRACE_ALU_INPUT1 (GPR[TRX]);
68 GPR[TRX] = (unsigned_word)(unsigned16)(GPR[TRX]);
69 TRACE_ALU_RESULT (GPR[TRX]);
72 11101,3.RX,010,10001:RR:16::ZEW
76 check_u64 (SD_, instruction_0);
77 TRACE_ALU_INPUT1 (GPR[TRX]);
78 GPR[TRX] = (unsigned_word)(unsigned32)(GPR[TRX]);
79 TRACE_ALU_RESULT (GPR[TRX]);
83 11101,3.RX,100,00000:RR:16::JRC
91 11101,000,101,00000:RR:16::JRCRA
99 11101,3.RX,110,00000:RR:16::JALRC
108 // format routines for save/restore
123 :%s::::XSREGS:int xsregs
127 return "s2,s3,s4,s5,s6,s7,s8,";
129 return "s2,s3,s4,s5,s6,s7,";
131 return "s2,s3,s4,s5,s6,";
133 return "s2,s3,s4,s5,";
143 :%s::::AREGS:int aregs
146 // Fixme: how is the arg/static distinction made by the assembler?
147 static const char * const aregstr[16] = {
164 return aregstr[aregs];
167 :compute:::int:SFRAME:FS:((FS == 0) ? 128 \: (FS << 3))
168 :compute:::int:BFRAME:FSHI,FSLO:(((FSHI << 4) | FSLO) << 3)
170 :function:::void:do_save:int xsregs, int aregs, int ras0s1, int framesize
177 /* writes are in the same order as the hardware description... */
179 case 0: case 1: case 2: case 3: case 11:
182 case 4: case 5: case 6: case 7:
185 case 8: case 9: case 10:
195 sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
198 do_store (SD_, AccessLength_WORD, temp, 0, GPR[4]);
200 do_store (SD_,AccessLength_WORD, temp, 4 , GPR[5]);
202 do_store (SD_,AccessLength_WORD, temp, 8 , GPR[6]);
204 do_store (SD_,AccessLength_WORD, temp, 12, GPR[7]);
211 do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[31]);
215 do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[30]);
217 do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[23]);
219 do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[22]);
221 do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[21]);
223 do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[20]);
225 do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[19]);
227 do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[18]);
231 do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[17]);
233 do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[16]);
236 case 0: case 4: case 8: case 12: case 14:
239 case 1: case 5: case 9: case 13:
242 case 2: case 6: case 10:
252 sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
255 do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[7]);
257 do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[6]);
259 do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[5]);
261 do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[4]);
267 GPR[29] -= framesize;
270 01100,100,1,3.RAS,4.FS:I8:16::SAVE
271 "save %s<RAS>,<SFRAME>"
274 do_save (SD_, 0, 0, RAS, SFRAME);
278 11110,3.XSREGS,4.FSHI,4.AREGS + 01100,100,1,3.RAS,4.FSLO:EXT-I8:16::SAVE
279 "save %s<RAS>%s<XSREGS>%s<AREGS><BFRAME>"
282 do_save (SD_, XSREGS, AREGS, RAS, BFRAME);
286 :function:::void:do_restore:int xsregs, int aregs, int ras0s1, int framesize
289 unsigned_word temp, temp2;
292 temp = GPR[29] + framesize;
295 /* reads are in the same order as the hardware description... */
298 GPR[31] = EXTEND32 (do_load(SD_, AccessLength_WORD, temp -= 4, 0));
302 GPR[30] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
304 GPR[23] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
306 GPR[22] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
308 GPR[21] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
310 GPR[20] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
312 GPR[19] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
314 GPR[18] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
318 GPR[17] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
320 GPR[16] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
323 case 0: case 4: case 8: case 12: case 14:
326 case 1: case 5: case 9: case 13:
329 case 2: case 6: case 10:
339 sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
342 GPR[7] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
344 GPR[6] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
346 GPR[5] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
348 GPR[4] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
357 01100,100,0,3.RAS,4.FS:I8:16::RESTORE
358 "restore %s<RAS>,<SFRAME>"
361 do_restore (SD_,0,0,RAS,SFRAME);
364 11110,3.XSREGS,4.FSHI,4.AREGS + 01100,100,0,3.RAS,4.FSLO:EXT-I8:16::RESTORE
365 "restore %s<RAS>%s<XSREGS>%s<AREGS><BFRAME>"
368 do_restore (SD_,XSREGS,AREGS,RAS,BFRAME);