2 /* MIPS Simulator FPU (CoProcessor 1) support.
3 Copyright (C) 2002-2015 Free Software Foundation, Inc.
4 Originally created by Cygnus Solutions. Extensive modifications,
5 including paired-single operation support and MIPS-3D support
6 contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
9 This file is part of GDB, the GNU debugger.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 /* XXX: The following notice should be removed as soon as is practical: */
25 /* Floating Point Support for gdb MIPS simulators
27 This file is part of the MIPS sim
29 THIS SOFTWARE IS NOT COPYRIGHTED
32 Cygnus offers the following for use in the public domain. Cygnus
33 makes no warranty with regard to the software or it's performance
34 and the user accepts the software "AS IS" with all faults.
36 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
37 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
38 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
40 (Originally, this code was in interp.c)
45 /* Within cp1.c we refer to sim_cpu directly. */
47 #define SD CPU_STATE(cpu)
49 /*-- FPU support routines ---------------------------------------------------*/
51 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
52 formats conform to ANSI/IEEE Std 754-1985.
54 SINGLE precision floating:
55 seeeeeeeefffffffffffffffffffffff
60 SINGLE precision fixed:
61 siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
65 DOUBLE precision floating:
66 seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
71 DOUBLE precision fixed:
72 siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
76 PAIRED SINGLE precision floating:
77 seeeeeeeefffffffffffffffffffffffseeeeeeeefffffffffffffffffffffff
82 Note: upper = [63..32], lower = [31..0]
85 /* Extract packed single values: */
86 #define FP_PS_upper(v) (((v) >> 32) & (unsigned)0xFFFFFFFF)
87 #define FP_PS_lower(v) ((v) & (unsigned)0xFFFFFFFF)
88 #define FP_PS_cat(u,l) (((unsigned64)((u) & (unsigned)0xFFFFFFFF) << 32) \
89 | (unsigned64)((l) & 0xFFFFFFFF))
91 /* Explicit QNaN values. */
92 #define FPQNaN_SINGLE (0x7FBFFFFF)
93 #define FPQNaN_WORD (0x7FFFFFFF)
94 #define FPQNaN_DOUBLE (UNSIGNED64 (0x7FF7FFFFFFFFFFFF))
95 #define FPQNaN_LONG (UNSIGNED64 (0x7FFFFFFFFFFFFFFF))
96 #define FPQNaN_PS (FP_PS_cat (FPQNaN_SINGLE, FPQNaN_SINGLE))
98 static const char *fpu_format_name (FP_formats fmt);
100 static const char *fpu_rounding_mode_name (int rm);
104 value_fpr (sim_cpu *cpu,
112 /* Treat unused register values, as fixed-point 64bit values. */
113 if (fmt == fmt_unknown)
116 /* If request to read data as "unknown", then use the current
118 fmt = FPR_STATE[fpr];
124 /* For values not yet accessed, set to the desired format. */
125 if (fmt < fmt_uninterpreted)
127 if (FPR_STATE[fpr] == fmt_uninterpreted)
129 FPR_STATE[fpr] = fmt;
131 printf ("DBG: Register %d was fmt_uninterpreted. Now %s\n", fpr,
132 fpu_format_name (fmt));
135 else if (fmt != FPR_STATE[fpr])
137 sim_io_eprintf (SD, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
138 fpr, fpu_format_name (FPR_STATE[fpr]),
139 fpu_format_name (fmt), pr_addr (cia));
140 FPR_STATE[fpr] = fmt_unknown;
144 if (FPR_STATE[fpr] == fmt_unknown)
146 /* Set QNaN value: */
149 case fmt_single: value = FPQNaN_SINGLE; break;
150 case fmt_double: value = FPQNaN_DOUBLE; break;
151 case fmt_word: value = FPQNaN_WORD; break;
152 case fmt_long: value = FPQNaN_LONG; break;
153 case fmt_ps: value = FPQNaN_PS; break;
154 default: err = -1; break;
157 else if (SizeFGR () == 64)
161 case fmt_uninterpreted_32:
164 value = (FGR[fpr] & 0xFFFFFFFF);
167 case fmt_uninterpreted_64:
168 case fmt_uninterpreted:
184 case fmt_uninterpreted_32:
187 value = (FGR[fpr] & 0xFFFFFFFF);
190 case fmt_uninterpreted_64:
191 case fmt_uninterpreted:
196 /* Even register numbers only. */
198 printf ("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
199 fpr + 1, pr_uword64 ((uword64) FGR[fpr+1]),
200 fpr, pr_uword64 ((uword64) FGR[fpr]));
202 value = ((((uword64) FGR[fpr+1]) << 32)
203 | (FGR[fpr] & 0xFFFFFFFF));
207 SignalException (ReservedInstruction, 0);
212 SignalException (ReservedInstruction, 0);
222 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR ()");
225 printf ("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d\n",
226 fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia),
234 store_fpr (sim_cpu *cpu,
243 printf ("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d, \n",
244 fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia),
248 if (SizeFGR () == 64)
252 case fmt_uninterpreted_32:
253 fmt = fmt_uninterpreted;
256 if (STATE_VERBOSE_P (SD))
258 "Warning: PC 0x%s: interp.c store_fpr DEADCODE\n",
260 FGR[fpr] = (((uword64) 0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
261 FPR_STATE[fpr] = fmt;
264 case fmt_uninterpreted_64:
265 fmt = fmt_uninterpreted;
266 case fmt_uninterpreted:
271 FPR_STATE[fpr] = fmt;
275 FPR_STATE[fpr] = fmt_unknown;
284 case fmt_uninterpreted_32:
285 fmt = fmt_uninterpreted;
288 FGR[fpr] = (value & 0xFFFFFFFF);
289 FPR_STATE[fpr] = fmt;
292 case fmt_uninterpreted_64:
293 fmt = fmt_uninterpreted;
294 case fmt_uninterpreted:
299 /* Even register numbers only. */
300 FGR[fpr+1] = (value >> 32);
301 FGR[fpr] = (value & 0xFFFFFFFF);
302 FPR_STATE[fpr + 1] = fmt;
303 FPR_STATE[fpr] = fmt;
307 FPR_STATE[fpr] = fmt_unknown;
308 FPR_STATE[fpr ^ 1] = fmt_unknown;
309 SignalException (ReservedInstruction, 0);
314 FPR_STATE[fpr] = fmt_unknown;
315 SignalException (ReservedInstruction, 0);
319 FPR_STATE[fpr] = fmt_unknown;
326 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR ()");
329 printf ("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",
330 fpr, pr_uword64 (FGR[fpr]), fpu_format_name (fmt));
337 /* CP1 control/status register access functions. */
340 test_fcsr (sim_cpu *cpu,
345 cause = (FCSR & fcsr_CAUSE_mask) >> fcsr_CAUSE_shift;
346 if ((cause & ((FCSR & fcsr_ENABLES_mask) >> fcsr_ENABLES_shift)) != 0
347 || (cause & (1 << UO)))
349 SignalExceptionFPE();
354 value_fcr(sim_cpu *cpu,
358 unsigned32 value = 0;
362 case 0: /* FP Implementation and Revision Register. */
365 case 25: /* FP Condition Codes Register (derived from FCSR). */
366 value = (FCR31 & fcsr_FCC_mask) >> fcsr_FCC_shift;
367 value = (value & 0x1) | (value >> 1); /* Close FCC gap. */
369 case 26: /* FP Exceptions Register (derived from FCSR). */
370 value = FCR31 & (fcsr_CAUSE_mask | fcsr_FLAGS_mask);
372 case 28: /* FP Enables Register (derived from FCSR). */
373 value = FCR31 & (fcsr_ENABLES_mask | fcsr_RM_mask);
374 if ((FCR31 & fcsr_FS) != 0)
377 case 31: /* FP Control/Status Register (FCSR). */
378 value = FCR31 & ~fcsr_ZERO_mask;
382 return (EXTEND32 (value));
386 store_fcr(sim_cpu *cpu,
396 case 25: /* FP Condition Codes Register (stored into FCSR). */
397 v = (v << 1) | (v & 0x1); /* Adjust for FCC gap. */
398 FCR31 &= ~fcsr_FCC_mask;
399 FCR31 |= ((v << fcsr_FCC_shift) & fcsr_FCC_mask);
401 case 26: /* FP Exceptions Register (stored into FCSR). */
402 FCR31 &= ~(fcsr_CAUSE_mask | fcsr_FLAGS_mask);
403 FCR31 |= (v & (fcsr_CAUSE_mask | fcsr_FLAGS_mask));
406 case 28: /* FP Enables Register (stored into FCSR). */
407 if ((v & fenr_FS) != 0)
411 FCR31 &= (fcsr_FCC_mask | fcsr_CAUSE_mask | fcsr_FLAGS_mask);
412 FCR31 |= (v & (fcsr_FS | fcsr_ENABLES_mask | fcsr_RM_mask));
415 case 31: /* FP Control/Status Register (FCSR). */
416 FCR31 = v & ~fcsr_ZERO_mask;
423 update_fcsr (sim_cpu *cpu,
425 sim_fpu_status status)
427 FCSR &= ~fcsr_CAUSE_mask;
431 unsigned int cause = 0;
433 /* map between sim_fpu codes and MIPS FCSR */
434 if (status & (sim_fpu_status_invalid_snan
435 | sim_fpu_status_invalid_isi
436 | sim_fpu_status_invalid_idi
437 | sim_fpu_status_invalid_zdz
438 | sim_fpu_status_invalid_imz
439 | sim_fpu_status_invalid_cmp
440 | sim_fpu_status_invalid_sqrt
441 | sim_fpu_status_invalid_cvi))
443 if (status & sim_fpu_status_invalid_div0)
445 if (status & sim_fpu_status_overflow)
447 if (status & sim_fpu_status_underflow)
449 if (status & sim_fpu_status_inexact)
452 /* Implicit clearing of other bits by unimplemented done by callers. */
453 if (status & sim_fpu_status_unimplemented)
457 FCSR |= (cause << fcsr_CAUSE_shift);
458 test_fcsr (cpu, cia);
459 FCSR |= ((cause & ~(1 << UO)) << fcsr_FLAGS_shift);
465 rounding_mode(int rm)
472 /* Round result to nearest representable value. When two
473 representable values are equally near, round to the value
474 that has a least significant bit of zero (i.e. is even). */
475 round = sim_fpu_round_near;
478 /* Round result to the value closest to, and not greater in
479 magnitude than, the result. */
480 round = sim_fpu_round_zero;
483 /* Round result to the value closest to, and not less than,
485 round = sim_fpu_round_up;
488 /* Round result to the value closest to, and not greater than,
490 round = sim_fpu_round_down;
494 fprintf (stderr, "Bad switch\n");
500 /* When the FS bit is set, MIPS processors return zero for
501 denormalized results and optionally replace denormalized inputs
502 with zero. When FS is clear, some implementation trap on input
503 and/or output, while other perform the operation in hardware. */
504 static sim_fpu_denorm
505 denorm_mode(sim_cpu *cpu)
507 sim_fpu_denorm denorm;
509 /* XXX: FIXME: Eventually should be CPU model dependent. */
511 denorm = sim_fpu_denorm_zero;
518 /* Comparison operations. */
520 static sim_fpu_status
521 fp_test(unsigned64 op1,
530 sim_fpu_status status = 0;
531 int less, equal, unordered;
533 /* The format type has already been checked: */
538 sim_fpu_32to (&wop1, op1);
539 sim_fpu_32to (&wop2, op2);
544 sim_fpu_64to (&wop1, op1);
545 sim_fpu_64to (&wop2, op2);
549 fprintf (stderr, "Bad switch\n");
553 if (sim_fpu_is_nan (&wop1) || sim_fpu_is_nan (&wop2))
555 if ((cond & (1 << 3)) ||
556 sim_fpu_is_snan (&wop1) || sim_fpu_is_snan (&wop2))
557 status = sim_fpu_status_invalid_snan;
566 status |= sim_fpu_abs (&wop1, &wop1);
567 status |= sim_fpu_abs (&wop2, &wop2);
569 equal = sim_fpu_is_eq (&wop1, &wop2);
570 less = !equal && sim_fpu_is_lt (&wop1, &wop2);
573 *condition = (((cond & (1 << 2)) && less)
574 || ((cond & (1 << 1)) && equal)
575 || ((cond & (1 << 0)) && unordered));
589 sim_fpu_status status = 0;
591 /* The format type should already have been checked. The FCSR is
592 updated before the condition codes so that any exceptions will
593 be signalled before the condition codes are changed. */
600 status = fp_test(op1, op2, fmt, abs, cond, &result);
601 update_fcsr (cpu, cia, status);
607 int result0, result1;
608 status = fp_test(FP_PS_lower (op1), FP_PS_lower (op2), fmt_single,
609 abs, cond, &result0);
610 status |= fp_test(FP_PS_upper (op1), FP_PS_upper (op2), fmt_single,
611 abs, cond, &result1);
612 update_fcsr (cpu, cia, status);
613 SETFCC (cc, result0);
614 SETFCC (cc+1, result1);
618 sim_io_eprintf (SD, "Bad switch\n");
624 /* Basic arithmetic operations. */
627 fp_unary(sim_cpu *cpu,
629 int (*sim_fpu_op)(sim_fpu *, const sim_fpu *),
635 sim_fpu_round round = rounding_mode (GETRM());
636 sim_fpu_denorm denorm = denorm_mode (cpu);
637 sim_fpu_status status = 0;
638 unsigned64 result = 0;
640 /* The format type has already been checked: */
646 sim_fpu_32to (&wop, op);
647 status |= (*sim_fpu_op) (&ans, &wop);
648 status |= sim_fpu_round_32 (&ans, round, denorm);
649 sim_fpu_to32 (&res, &ans);
656 sim_fpu_64to (&wop, op);
657 status |= (*sim_fpu_op) (&ans, &wop);
658 status |= sim_fpu_round_64 (&ans, round, denorm);
659 sim_fpu_to64 (&res, &ans);
665 int status_u = 0, status_l = 0;
666 unsigned32 res_u, res_l;
667 sim_fpu_32to (&wop, FP_PS_upper(op));
668 status_u |= (*sim_fpu_op) (&ans, &wop);
669 sim_fpu_to32 (&res_u, &ans);
670 sim_fpu_32to (&wop, FP_PS_lower(op));
671 status_l |= (*sim_fpu_op) (&ans, &wop);
672 sim_fpu_to32 (&res_l, &ans);
673 result = FP_PS_cat(res_u, res_l);
674 status = status_u | status_l;
678 sim_io_eprintf (SD, "Bad switch\n");
682 update_fcsr (cpu, cia, status);
687 fp_binary(sim_cpu *cpu,
689 int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
697 sim_fpu_round round = rounding_mode (GETRM());
698 sim_fpu_denorm denorm = denorm_mode (cpu);
699 sim_fpu_status status = 0;
700 unsigned64 result = 0;
702 /* The format type has already been checked: */
708 sim_fpu_32to (&wop1, op1);
709 sim_fpu_32to (&wop2, op2);
710 status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
711 status |= sim_fpu_round_32 (&ans, round, denorm);
712 sim_fpu_to32 (&res, &ans);
719 sim_fpu_64to (&wop1, op1);
720 sim_fpu_64to (&wop2, op2);
721 status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
722 status |= sim_fpu_round_64 (&ans, round, denorm);
723 sim_fpu_to64 (&res, &ans);
729 int status_u = 0, status_l = 0;
730 unsigned32 res_u, res_l;
731 sim_fpu_32to (&wop1, FP_PS_upper(op1));
732 sim_fpu_32to (&wop2, FP_PS_upper(op2));
733 status_u |= (*sim_fpu_op) (&ans, &wop1, &wop2);
734 sim_fpu_to32 (&res_u, &ans);
735 sim_fpu_32to (&wop1, FP_PS_lower(op1));
736 sim_fpu_32to (&wop2, FP_PS_lower(op2));
737 status_l |= (*sim_fpu_op) (&ans, &wop1, &wop2);
738 sim_fpu_to32 (&res_l, &ans);
739 result = FP_PS_cat(res_u, res_l);
740 status = status_u | status_l;
744 sim_io_eprintf (SD, "Bad switch\n");
748 update_fcsr (cpu, cia, status);
752 /* Common MAC code for single operands (.s or .d), defers setting FCSR. */
753 static sim_fpu_status
754 inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
762 sim_fpu_denorm denorm,
768 sim_fpu_status status = 0;
769 sim_fpu_status op_status;
777 sim_fpu_32to (&wop1, op1);
778 sim_fpu_32to (&wop2, op2);
779 status |= sim_fpu_mul (&ans, &wop1, &wop2);
780 if (scale != 0 && sim_fpu_is_number (&ans)) /* number or denorm */
781 ans.normal_exp += scale;
782 status |= sim_fpu_round_32 (&ans, round, denorm);
785 sim_fpu_32to (&wop2, op3);
786 op_status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
787 op_status |= sim_fpu_round_32 (&ans, round, denorm);
792 op_status = sim_fpu_neg (&ans, &wop1);
793 op_status |= sim_fpu_round_32 (&ans, round, denorm);
796 sim_fpu_to32 (&res, &ans);
803 sim_fpu_64to (&wop1, op1);
804 sim_fpu_64to (&wop2, op2);
805 status |= sim_fpu_mul (&ans, &wop1, &wop2);
806 if (scale != 0 && sim_fpu_is_number (&ans)) /* number or denorm */
807 ans.normal_exp += scale;
808 status |= sim_fpu_round_64 (&ans, round, denorm);
811 sim_fpu_64to (&wop2, op3);
812 op_status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
813 op_status |= sim_fpu_round_64 (&ans, round, denorm);
818 op_status = sim_fpu_neg (&ans, &wop1);
819 op_status |= sim_fpu_round_64 (&ans, round, denorm);
822 sim_fpu_to64 (&res, &ans);
827 fprintf (stderr, "Bad switch\n");
834 /* Common implementation of madd, nmadd, msub, nmsub that does
835 intermediate rounding per spec. Also used for recip2 and rsqrt2,
836 which are transformed into equivalent nmsub operations. The scale
837 argument is an adjustment to the exponent of the intermediate
838 product op1*op2. It is currently non-zero for rsqrt2 (-1), which
839 requires an effective division by 2. */
843 int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
851 sim_fpu_round round = rounding_mode (GETRM());
852 sim_fpu_denorm denorm = denorm_mode (cpu);
853 sim_fpu_status status = 0;
854 unsigned64 result = 0;
856 /* The format type has already been checked: */
861 status = inner_mac(sim_fpu_op, op1, op2, op3, scale,
862 negate, fmt, round, denorm, &result);
866 int status_u, status_l;
867 unsigned64 result_u, result_l;
868 status_u = inner_mac(sim_fpu_op, FP_PS_upper(op1), FP_PS_upper(op2),
869 FP_PS_upper(op3), scale, negate, fmt_single,
870 round, denorm, &result_u);
871 status_l = inner_mac(sim_fpu_op, FP_PS_lower(op1), FP_PS_lower(op2),
872 FP_PS_lower(op3), scale, negate, fmt_single,
873 round, denorm, &result_l);
874 result = FP_PS_cat(result_u, result_l);
875 status = status_u | status_l;
879 sim_io_eprintf (SD, "Bad switch\n");
883 update_fcsr (cpu, cia, status);
887 /* Common rsqrt code for single operands (.s or .d), intermediate rounding. */
888 static sim_fpu_status
889 inner_rsqrt(unsigned64 op1,
892 sim_fpu_denorm denorm,
897 sim_fpu_status status = 0;
898 sim_fpu_status op_status;
906 sim_fpu_32to (&wop1, op1);
907 status |= sim_fpu_sqrt (&ans, &wop1);
908 status |= sim_fpu_round_32 (&ans, status, round);
910 op_status = sim_fpu_inv (&ans, &wop1);
911 op_status |= sim_fpu_round_32 (&ans, round, denorm);
912 sim_fpu_to32 (&res, &ans);
920 sim_fpu_64to (&wop1, op1);
921 status |= sim_fpu_sqrt (&ans, &wop1);
922 status |= sim_fpu_round_64 (&ans, round, denorm);
924 op_status = sim_fpu_inv (&ans, &wop1);
925 op_status |= sim_fpu_round_64 (&ans, round, denorm);
926 sim_fpu_to64 (&res, &ans);
932 fprintf (stderr, "Bad switch\n");
940 fp_inv_sqrt(sim_cpu *cpu,
945 sim_fpu_round round = rounding_mode (GETRM());
946 sim_fpu_round denorm = denorm_mode (cpu);
947 sim_fpu_status status = 0;
948 unsigned64 result = 0;
950 /* The format type has already been checked: */
955 status = inner_rsqrt (op1, fmt, round, denorm, &result);
959 int status_u, status_l;
960 unsigned64 result_u, result_l;
961 status_u = inner_rsqrt (FP_PS_upper(op1), fmt_single, round, denorm,
963 status_l = inner_rsqrt (FP_PS_lower(op1), fmt_single, round, denorm,
965 result = FP_PS_cat(result_u, result_l);
966 status = status_u | status_l;
970 sim_io_eprintf (SD, "Bad switch\n");
974 update_fcsr (cpu, cia, status);
985 return fp_unary(cpu, cia, &sim_fpu_abs, op, fmt);
994 return fp_unary(cpu, cia, &sim_fpu_neg, op, fmt);
1004 return fp_binary(cpu, cia, &sim_fpu_add, op1, op2, fmt);
1008 fp_sub(sim_cpu *cpu,
1014 return fp_binary(cpu, cia, &sim_fpu_sub, op1, op2, fmt);
1018 fp_mul(sim_cpu *cpu,
1024 return fp_binary(cpu, cia, &sim_fpu_mul, op1, op2, fmt);
1028 fp_div(sim_cpu *cpu,
1034 return fp_binary(cpu, cia, &sim_fpu_div, op1, op2, fmt);
1038 fp_recip(sim_cpu *cpu,
1043 return fp_unary(cpu, cia, &sim_fpu_inv, op, fmt);
1047 fp_sqrt(sim_cpu *cpu,
1052 return fp_unary(cpu, cia, &sim_fpu_sqrt, op, fmt);
1056 fp_rsqrt(sim_cpu *cpu,
1061 return fp_inv_sqrt(cpu, cia, op, fmt);
1065 fp_madd(sim_cpu *cpu,
1072 return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 0, fmt);
1076 fp_msub(sim_cpu *cpu,
1083 return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 0, fmt);
1087 fp_nmadd(sim_cpu *cpu,
1094 return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 1, fmt);
1098 fp_nmsub(sim_cpu *cpu,
1105 return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 1, fmt);
1109 /* MIPS-3D ASE operations. */
1111 /* Variant of fp_binary for *r.ps MIPS-3D operations. */
1113 fp_binary_r(sim_cpu *cpu,
1115 int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
1122 sim_fpu_round round = rounding_mode (GETRM ());
1123 sim_fpu_denorm denorm = denorm_mode (cpu);
1124 sim_fpu_status status_u, status_l;
1126 unsigned32 res_u, res_l;
1128 /* The format must be fmt_ps. */
1130 sim_fpu_32to (&wop1, FP_PS_upper (op1));
1131 sim_fpu_32to (&wop2, FP_PS_lower (op1));
1132 status_u |= (*sim_fpu_op) (&ans, &wop1, &wop2);
1133 status_u |= sim_fpu_round_32 (&ans, round, denorm);
1134 sim_fpu_to32 (&res_u, &ans);
1136 sim_fpu_32to (&wop1, FP_PS_upper (op2));
1137 sim_fpu_32to (&wop2, FP_PS_lower (op2));
1138 status_l |= (*sim_fpu_op) (&ans, &wop1, &wop2);
1139 status_l |= sim_fpu_round_32 (&ans, round, denorm);
1140 sim_fpu_to32 (&res_l, &ans);
1141 result = FP_PS_cat (res_u, res_l);
1143 update_fcsr (cpu, cia, status_u | status_l);
1148 fp_add_r(sim_cpu *cpu,
1154 return fp_binary_r (cpu, cia, &sim_fpu_add, op1, op2);
1158 fp_mul_r(sim_cpu *cpu,
1164 return fp_binary_r (cpu, cia, &sim_fpu_mul, op1, op2);
1167 #define NR_FRAC_GUARD (60)
1168 #define IMPLICIT_1 LSBIT64 (NR_FRAC_GUARD)
1171 fpu_inv1(sim_fpu *f, const sim_fpu *l)
1173 static const sim_fpu sim_fpu_one = {
1174 sim_fpu_class_number, 0, IMPLICIT_1, 0
1179 if (sim_fpu_is_zero (l))
1183 return sim_fpu_status_invalid_div0;
1185 if (sim_fpu_is_infinity (l))
1191 status |= sim_fpu_div (f, &sim_fpu_one, l);
1196 fpu_inv1_32(sim_fpu *f, const sim_fpu *l)
1198 if (sim_fpu_is_zero (l))
1202 return sim_fpu_status_invalid_div0;
1204 return fpu_inv1 (f, l);
1208 fpu_inv1_64(sim_fpu *f, const sim_fpu *l)
1210 if (sim_fpu_is_zero (l))
1214 return sim_fpu_status_invalid_div0;
1216 return fpu_inv1 (f, l);
1220 fp_recip1(sim_cpu *cpu,
1229 return fp_unary (cpu, cia, &fpu_inv1_32, op, fmt);
1231 return fp_unary (cpu, cia, &fpu_inv1_64, op, fmt);
1237 fp_recip2(sim_cpu *cpu,
1243 static const unsigned64 one_single = UNSIGNED64 (0x3F800000);
1244 static const unsigned64 one_double = UNSIGNED64 (0x3FF0000000000000);
1245 static const unsigned64 one_ps = (UNSIGNED64 (0x3F800000) << 32 | UNSIGNED64 (0x3F800000));
1248 /* Implemented as nmsub fd, 1, fs, ft. */
1251 case fmt_single: one = one_single; break;
1252 case fmt_double: one = one_double; break;
1253 case fmt_ps: one = one_ps; break;
1254 default: one = 0; abort ();
1256 return fp_mac (cpu, cia, &sim_fpu_sub, op1, op2, one, 0, 1, fmt);
1260 fpu_inv_sqrt1(sim_fpu *f, const sim_fpu *l)
1262 static const sim_fpu sim_fpu_one = {
1263 sim_fpu_class_number, 0, IMPLICIT_1, 0
1268 if (sim_fpu_is_zero (l))
1272 return sim_fpu_status_invalid_div0;
1274 if (sim_fpu_is_infinity (l))
1278 f->class = sim_fpu_class_zero;
1284 status = sim_fpu_status_invalid_sqrt;
1288 status |= sim_fpu_sqrt (&t, l);
1289 status |= sim_fpu_div (f, &sim_fpu_one, &t);
1294 fpu_inv_sqrt1_32(sim_fpu *f, const sim_fpu *l)
1296 if (sim_fpu_is_zero (l))
1300 return sim_fpu_status_invalid_div0;
1302 return fpu_inv_sqrt1 (f, l);
1306 fpu_inv_sqrt1_64(sim_fpu *f, const sim_fpu *l)
1308 if (sim_fpu_is_zero (l))
1312 return sim_fpu_status_invalid_div0;
1314 return fpu_inv_sqrt1 (f, l);
1318 fp_rsqrt1(sim_cpu *cpu,
1327 return fp_unary (cpu, cia, &fpu_inv_sqrt1_32, op, fmt);
1329 return fp_unary (cpu, cia, &fpu_inv_sqrt1_64, op, fmt);
1335 fp_rsqrt2(sim_cpu *cpu,
1341 static const unsigned64 half_single = UNSIGNED64 (0x3F000000);
1342 static const unsigned64 half_double = UNSIGNED64 (0x3FE0000000000000);
1343 static const unsigned64 half_ps = (UNSIGNED64 (0x3F000000) << 32 | UNSIGNED64 (0x3F000000));
1346 /* Implemented as (nmsub fd, 0.5, fs, ft)/2, where the divide is
1347 done by scaling the exponent during multiply. */
1350 case fmt_single: half = half_single; break;
1351 case fmt_double: half = half_double; break;
1352 case fmt_ps: half = half_ps; break;
1353 default: half = 0; abort ();
1355 return fp_mac (cpu, cia, &sim_fpu_sub, op1, op2, half, -1, 1, fmt);
1359 /* Conversion operations. */
1362 convert (sim_cpu *cpu,
1370 sim_fpu_round round = rounding_mode (rm);
1371 sim_fpu_denorm denorm = denorm_mode (cpu);
1372 unsigned32 result32;
1373 unsigned64 result64;
1374 sim_fpu_status status = 0;
1376 /* Convert the input to sim_fpu internal format */
1380 sim_fpu_64to (&wop, op);
1383 sim_fpu_32to (&wop, op);
1386 status = sim_fpu_i32to (&wop, op, round);
1389 status = sim_fpu_i64to (&wop, op, round);
1392 sim_io_eprintf (SD, "Bad switch\n");
1396 /* Convert sim_fpu format into the output */
1397 /* The value WOP is converted to the destination format, rounding
1398 using mode RM. When the destination is a fixed-point format, then
1399 a source value of Infinity, NaN or one which would round to an
1400 integer outside the fixed point range then an IEEE Invalid Operation
1401 condition is raised. Not used if destination format is PS. */
1405 status |= sim_fpu_round_32 (&wop, round, denorm);
1406 /* For a NaN, normalize mantissa bits (cvt.s.d can't preserve them) */
1407 if (sim_fpu_is_qnan (&wop))
1409 sim_fpu_to32 (&result32, &wop);
1410 result64 = result32;
1413 status |= sim_fpu_round_64 (&wop, round, denorm);
1414 /* For a NaN, normalize mantissa bits (make cvt.d.s consistent) */
1415 if (sim_fpu_is_qnan (&wop))
1417 sim_fpu_to64 (&result64, &wop);
1420 status |= sim_fpu_to32i (&result32, &wop, round);
1421 result64 = result32;
1424 status |= sim_fpu_to64i (&result64, &wop, round);
1428 sim_io_eprintf (SD, "Bad switch\n");
1432 update_fcsr (cpu, cia, status);
1437 ps_lower(sim_cpu *cpu,
1441 return FP_PS_lower (op);
1445 ps_upper(sim_cpu *cpu,
1449 return FP_PS_upper(op);
1453 pack_ps(sim_cpu *cpu,
1459 unsigned64 result = 0;
1461 /* The registers must specify FPRs valid for operands of type
1462 "fmt". If they are not valid, the result is undefined. */
1464 /* The format type should already have been checked: */
1470 unsigned32 res_u, res_l;
1471 sim_fpu_32to (&wop, op1);
1472 sim_fpu_to32 (&res_u, &wop);
1473 sim_fpu_32to (&wop, op2);
1474 sim_fpu_to32 (&res_l, &wop);
1475 result = FP_PS_cat(res_u, res_l);
1479 sim_io_eprintf (SD, "Bad switch\n");
1487 convert_ps (sim_cpu *cpu,
1494 sim_fpu wop_u, wop_l;
1495 sim_fpu_round round = rounding_mode (rm);
1496 sim_fpu_denorm denorm = denorm_mode (cpu);
1497 unsigned32 res_u, res_l;
1499 sim_fpu_status status_u = 0, status_l = 0;
1501 /* As convert, but used only for paired values (formats PS, PW) */
1503 /* Convert the input to sim_fpu internal format */
1506 case fmt_word: /* fmt_pw */
1507 sim_fpu_i32to (&wop_u, (op >> 32) & (unsigned)0xFFFFFFFF, round);
1508 sim_fpu_i32to (&wop_l, op & (unsigned)0xFFFFFFFF, round);
1511 sim_fpu_32to (&wop_u, FP_PS_upper(op));
1512 sim_fpu_32to (&wop_l, FP_PS_lower(op));
1515 sim_io_eprintf (SD, "Bad switch\n");
1519 /* Convert sim_fpu format into the output */
1522 case fmt_word: /* fmt_pw */
1523 status_u |= sim_fpu_to32i (&res_u, &wop_u, round);
1524 status_l |= sim_fpu_to32i (&res_l, &wop_l, round);
1525 result = (((unsigned64)res_u) << 32) | (unsigned64)res_l;
1528 status_u |= sim_fpu_round_32 (&wop_u, 0, round);
1529 status_l |= sim_fpu_round_32 (&wop_l, 0, round);
1530 sim_fpu_to32 (&res_u, &wop_u);
1531 sim_fpu_to32 (&res_l, &wop_l);
1532 result = FP_PS_cat(res_u, res_l);
1536 sim_io_eprintf (SD, "Bad switch\n");
1540 update_fcsr (cpu, cia, status_u | status_l);
1545 fpu_format_name (FP_formats fmt)
1561 case fmt_uninterpreted:
1562 return "<uninterpreted>";
1563 case fmt_uninterpreted_32:
1564 return "<uninterpreted_32>";
1565 case fmt_uninterpreted_64:
1566 return "<uninterpreted_64>";
1568 return "<format error>";
1574 fpu_rounding_mode_name (int rm)
1587 return "<rounding mode error>";