1 2002-02-28 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
4 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
5 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
6 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
7 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
8 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
9 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
10 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
12 2002-02-28 Chris Demetriou <cgd@broadcom.com>
14 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
15 instruction-printing string.
16 (LWU): Use '64' as the filter flag.
18 2002-02-28 Chris Demetriou <cgd@broadcom.com>
20 * mips.igen (SDXC1): Fix instruction-printing string.
22 2002-02-28 Chris Demetriou <cgd@broadcom.com>
24 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
27 2002-02-27 Chris Demetriou <cgd@broadcom.com>
29 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
32 2002-02-27 Chris Demetriou <cgd@broadcom.com>
34 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
35 add a comma) so that it more closely match the MIPS ISA
36 documentation opcode partitioning.
37 (PREF): Put useful names on opcode fields, and include
38 instruction-printing string.
40 2002-02-27 Chris Demetriou <cgd@broadcom.com>
42 * mips.igen (check_u64): New function which in the future will
43 check whether 64-bit instructions are usable and signal an
44 exception if not. Currently a no-op.
45 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
46 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
47 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
48 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
50 * mips.igen (check_fpu): New function which in the future will
51 check whether FPU instructions are usable and signal an exception
52 if not. Currently a no-op.
53 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
54 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
55 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
56 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
57 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
58 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
59 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
60 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
62 2002-02-27 Chris Demetriou <cgd@broadcom.com>
64 * mips.igen (do_load_left, do_load_right): Move to be immediately
66 (do_store_left, do_store_right): Move to be immediately following
69 2002-02-27 Chris Demetriou <cgd@broadcom.com>
71 * mips.igen (mipsV): New model name. Also, add it to
72 all instructions and functions where it is appropriate.
74 2002-02-18 Chris Demetriou <cgd@broadcom.com>
76 * mips.igen: For all functions and instructions, list model
77 names that support that instruction one per line.
79 2002-02-11 Chris Demetriou <cgd@broadcom.com>
81 * mips.igen: Add some additional comments about supported
82 models, and about which instructions go where.
83 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
84 order as is used in the rest of the file.
86 2002-02-11 Chris Demetriou <cgd@broadcom.com>
88 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
89 indicating that ALU32_END or ALU64_END are there to check
91 (DADD): Likewise, but also remove previous comment about
94 2002-02-10 Chris Demetriou <cgd@broadcom.com>
96 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
97 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
98 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
99 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
100 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
101 fields (i.e., add and move commas) so that they more closely
102 match the MIPS ISA documentation opcode partitioning.
104 2002-02-10 Chris Demetriou <cgd@broadcom.com>
106 * mips.igen (ADDI): Print immediate value.
108 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
109 (SLL): Print "nop" specially, and don't run the code
110 that does the shift for the "nop" case.
112 2001-11-17 Fred Fish <fnf@redhat.com>
114 * sim-main.h (float_operation): Move enum declaration outside
115 of _sim_cpu struct declaration.
117 2001-04-12 Jim Blandy <jimb@redhat.com>
119 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
120 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
122 * sim-main.h (COCIDX): Remove definition; this isn't supported by
123 PENDING_FILL, and you can get the intended effect gracefully by
124 calling PENDING_SCHED directly.
126 2001-02-23 Ben Elliston <bje@redhat.com>
128 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
129 already defined elsewhere.
131 2001-02-19 Ben Elliston <bje@redhat.com>
133 * sim-main.h (sim_monitor): Return an int.
134 * interp.c (sim_monitor): Add return values.
135 (signal_exception): Handle error conditions from sim_monitor.
137 2001-02-08 Ben Elliston <bje@redhat.com>
139 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
140 (store_memory): Likewise, pass cia to sim_core_write*.
142 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
144 On advice from Chris G. Demetriou <cgd@sibyte.com>:
145 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
147 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
149 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
150 * Makefile.in: Don't delete *.igen when cleaning directory.
152 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
154 * m16.igen (break): Call SignalException not sim_engine_halt.
156 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
159 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
161 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
163 * mips.igen (MxC1, DMxC1): Fix printf formatting.
165 2000-05-24 Michael Hayes <mhayes@cygnus.com>
167 * mips.igen (do_dmultx): Fix typo.
169 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
171 * configure: Regenerated to track ../common/aclocal.m4 changes.
173 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
175 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
177 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
179 * sim-main.h (GPR_CLEAR): Define macro.
181 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
183 * interp.c (decode_coproc): Output long using %lx and not %s.
185 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
187 * interp.c (sim_open): Sort & extend dummy memory regions for
188 --board=jmr3904 for eCos.
190 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
192 * configure: Regenerated.
194 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
196 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
197 calls, conditional on the simulator being in verbose mode.
199 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
201 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
202 cache don't get ReservedInstruction traps.
204 1999-11-29 Mark Salter <msalter@cygnus.com>
206 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
207 to clear status bits in sdisr register. This is how the hardware works.
209 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
210 being used by cygmon.
212 1999-11-11 Andrew Haley <aph@cygnus.com>
214 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
217 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
219 * mips.igen (MULT): Correct previous mis-applied patch.
221 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
223 * mips.igen (delayslot32): Handle sequence like
224 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
225 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
226 (MULT): Actually pass the third register...
228 1999-09-03 Mark Salter <msalter@cygnus.com>
230 * interp.c (sim_open): Added more memory aliases for additional
231 hardware being touched by cygmon on jmr3904 board.
233 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
235 * configure: Regenerated to track ../common/aclocal.m4 changes.
237 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
239 * interp.c (sim_store_register): Handle case where client - GDB -
240 specifies that a 4 byte register is 8 bytes in size.
241 (sim_fetch_register): Ditto.
243 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
245 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
246 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
247 (idt_monitor_base): Base address for IDT monitor traps.
248 (pmon_monitor_base): Ditto for PMON.
249 (lsipmon_monitor_base): Ditto for LSI PMON.
250 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
251 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
252 (sim_firmware_command): New function.
253 (mips_option_handler): Call it for OPTION_FIRMWARE.
254 (sim_open): Allocate memory for idt_monitor region. If "--board"
255 option was given, add no monitor by default. Add BREAK hooks only if
256 monitors are also there.
258 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
260 * interp.c (sim_monitor): Flush output before reading input.
262 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
264 * tconfig.in (SIM_HANDLES_LMA): Always define.
266 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
268 From Mark Salter <msalter@cygnus.com>:
269 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
270 (sim_open): Add setup for BSP board.
272 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
274 * mips.igen (MULT, MULTU): Add syntax for two operand version.
275 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
276 them as unimplemented.
278 1999-05-08 Felix Lee <flee@cygnus.com>
280 * configure: Regenerated to track ../common/aclocal.m4 changes.
282 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
284 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
286 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
288 * configure.in: Any mips64vr5*-*-* target should have
289 -DTARGET_ENABLE_FR=1.
290 (default_endian): Any mips64vr*el-*-* target should default to
292 * configure: Re-generate.
294 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
296 * mips.igen (ldl): Extend from _16_, not 32.
298 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
300 * interp.c (sim_store_register): Force registers written to by GDB
301 into an un-interpreted state.
303 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
305 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
306 CPU, start periodic background I/O polls.
307 (tx3904sio_poll): New function: periodic I/O poller.
309 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
311 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
313 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
315 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
318 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
320 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
321 (load_word): Call SIM_CORE_SIGNAL hook on error.
322 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
323 starting. For exception dispatching, pass PC instead of NULL_CIA.
324 (decode_coproc): Use COP0_BADVADDR to store faulting address.
325 * sim-main.h (COP0_BADVADDR): Define.
326 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
327 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
328 (_sim_cpu): Add exc_* fields to store register value snapshots.
329 * mips.igen (*): Replace memory-related SignalException* calls
330 with references to SIM_CORE_SIGNAL hook.
332 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
334 * sim-main.c (*): Minor warning cleanups.
336 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
338 * m16.igen (DADDIU5): Correct type-o.
340 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
342 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
345 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
347 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
349 (interp.o): Add dependency on itable.h
350 (oengine.c, gencode): Delete remaining references.
351 (BUILT_SRC_FROM_GEN): Clean up.
353 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
356 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
357 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
359 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
360 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
361 Drop the "64" qualifier to get the HACK generator working.
362 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
363 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
364 qualifier to get the hack generator working.
365 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
367 (DSLLV): Use do_dsllv.
370 (DSRLV): Use do_dsrlv.
371 (BC1): Move *vr4100 to get the HACK generator working.
372 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
373 get the HACK generator working.
374 (MACC) Rename to get the HACK generator working.
375 (DMACC,MACCS,DMACCS): Add the 64.
377 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
379 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
380 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
382 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
384 * mips/interp.c (DEBUG): Cleanups.
386 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
388 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
389 (tx3904sio_tickle): fflush after a stdout character output.
391 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
393 * interp.c (sim_close): Uninstall modules.
395 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
397 * sim-main.h, interp.c (sim_monitor): Change to global
400 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
402 * configure.in (vr4100): Only include vr4100 instructions in
404 * configure: Re-generate.
405 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
407 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
409 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
410 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
413 * configure.in (sim_default_gen, sim_use_gen): Replace with
415 (--enable-sim-igen): Delete config option. Always using IGEN.
416 * configure: Re-generate.
418 * Makefile.in (gencode): Kill, kill, kill.
421 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
423 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
424 bit mips16 igen simulator.
425 * configure: Re-generate.
427 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
428 as part of vr4100 ISA.
429 * vr.igen: Mark all instructions as 64 bit only.
431 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
433 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
436 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
438 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
439 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
440 * configure: Re-generate.
442 * m16.igen (BREAK): Define breakpoint instruction.
443 (JALX32): Mark instruction as mips16 and not r3900.
444 * mips.igen (C.cond.fmt): Fix typo in instruction format.
446 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
448 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
450 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
451 insn as a debug breakpoint.
453 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
455 (PENDING_SCHED): Clean up trace statement.
456 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
457 (PENDING_FILL): Delay write by only one cycle.
458 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
460 * sim-main.c (pending_tick): Clean up trace statements. Add trace
462 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
464 (pending_tick): Move incrementing of index to FOR statement.
465 (pending_tick): Only update PENDING_OUT after a write has occured.
467 * configure.in: Add explicit mips-lsi-* target. Use gencode to
469 * configure: Re-generate.
471 * interp.c (sim_engine_run OLD): Delete explicit call to
472 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
474 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
476 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
477 interrupt level number to match changed SignalExceptionInterrupt
480 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
482 * interp.c: #include "itable.h" if WITH_IGEN.
483 (get_insn_name): New function.
484 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
485 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
487 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
489 * configure: Rebuilt to inhale new common/aclocal.m4.
491 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
493 * dv-tx3904sio.c: Include sim-assert.h.
495 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
497 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
498 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
499 Reorganize target-specific sim-hardware checks.
500 * configure: rebuilt.
501 * interp.c (sim_open): For tx39 target boards, set
502 OPERATING_ENVIRONMENT, add tx3904sio devices.
503 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
504 ROM executables. Install dv-sockser into sim-modules list.
506 * dv-tx3904irc.c: Compiler warning clean-up.
507 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
508 frequent hw-trace messages.
510 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
512 * vr.igen (MulAcc): Identify as a vr4100 specific function.
514 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
516 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
519 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
520 * mips.igen: Define vr4100 model. Include vr.igen.
521 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
523 * mips.igen (check_mf_hilo): Correct check.
525 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
527 * sim-main.h (interrupt_event): Add prototype.
529 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
530 register_ptr, register_value.
531 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
533 * sim-main.h (tracefh): Make extern.
535 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
537 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
538 Reduce unnecessarily high timer event frequency.
539 * dv-tx3904cpu.c: Ditto for interrupt event.
541 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
543 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
545 (interrupt_event): Made non-static.
547 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
548 interchange of configuration values for external vs. internal
551 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
553 * mips.igen (BREAK): Moved code to here for
554 simulator-reserved break instructions.
555 * gencode.c (build_instruction): Ditto.
556 * interp.c (signal_exception): Code moved from here. Non-
557 reserved instructions now use exception vector, rather
559 * sim-main.h: Moved magic constants to here.
561 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
563 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
564 register upon non-zero interrupt event level, clear upon zero
566 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
567 by passing zero event value.
568 (*_io_{read,write}_buffer): Endianness fixes.
569 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
570 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
572 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
573 serial I/O and timer module at base address 0xFFFF0000.
575 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
577 * mips.igen (SWC1) : Correct the handling of ReverseEndian
580 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
582 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
586 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
588 * dv-tx3904tmr.c: New file - implements tx3904 timer.
589 * dv-tx3904{irc,cpu}.c: Mild reformatting.
590 * configure.in: Include tx3904tmr in hw_device list.
591 * configure: Rebuilt.
592 * interp.c (sim_open): Instantiate three timer instances.
593 Fix address typo of tx3904irc instance.
595 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
597 * interp.c (signal_exception): SystemCall exception now uses
598 the exception vector.
600 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
602 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
605 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
607 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
609 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
611 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
613 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
614 sim-main.h. Declare a struct hw_descriptor instead of struct
615 hw_device_descriptor.
617 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
619 * mips.igen (do_store_left, do_load_left): Compute nr of left and
620 right bits and then re-align left hand bytes to correct byte
621 lanes. Fix incorrect computation in do_store_left when loading
622 bytes from second word.
624 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
626 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
627 * interp.c (sim_open): Only create a device tree when HW is
630 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
631 * interp.c (signal_exception): Ditto.
633 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
635 * gencode.c: Mark BEGEZALL as LIKELY.
637 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
639 * sim-main.h (ALU32_END): Sign extend 32 bit results.
640 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
642 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
644 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
645 modules. Recognize TX39 target with "mips*tx39" pattern.
646 * configure: Rebuilt.
647 * sim-main.h (*): Added many macros defining bits in
648 TX39 control registers.
649 (SignalInterrupt): Send actual PC instead of NULL.
650 (SignalNMIReset): New exception type.
651 * interp.c (board): New variable for future use to identify
652 a particular board being simulated.
653 (mips_option_handler,mips_options): Added "--board" option.
654 (interrupt_event): Send actual PC.
655 (sim_open): Make memory layout conditional on board setting.
656 (signal_exception): Initial implementation of hardware interrupt
657 handling. Accept another break instruction variant for simulator
659 (decode_coproc): Implement RFE instruction for TX39.
660 (mips.igen): Decode RFE instruction as such.
661 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
662 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
663 bbegin to implement memory map.
664 * dv-tx3904cpu.c: New file.
665 * dv-tx3904irc.c: New file.
667 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
669 * mips.igen (check_mt_hilo): Create a separate r3900 version.
671 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
673 * tx.igen (madd,maddu): Replace calls to check_op_hilo
674 with calls to check_div_hilo.
676 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
678 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
679 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
680 Add special r3900 version of do_mult_hilo.
681 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
682 with calls to check_mult_hilo.
683 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
684 with calls to check_div_hilo.
686 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
688 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
689 Document a replacement.
691 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
693 * interp.c (sim_monitor): Make mon_printf work.
695 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
697 * sim-main.h (INSN_NAME): New arg `cpu'.
699 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
701 * configure: Regenerated to track ../common/aclocal.m4 changes.
703 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
705 * configure: Regenerated to track ../common/aclocal.m4 changes.
708 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
710 * acconfig.h: New file.
711 * configure.in: Reverted change of Apr 24; use sinclude again.
713 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
715 * configure: Regenerated to track ../common/aclocal.m4 changes.
718 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
720 * configure.in: Don't call sinclude.
722 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
724 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
726 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
728 * mips.igen (ERET): Implement.
730 * interp.c (decode_coproc): Return sign-extended EPC.
732 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
734 * interp.c (signal_exception): Do not ignore Trap.
735 (signal_exception): On TRAP, restart at exception address.
736 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
737 (signal_exception): Update.
738 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
739 so that TRAP instructions are caught.
741 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
743 * sim-main.h (struct hilo_access, struct hilo_history): Define,
744 contains HI/LO access history.
745 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
746 (HIACCESS, LOACCESS): Delete, replace with
747 (HIHISTORY, LOHISTORY): New macros.
748 (CHECKHILO): Delete all, moved to mips.igen
750 * gencode.c (build_instruction): Do not generate checks for
751 correct HI/LO register usage.
753 * interp.c (old_engine_run): Delete checks for correct HI/LO
756 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
757 check_mf_cycles): New functions.
758 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
759 do_divu, domultx, do_mult, do_multu): Use.
761 * tx.igen ("madd", "maddu"): Use.
763 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
765 * mips.igen (DSRAV): Use function do_dsrav.
766 (SRAV): Use new function do_srav.
768 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
769 (B): Sign extend 11 bit immediate.
770 (EXT-B*): Shift 16 bit immediate left by 1.
771 (ADDIU*): Don't sign extend immediate value.
773 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
775 * m16run.c (sim_engine_run): Restore CIA after handling an event.
777 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
780 * mips.igen (delayslot32, nullify_next_insn): New functions.
781 (m16.igen): Always include.
782 (do_*): Add more tracing.
784 * m16.igen (delayslot16): Add NIA argument, could be called by a
785 32 bit MIPS16 instruction.
787 * interp.c (ifetch16): Move function from here.
788 * sim-main.c (ifetch16): To here.
790 * sim-main.c (ifetch16, ifetch32): Update to match current
791 implementations of LH, LW.
792 (signal_exception): Don't print out incorrect hex value of illegal
795 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
797 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
800 * m16.igen: Implement MIPS16 instructions.
802 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
803 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
804 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
805 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
806 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
807 bodies of corresponding code from 32 bit insn to these. Also used
808 by MIPS16 versions of functions.
810 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
811 (IMEM16): Drop NR argument from macro.
813 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
815 * Makefile.in (SIM_OBJS): Add sim-main.o.
817 * sim-main.h (address_translation, load_memory, store_memory,
818 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
820 (pr_addr, pr_uword64): Declare.
821 (sim-main.c): Include when H_REVEALS_MODULE_P.
823 * interp.c (address_translation, load_memory, store_memory,
824 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
826 * sim-main.c: To here. Fix compilation problems.
828 * configure.in: Enable inlining.
829 * configure: Re-config.
831 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
833 * configure: Regenerated to track ../common/aclocal.m4 changes.
835 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
837 * mips.igen: Include tx.igen.
838 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
839 * tx.igen: New file, contains MADD and MADDU.
841 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
842 the hardwired constant `7'.
843 (store_memory): Ditto.
844 (LOADDRMASK): Move definition to sim-main.h.
846 mips.igen (MTC0): Enable for r3900.
849 mips.igen (do_load_byte): Delete.
850 (do_load, do_store, do_load_left, do_load_write, do_store_left,
851 do_store_right): New functions.
852 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
854 configure.in: Let the tx39 use igen again.
857 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
859 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
860 not an address sized quantity. Return zero for cache sizes.
862 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
864 * mips.igen (r3900): r3900 does not support 64 bit integer
867 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
869 * configure.in (mipstx39*-*-*): Use gencode simulator rather
871 * configure : Rebuild.
873 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
875 * configure: Regenerated to track ../common/aclocal.m4 changes.
877 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
879 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
881 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
883 * configure: Regenerated to track ../common/aclocal.m4 changes.
884 * config.in: Regenerated to track ../common/aclocal.m4 changes.
886 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
888 * configure: Regenerated to track ../common/aclocal.m4 changes.
890 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
892 * interp.c (Max, Min): Comment out functions. Not yet used.
894 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
896 * configure: Regenerated to track ../common/aclocal.m4 changes.
898 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
900 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
901 configurable settings for stand-alone simulator.
903 * configure.in: Added X11 search, just in case.
905 * configure: Regenerated.
907 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
909 * interp.c (sim_write, sim_read, load_memory, store_memory):
910 Replace sim_core_*_map with read_map, write_map, exec_map resp.
912 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
914 * sim-main.h (GETFCC): Return an unsigned value.
916 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
918 * mips.igen (DIV): Fix check for -1 / MIN_INT.
919 (DADD): Result destination is RD not RT.
921 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
923 * sim-main.h (HIACCESS, LOACCESS): Always define.
925 * mdmx.igen (Maxi, Mini): Rename Max, Min.
927 * interp.c (sim_info): Delete.
929 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
931 * interp.c (DECLARE_OPTION_HANDLER): Use it.
932 (mips_option_handler): New argument `cpu'.
933 (sim_open): Update call to sim_add_option_table.
935 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
937 * mips.igen (CxC1): Add tracing.
939 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
941 * sim-main.h (Max, Min): Declare.
943 * interp.c (Max, Min): New functions.
945 * mips.igen (BC1): Add tracing.
947 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
949 * interp.c Added memory map for stack in vr4100
951 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
953 * interp.c (load_memory): Add missing "break"'s.
955 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
957 * interp.c (sim_store_register, sim_fetch_register): Pass in
958 length parameter. Return -1.
960 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
962 * interp.c: Added hardware init hook, fixed warnings.
964 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
966 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
968 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
970 * interp.c (ifetch16): New function.
972 * sim-main.h (IMEM32): Rename IMEM.
973 (IMEM16_IMMED): Define.
975 (DELAY_SLOT): Update.
977 * m16run.c (sim_engine_run): New file.
979 * m16.igen: All instructions except LB.
980 (LB): Call do_load_byte.
981 * mips.igen (do_load_byte): New function.
982 (LB): Call do_load_byte.
984 * mips.igen: Move spec for insn bit size and high bit from here.
985 * Makefile.in (tmp-igen, tmp-m16): To here.
987 * m16.dc: New file, decode mips16 instructions.
989 * Makefile.in (SIM_NO_ALL): Define.
990 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
992 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
994 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
995 point unit to 32 bit registers.
996 * configure: Re-generate.
998 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1000 * configure.in (sim_use_gen): Make IGEN the default simulator
1001 generator for generic 32 and 64 bit mips targets.
1002 * configure: Re-generate.
1004 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1006 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1009 * interp.c (sim_fetch_register, sim_store_register): Read/write
1010 FGR from correct location.
1011 (sim_open): Set size of FGR's according to
1012 WITH_TARGET_FLOATING_POINT_BITSIZE.
1014 * sim-main.h (FGR): Store floating point registers in a separate
1017 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1019 * configure: Regenerated to track ../common/aclocal.m4 changes.
1021 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1023 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1025 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1027 * interp.c (pending_tick): New function. Deliver pending writes.
1029 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1030 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1031 it can handle mixed sized quantites and single bits.
1033 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1035 * interp.c (oengine.h): Do not include when building with IGEN.
1036 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1037 (sim_info): Ditto for PROCESSOR_64BIT.
1038 (sim_monitor): Replace ut_reg with unsigned_word.
1039 (*): Ditto for t_reg.
1040 (LOADDRMASK): Define.
1041 (sim_open): Remove defunct check that host FP is IEEE compliant,
1042 using software to emulate floating point.
1043 (value_fpr, ...): Always compile, was conditional on HASFPU.
1045 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1047 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1050 * interp.c (SD, CPU): Define.
1051 (mips_option_handler): Set flags in each CPU.
1052 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1053 (sim_close): Do not clear STATE, deleted anyway.
1054 (sim_write, sim_read): Assume CPU zero's vm should be used for
1056 (sim_create_inferior): Set the PC for all processors.
1057 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1059 (mips16_entry): Pass correct nr of args to store_word, load_word.
1060 (ColdReset): Cold reset all cpu's.
1061 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1062 (sim_monitor, load_memory, store_memory, signal_exception): Use
1063 `CPU' instead of STATE_CPU.
1066 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1069 * sim-main.h (signal_exception): Add sim_cpu arg.
1070 (SignalException*): Pass both SD and CPU to signal_exception.
1071 * interp.c (signal_exception): Update.
1073 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1075 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1076 address_translation): Ditto
1077 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1079 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1081 * configure: Regenerated to track ../common/aclocal.m4 changes.
1083 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1085 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1087 * mips.igen (model): Map processor names onto BFD name.
1089 * sim-main.h (CPU_CIA): Delete.
1090 (SET_CIA, GET_CIA): Define
1092 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1094 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1097 * configure.in (default_endian): Configure a big-endian simulator
1099 * configure: Re-generate.
1101 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1103 * configure: Regenerated to track ../common/aclocal.m4 changes.
1105 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1107 * interp.c (sim_monitor): Handle Densan monitor outbyte
1108 and inbyte functions.
1110 1997-12-29 Felix Lee <flee@cygnus.com>
1112 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1114 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1116 * Makefile.in (tmp-igen): Arrange for $zero to always be
1117 reset to zero after every instruction.
1119 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1121 * configure: Regenerated to track ../common/aclocal.m4 changes.
1124 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1126 * mips.igen (MSUB): Fix to work like MADD.
1127 * gencode.c (MSUB): Similarly.
1129 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1131 * configure: Regenerated to track ../common/aclocal.m4 changes.
1133 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1135 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1137 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1139 * sim-main.h (sim-fpu.h): Include.
1141 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1142 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1143 using host independant sim_fpu module.
1145 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1147 * interp.c (signal_exception): Report internal errors with SIGABRT
1150 * sim-main.h (C0_CONFIG): New register.
1151 (signal.h): No longer include.
1153 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1155 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1157 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1159 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1161 * mips.igen: Tag vr5000 instructions.
1162 (ANDI): Was missing mipsIV model, fix assembler syntax.
1163 (do_c_cond_fmt): New function.
1164 (C.cond.fmt): Handle mips I-III which do not support CC field
1166 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1167 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1169 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1170 vr5000 which saves LO in a GPR separatly.
1172 * configure.in (enable-sim-igen): For vr5000, select vr5000
1173 specific instructions.
1174 * configure: Re-generate.
1176 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1178 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1180 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1181 fmt_uninterpreted_64 bit cases to switch. Convert to
1184 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1186 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1187 as specified in IV3.2 spec.
1188 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1190 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1192 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1193 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1194 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1195 PENDING_FILL versions of instructions. Simplify.
1197 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1199 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1201 (MTHI, MFHI): Disable code checking HI-LO.
1203 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1205 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1207 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1209 * gencode.c (build_mips16_operands): Replace IPC with cia.
1211 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1212 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1214 (UndefinedResult): Replace function with macro/function
1216 (sim_engine_run): Don't save PC in IPC.
1218 * sim-main.h (IPC): Delete.
1221 * interp.c (signal_exception, store_word, load_word,
1222 address_translation, load_memory, store_memory, cache_op,
1223 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1224 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1225 current instruction address - cia - argument.
1226 (sim_read, sim_write): Call address_translation directly.
1227 (sim_engine_run): Rename variable vaddr to cia.
1228 (signal_exception): Pass cia to sim_monitor
1230 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1231 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1232 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1234 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1235 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1238 * interp.c (signal_exception): Pass restart address to
1241 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1242 idecode.o): Add dependency.
1244 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1246 (DELAY_SLOT): Update NIA not PC with branch address.
1247 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1249 * mips.igen: Use CIA not PC in branch calculations.
1250 (illegal): Call SignalException.
1251 (BEQ, ADDIU): Fix assembler.
1253 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1255 * m16.igen (JALX): Was missing.
1257 * configure.in (enable-sim-igen): New configuration option.
1258 * configure: Re-generate.
1260 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1262 * interp.c (load_memory, store_memory): Delete parameter RAW.
1263 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1264 bypassing {load,store}_memory.
1266 * sim-main.h (ByteSwapMem): Delete definition.
1268 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1270 * interp.c (sim_do_command, sim_commands): Delete mips specific
1271 commands. Handled by module sim-options.
1273 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1274 (WITH_MODULO_MEMORY): Define.
1276 * interp.c (sim_info): Delete code printing memory size.
1278 * interp.c (mips_size): Nee sim_size, delete function.
1280 (monitor, monitor_base, monitor_size): Delete global variables.
1281 (sim_open, sim_close): Delete code creating monitor and other
1282 memory regions. Use sim-memopts module, via sim_do_commandf, to
1283 manage memory regions.
1284 (load_memory, store_memory): Use sim-core for memory model.
1286 * interp.c (address_translation): Delete all memory map code
1287 except line forcing 32 bit addresses.
1289 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1291 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1294 * interp.c (logfh, logfile): Delete globals.
1295 (sim_open, sim_close): Delete code opening & closing log file.
1296 (mips_option_handler): Delete -l and -n options.
1297 (OPTION mips_options): Ditto.
1299 * interp.c (OPTION mips_options): Rename option trace to dinero.
1300 (mips_option_handler): Update.
1302 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1304 * interp.c (fetch_str): New function.
1305 (sim_monitor): Rewrite using sim_read & sim_write.
1306 (sim_open): Check magic number.
1307 (sim_open): Write monitor vectors into memory using sim_write.
1308 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1309 (sim_read, sim_write): Simplify - transfer data one byte at a
1311 (load_memory, store_memory): Clarify meaning of parameter RAW.
1313 * sim-main.h (isHOST): Defete definition.
1314 (isTARGET): Mark as depreciated.
1315 (address_translation): Delete parameter HOST.
1317 * interp.c (address_translation): Delete parameter HOST.
1319 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1323 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1324 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1326 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1328 * mips.igen: Add model filter field to records.
1330 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1332 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1334 interp.c (sim_engine_run): Do not compile function sim_engine_run
1335 when WITH_IGEN == 1.
1337 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1338 target architecture.
1340 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1341 igen. Replace with configuration variables sim_igen_flags /
1344 * m16.igen: New file. Copy mips16 insns here.
1345 * mips.igen: From here.
1347 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1349 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1351 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1353 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1355 * gencode.c (build_instruction): Follow sim_write's lead in using
1356 BigEndianMem instead of !ByteSwapMem.
1358 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1360 * configure.in (sim_gen): Dependent on target, select type of
1361 generator. Always select old style generator.
1363 configure: Re-generate.
1365 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1367 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1368 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1369 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1370 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1371 SIM_@sim_gen@_*, set by autoconf.
1373 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1375 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1377 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1378 CURRENT_FLOATING_POINT instead.
1380 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1381 (address_translation): Raise exception InstructionFetch when
1382 translation fails and isINSTRUCTION.
1384 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1385 sim_engine_run): Change type of of vaddr and paddr to
1387 (address_translation, prefetch, load_memory, store_memory,
1388 cache_op): Change type of vAddr and pAddr to address_word.
1390 * gencode.c (build_instruction): Change type of vaddr and paddr to
1393 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1395 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1396 macro to obtain result of ALU op.
1398 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1400 * interp.c (sim_info): Call profile_print.
1402 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1404 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1406 * sim-main.h (WITH_PROFILE): Do not define, defined in
1407 common/sim-config.h. Use sim-profile module.
1408 (simPROFILE): Delete defintion.
1410 * interp.c (PROFILE): Delete definition.
1411 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1412 (sim_close): Delete code writing profile histogram.
1413 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1415 (sim_engine_run): Delete code profiling the PC.
1417 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1419 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1421 * interp.c (sim_monitor): Make register pointers of type
1424 * sim-main.h: Make registers of type unsigned_word not
1427 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1429 * interp.c (sync_operation): Rename from SyncOperation, make
1430 global, add SD argument.
1431 (prefetch): Rename from Prefetch, make global, add SD argument.
1432 (decode_coproc): Make global.
1434 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1436 * gencode.c (build_instruction): Generate DecodeCoproc not
1437 decode_coproc calls.
1439 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1440 (SizeFGR): Move to sim-main.h
1441 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1442 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1443 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1445 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1446 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1447 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1448 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1449 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1450 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1452 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1454 (sim-alu.h): Include.
1455 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1456 (sim_cia): Typedef to instruction_address.
1458 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1460 * Makefile.in (interp.o): Rename generated file engine.c to
1465 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1467 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1469 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1471 * gencode.c (build_instruction): For "FPSQRT", output correct
1472 number of arguments to Recip.
1474 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1476 * Makefile.in (interp.o): Depends on sim-main.h
1478 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1480 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1481 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1482 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1483 STATE, DSSTATE): Define
1484 (GPR, FGRIDX, ..): Define.
1486 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1487 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1488 (GPR, FGRIDX, ...): Delete macros.
1490 * interp.c: Update names to match defines from sim-main.h
1492 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1494 * interp.c (sim_monitor): Add SD argument.
1495 (sim_warning): Delete. Replace calls with calls to
1497 (sim_error): Delete. Replace calls with sim_io_error.
1498 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1499 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1500 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1502 (mips_size): Rename from sim_size. Add SD argument.
1504 * interp.c (simulator): Delete global variable.
1505 (callback): Delete global variable.
1506 (mips_option_handler, sim_open, sim_write, sim_read,
1507 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1508 sim_size,sim_monitor): Use sim_io_* not callback->*.
1509 (sim_open): ZALLOC simulator struct.
1510 (PROFILE): Do not define.
1512 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1514 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1515 support.h with corresponding code.
1517 * sim-main.h (word64, uword64), support.h: Move definition to
1519 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1522 * Makefile.in: Update dependencies
1523 * interp.c: Do not include.
1525 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1527 * interp.c (address_translation, load_memory, store_memory,
1528 cache_op): Rename to from AddressTranslation et.al., make global,
1531 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1534 * interp.c (SignalException): Rename to signal_exception, make
1537 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1539 * sim-main.h (SignalException, SignalExceptionInterrupt,
1540 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1541 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1542 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1545 * interp.c, support.h: Use.
1547 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1549 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1550 to value_fpr / store_fpr. Add SD argument.
1551 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1552 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1554 * sim-main.h (ValueFPR, StoreFPR): Define.
1556 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1558 * interp.c (sim_engine_run): Check consistency between configure
1559 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1562 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1563 (mips_fpu): Configure WITH_FLOATING_POINT.
1564 (mips_endian): Configure WITH_TARGET_ENDIAN.
1565 * configure: Update.
1567 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1569 * configure: Regenerated to track ../common/aclocal.m4 changes.
1571 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1573 * configure: Regenerated.
1575 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1577 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1579 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1581 * gencode.c (print_igen_insn_models): Assume certain architectures
1582 include all mips* instructions.
1583 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1586 * Makefile.in (tmp.igen): Add target. Generate igen input from
1589 * gencode.c (FEATURE_IGEN): Define.
1590 (main): Add --igen option. Generate output in igen format.
1591 (process_instructions): Format output according to igen option.
1592 (print_igen_insn_format): New function.
1593 (print_igen_insn_models): New function.
1594 (process_instructions): Only issue warnings and ignore
1595 instructions when no FEATURE_IGEN.
1597 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1599 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1602 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1604 * configure: Regenerated to track ../common/aclocal.m4 changes.
1606 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1608 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1609 SIM_RESERVED_BITS): Delete, moved to common.
1610 (SIM_EXTRA_CFLAGS): Update.
1612 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1614 * configure.in: Configure non-strict memory alignment.
1615 * configure: Regenerated to track ../common/aclocal.m4 changes.
1617 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1619 * configure: Regenerated to track ../common/aclocal.m4 changes.
1621 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1623 * gencode.c (SDBBP,DERET): Added (3900) insns.
1624 (RFE): Turn on for 3900.
1625 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1626 (dsstate): Made global.
1627 (SUBTARGET_R3900): Added.
1628 (CANCELDELAYSLOT): New.
1629 (SignalException): Ignore SystemCall rather than ignore and
1630 terminate. Add DebugBreakPoint handling.
1631 (decode_coproc): New insns RFE, DERET; and new registers Debug
1632 and DEPC protected by SUBTARGET_R3900.
1633 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1635 * Makefile.in,configure.in: Add mips subtarget option.
1636 * configure: Update.
1638 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1640 * gencode.c: Add r3900 (tx39).
1643 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1645 * gencode.c (build_instruction): Don't need to subtract 4 for
1648 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1650 * interp.c: Correct some HASFPU problems.
1652 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1654 * configure: Regenerated to track ../common/aclocal.m4 changes.
1656 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1658 * interp.c (mips_options): Fix samples option short form, should
1661 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1663 * interp.c (sim_info): Enable info code. Was just returning.
1665 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1667 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1670 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1672 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1674 (build_instruction): Ditto for LL.
1676 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1678 * configure: Regenerated to track ../common/aclocal.m4 changes.
1680 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1682 * configure: Regenerated to track ../common/aclocal.m4 changes.
1685 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1687 * interp.c (sim_open): Add call to sim_analyze_program, update
1690 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1692 * interp.c (sim_kill): Delete.
1693 (sim_create_inferior): Add ABFD argument. Set PC from same.
1694 (sim_load): Move code initializing trap handlers from here.
1695 (sim_open): To here.
1696 (sim_load): Delete, use sim-hload.c.
1698 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1700 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1702 * configure: Regenerated to track ../common/aclocal.m4 changes.
1705 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1707 * interp.c (sim_open): Add ABFD argument.
1708 (sim_load): Move call to sim_config from here.
1709 (sim_open): To here. Check return status.
1711 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1713 * gencode.c (build_instruction): Two arg MADD should
1714 not assign result to $0.
1716 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1718 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1719 * sim/mips/configure.in: Regenerate.
1721 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1723 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1724 signed8, unsigned8 et.al. types.
1726 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1727 hosts when selecting subreg.
1729 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1731 * interp.c (sim_engine_run): Reset the ZERO register to zero
1732 regardless of FEATURE_WARN_ZERO.
1733 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1735 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1737 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1738 (SignalException): For BreakPoints ignore any mode bits and just
1740 (SignalException): Always set the CAUSE register.
1742 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1744 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1745 exception has been taken.
1747 * interp.c: Implement the ERET and mt/f sr instructions.
1749 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1751 * interp.c (SignalException): Don't bother restarting an
1754 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1756 * interp.c (SignalException): Really take an interrupt.
1757 (interrupt_event): Only deliver interrupts when enabled.
1759 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761 * interp.c (sim_info): Only print info when verbose.
1762 (sim_info) Use sim_io_printf for output.
1764 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1766 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1769 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1771 * interp.c (sim_do_command): Check for common commands if a
1772 simulator specific command fails.
1774 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1776 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1777 and simBE when DEBUG is defined.
1779 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1781 * interp.c (interrupt_event): New function. Pass exception event
1782 onto exception handler.
1784 * configure.in: Check for stdlib.h.
1785 * configure: Regenerate.
1787 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1788 variable declaration.
1789 (build_instruction): Initialize memval1.
1790 (build_instruction): Add UNUSED attribute to byte, bigend,
1792 (build_operands): Ditto.
1794 * interp.c: Fix GCC warnings.
1795 (sim_get_quit_code): Delete.
1797 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1798 * Makefile.in: Ditto.
1799 * configure: Re-generate.
1801 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1803 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1805 * interp.c (mips_option_handler): New function parse argumes using
1807 (myname): Replace with STATE_MY_NAME.
1808 (sim_open): Delete check for host endianness - performed by
1810 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1811 (sim_open): Move much of the initialization from here.
1812 (sim_load): To here. After the image has been loaded and
1814 (sim_open): Move ColdReset from here.
1815 (sim_create_inferior): To here.
1816 (sim_open): Make FP check less dependant on host endianness.
1818 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1820 * interp.c (sim_set_callbacks): Delete.
1822 * interp.c (membank, membank_base, membank_size): Replace with
1823 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1824 (sim_open): Remove call to callback->init. gdb/run do this.
1828 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1830 * interp.c (big_endian_p): Delete, replaced by
1831 current_target_byte_order.
1833 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1835 * interp.c (host_read_long, host_read_word, host_swap_word,
1836 host_swap_long): Delete. Using common sim-endian.
1837 (sim_fetch_register, sim_store_register): Use H2T.
1838 (pipeline_ticks): Delete. Handled by sim-events.
1840 (sim_engine_run): Update.
1842 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1844 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1846 (SignalException): To here. Signal using sim_engine_halt.
1847 (sim_stop_reason): Delete, moved to common.
1849 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1851 * interp.c (sim_open): Add callback argument.
1852 (sim_set_callbacks): Delete SIM_DESC argument.
1855 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1857 * Makefile.in (SIM_OBJS): Add common modules.
1859 * interp.c (sim_set_callbacks): Also set SD callback.
1860 (set_endianness, xfer_*, swap_*): Delete.
1861 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1862 Change to functions using sim-endian macros.
1863 (control_c, sim_stop): Delete, use common version.
1864 (simulate): Convert into.
1865 (sim_engine_run): This function.
1866 (sim_resume): Delete.
1868 * interp.c (simulation): New variable - the simulator object.
1869 (sim_kind): Delete global - merged into simulation.
1870 (sim_load): Cleanup. Move PC assignment from here.
1871 (sim_create_inferior): To here.
1873 * sim-main.h: New file.
1874 * interp.c (sim-main.h): Include.
1876 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1878 * configure: Regenerated to track ../common/aclocal.m4 changes.
1880 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1882 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1884 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1886 * gencode.c (build_instruction): DIV instructions: check
1887 for division by zero and integer overflow before using
1888 host's division operation.
1890 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1892 * Makefile.in (SIM_OBJS): Add sim-load.o.
1893 * interp.c: #include bfd.h.
1894 (target_byte_order): Delete.
1895 (sim_kind, myname, big_endian_p): New static locals.
1896 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1897 after argument parsing. Recognize -E arg, set endianness accordingly.
1898 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1899 load file into simulator. Set PC from bfd.
1900 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1901 (set_endianness): Use big_endian_p instead of target_byte_order.
1903 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1905 * interp.c (sim_size): Delete prototype - conflicts with
1906 definition in remote-sim.h. Correct definition.
1908 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1910 * configure: Regenerated to track ../common/aclocal.m4 changes.
1913 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1915 * interp.c (sim_open): New arg `kind'.
1917 * configure: Regenerated to track ../common/aclocal.m4 changes.
1919 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1921 * configure: Regenerated to track ../common/aclocal.m4 changes.
1923 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1925 * interp.c (sim_open): Set optind to 0 before calling getopt.
1927 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1929 * configure: Regenerated to track ../common/aclocal.m4 changes.
1931 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1933 * interp.c : Replace uses of pr_addr with pr_uword64
1934 where the bit length is always 64 independent of SIM_ADDR.
1935 (pr_uword64) : added.
1937 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1939 * configure: Re-generate.
1941 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1943 * configure: Regenerate to track ../common/aclocal.m4 changes.
1945 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1947 * interp.c (sim_open): New SIM_DESC result. Argument is now
1949 (other sim_*): New SIM_DESC argument.
1951 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1953 * interp.c: Fix printing of addresses for non-64-bit targets.
1954 (pr_addr): Add function to print address based on size.
1956 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1958 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1960 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1962 * gencode.c (build_mips16_operands): Correct computation of base
1963 address for extended PC relative instruction.
1965 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1967 * interp.c (mips16_entry): Add support for floating point cases.
1968 (SignalException): Pass floating point cases to mips16_entry.
1969 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1971 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1973 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1974 and then set the state to fmt_uninterpreted.
1975 (COP_SW): Temporarily set the state to fmt_word while calling
1978 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1980 * gencode.c (build_instruction): The high order may be set in the
1981 comparison flags at any ISA level, not just ISA 4.
1983 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1985 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1986 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1987 * configure.in: sinclude ../common/aclocal.m4.
1988 * configure: Regenerated.
1990 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1992 * configure: Rebuild after change to aclocal.m4.
1994 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1996 * configure configure.in Makefile.in: Update to new configure
1997 scheme which is more compatible with WinGDB builds.
1998 * configure.in: Improve comment on how to run autoconf.
1999 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2000 * Makefile.in: Use autoconf substitution to install common
2003 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2005 * gencode.c (build_instruction): Use BigEndianCPU instead of
2008 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2010 * interp.c (sim_monitor): Make output to stdout visible in
2011 wingdb's I/O log window.
2013 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2015 * support.h: Undo previous change to SIGTRAP
2018 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2020 * interp.c (store_word, load_word): New static functions.
2021 (mips16_entry): New static function.
2022 (SignalException): Look for mips16 entry and exit instructions.
2023 (simulate): Use the correct index when setting fpr_state after
2024 doing a pending move.
2026 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2028 * interp.c: Fix byte-swapping code throughout to work on
2029 both little- and big-endian hosts.
2031 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2033 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2034 with gdb/config/i386/xm-windows.h.
2036 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2038 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2039 that messes up arithmetic shifts.
2041 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2043 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2044 SIGTRAP and SIGQUIT for _WIN32.
2046 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2048 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2049 force a 64 bit multiplication.
2050 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2051 destination register is 0, since that is the default mips16 nop
2054 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2056 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2057 (build_endian_shift): Don't check proc64.
2058 (build_instruction): Always set memval to uword64. Cast op2 to
2059 uword64 when shifting it left in memory instructions. Always use
2060 the same code for stores--don't special case proc64.
2062 * gencode.c (build_mips16_operands): Fix base PC value for PC
2064 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2066 * interp.c (simJALDELAYSLOT): Define.
2067 (JALDELAYSLOT): Define.
2068 (INDELAYSLOT, INJALDELAYSLOT): Define.
2069 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2071 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2073 * interp.c (sim_open): add flush_cache as a PMON routine
2074 (sim_monitor): handle flush_cache by ignoring it
2076 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2078 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2080 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2081 (BigEndianMem): Rename to ByteSwapMem and change sense.
2082 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2083 BigEndianMem references to !ByteSwapMem.
2084 (set_endianness): New function, with prototype.
2085 (sim_open): Call set_endianness.
2086 (sim_info): Use simBE instead of BigEndianMem.
2087 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2088 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2089 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2090 ifdefs, keeping the prototype declaration.
2091 (swap_word): Rewrite correctly.
2092 (ColdReset): Delete references to CONFIG. Delete endianness related
2093 code; moved to set_endianness.
2095 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2097 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2098 * interp.c (CHECKHILO): Define away.
2099 (simSIGINT): New macro.
2100 (membank_size): Increase from 1MB to 2MB.
2101 (control_c): New function.
2102 (sim_resume): Rename parameter signal to signal_number. Add local
2103 variable prev. Call signal before and after simulate.
2104 (sim_stop_reason): Add simSIGINT support.
2105 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2107 (sim_warning): Delete call to SignalException. Do call printf_filtered
2109 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2110 a call to sim_warning.
2112 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2114 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2115 16 bit instructions.
2117 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2119 Add support for mips16 (16 bit MIPS implementation):
2120 * gencode.c (inst_type): Add mips16 instruction encoding types.
2121 (GETDATASIZEINSN): Define.
2122 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2123 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2125 (MIPS16_DECODE): New table, for mips16 instructions.
2126 (bitmap_val): New static function.
2127 (struct mips16_op): Define.
2128 (mips16_op_table): New table, for mips16 operands.
2129 (build_mips16_operands): New static function.
2130 (process_instructions): If PC is odd, decode a mips16
2131 instruction. Break out instruction handling into new
2132 build_instruction function.
2133 (build_instruction): New static function, broken out of
2134 process_instructions. Check modifiers rather than flags for SHIFT
2135 bit count and m[ft]{hi,lo} direction.
2136 (usage): Pass program name to fprintf.
2137 (main): Remove unused variable this_option_optind. Change
2138 ``*loptarg++'' to ``loptarg++''.
2139 (my_strtoul): Parenthesize && within ||.
2140 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2141 (simulate): If PC is odd, fetch a 16 bit instruction, and
2142 increment PC by 2 rather than 4.
2143 * configure.in: Add case for mips16*-*-*.
2144 * configure: Rebuild.
2146 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2148 * interp.c: Allow -t to enable tracing in standalone simulator.
2149 Fix garbage output in trace file and error messages.
2151 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2153 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2154 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2155 * configure.in: Simplify using macros in ../common/aclocal.m4.
2156 * configure: Regenerated.
2157 * tconfig.in: New file.
2159 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2161 * interp.c: Fix bugs in 64-bit port.
2162 Use ansi function declarations for msvc compiler.
2163 Initialize and test file pointer in trace code.
2164 Prevent duplicate definition of LAST_EMED_REGNUM.
2166 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2168 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2170 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2172 * interp.c (SignalException): Check for explicit terminating
2174 * gencode.c: Pass instruction value through SignalException()
2175 calls for Trap, Breakpoint and Syscall.
2177 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2179 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2180 only used on those hosts that provide it.
2181 * configure.in: Add sqrt() to list of functions to be checked for.
2182 * config.in: Re-generated.
2183 * configure: Re-generated.
2185 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2187 * gencode.c (process_instructions): Call build_endian_shift when
2188 expanding STORE RIGHT, to fix swr.
2189 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2190 clear the high bits.
2191 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2192 Fix float to int conversions to produce signed values.
2194 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2196 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2197 (process_instructions): Correct handling of nor instruction.
2198 Correct shift count for 32 bit shift instructions. Correct sign
2199 extension for arithmetic shifts to not shift the number of bits in
2200 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2201 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2203 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2204 It's OK to have a mult follow a mult. What's not OK is to have a
2205 mult follow an mfhi.
2206 (Convert): Comment out incorrect rounding code.
2208 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2210 * interp.c (sim_monitor): Improved monitor printf
2211 simulation. Tidied up simulator warnings, and added "--log" option
2212 for directing warning message output.
2213 * gencode.c: Use sim_warning() rather than WARNING macro.
2215 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2217 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2218 getopt1.o, rather than on gencode.c. Link objects together.
2219 Don't link against -liberty.
2220 (gencode.o, getopt.o, getopt1.o): New targets.
2221 * gencode.c: Include <ctype.h> and "ansidecl.h".
2222 (AND): Undefine after including "ansidecl.h".
2223 (ULONG_MAX): Define if not defined.
2224 (OP_*): Don't define macros; now defined in opcode/mips.h.
2225 (main): Call my_strtoul rather than strtoul.
2226 (my_strtoul): New static function.
2228 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2230 * gencode.c (process_instructions): Generate word64 and uword64
2231 instead of `long long' and `unsigned long long' data types.
2232 * interp.c: #include sysdep.h to get signals, and define default
2234 * (Convert): Work around for Visual-C++ compiler bug with type
2236 * support.h: Make things compile under Visual-C++ by using
2237 __int64 instead of `long long'. Change many refs to long long
2238 into word64/uword64 typedefs.
2240 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2242 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2243 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2245 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2246 (AC_PROG_INSTALL): Added.
2247 (AC_PROG_CC): Moved to before configure.host call.
2248 * configure: Rebuilt.
2250 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2252 * configure.in: Define @SIMCONF@ depending on mips target.
2253 * configure: Rebuild.
2254 * Makefile.in (run): Add @SIMCONF@ to control simulator
2256 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2257 * interp.c: Remove some debugging, provide more detailed error
2258 messages, update memory accesses to use LOADDRMASK.
2260 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2262 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2263 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2265 * configure: Rebuild.
2266 * config.in: New file, generated by autoheader.
2267 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2268 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2269 HAVE_ANINT and HAVE_AINT, as appropriate.
2270 * Makefile.in (run): Use @LIBS@ rather than -lm.
2271 (interp.o): Depend upon config.h.
2272 (Makefile): Just rebuild Makefile.
2273 (clean): Remove stamp-h.
2274 (mostlyclean): Make the same as clean, not as distclean.
2275 (config.h, stamp-h): New targets.
2277 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2279 * interp.c (ColdReset): Fix boolean test. Make all simulator
2282 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2284 * interp.c (xfer_direct_word, xfer_direct_long,
2285 swap_direct_word, swap_direct_long, xfer_big_word,
2286 xfer_big_long, xfer_little_word, xfer_little_long,
2287 swap_word,swap_long): Added.
2288 * interp.c (ColdReset): Provide function indirection to
2289 host<->simulated_target transfer routines.
2290 * interp.c (sim_store_register, sim_fetch_register): Updated to
2291 make use of indirected transfer routines.
2293 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2295 * gencode.c (process_instructions): Ensure FP ABS instruction
2297 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2298 system call support.
2300 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2302 * interp.c (sim_do_command): Complain if callback structure not
2305 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2307 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2308 support for Sun hosts.
2309 * Makefile.in (gencode): Ensure the host compiler and libraries
2310 used for cross-hosted build.
2312 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2314 * interp.c, gencode.c: Some more (TODO) tidying.
2316 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2318 * gencode.c, interp.c: Replaced explicit long long references with
2319 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2320 * support.h (SET64LO, SET64HI): Macros added.
2322 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2324 * configure: Regenerate with autoconf 2.7.
2326 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2328 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2329 * support.h: Remove superfluous "1" from #if.
2330 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2332 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2334 * interp.c (StoreFPR): Control UndefinedResult() call on
2335 WARN_RESULT manifest.
2337 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2339 * gencode.c: Tidied instruction decoding, and added FP instruction
2342 * interp.c: Added dineroIII, and BSD profiling support. Also
2343 run-time FP handling.
2345 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2347 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2348 gencode.c, interp.c, support.h: created.
projects / external / binutils.git / blob