1 2011-12-03 Mike Frysinger <vapier@gentoo.org>
3 * aclocal.m4: New file.
4 * configure: Regenerate.
6 2011-10-19 Mike Frysinger <vapier@gentoo.org>
8 * configure: Regenerate after common/acinclude.m4 update.
10 2011-10-17 Mike Frysinger <vapier@gentoo.org>
12 * configure.ac: Change include to common/acinclude.m4.
14 2011-10-17 Mike Frysinger <vapier@gentoo.org>
16 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
17 call. Replace common.m4 include with SIM_AC_COMMON.
18 * configure: Regenerate.
20 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
22 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
24 (tmp-mach-multi): Exit early when igen fails.
26 2011-07-05 Mike Frysinger <vapier@gentoo.org>
28 * interp.c (sim_do_command): Delete.
30 2011-02-14 Mike Frysinger <vapier@gentoo.org>
32 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
33 (tx3904sio_fifo_reset): Likewise.
34 * interp.c (sim_monitor): Likewise.
36 2010-04-14 Mike Frysinger <vapier@gentoo.org>
38 * interp.c (sim_write): Add const to buffer arg.
40 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
42 * interp.c: Don't include sysdep.h
44 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
46 * configure: Regenerate.
48 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
50 * config.in: Regenerate.
51 * configure: Likewise.
53 * configure: Regenerate.
55 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
57 * configure: Regenerate to track ../common/common.m4 changes.
60 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
61 Daniel Jacobowitz <dan@codesourcery.com>
62 Joseph Myers <joseph@codesourcery.com>
64 * configure: Regenerate.
66 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
68 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
69 that unconditionally allows fmt_ps.
70 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
71 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
72 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
73 filter from 64,f to 32,f.
74 (PREFX): Change filter from 64 to 32.
75 (LDXC1, LUXC1): Provide separate mips32r2 implementations
76 that use do_load_double instead of do_load. Make both LUXC1
77 versions unpredictable if SizeFGR () != 64.
78 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
79 instead of do_store. Remove unused variable. Make both SUXC1
80 versions unpredictable if SizeFGR () != 64.
82 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
84 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
85 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
88 2007-09-04 Nick Clifton <nickc@redhat.com>
90 * interp.c (options enum): Add OPTION_INFO_MEMORY.
91 (display_mem_info): New static variable.
92 (mips_option_handler): Handle OPTION_INFO_MEMORY.
93 (mips_options): Add info-memory and memory-info.
94 (sim_open): After processing the command line and board
95 specification, check display_mem_info. If it is set then
96 call the real handler for the --memory-info command line
99 2007-08-24 Joel Brobecker <brobecker@adacore.com>
101 * configure.ac: Change license of multi-run.c to GPL version 3.
102 * configure: Regenerate.
104 2007-06-28 Richard Sandiford <richard@codesourcery.com>
106 * configure.ac, configure: Revert last patch.
108 2007-06-26 Richard Sandiford <richard@codesourcery.com>
110 * configure.ac (sim_mipsisa3264_configs): New variable.
111 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
112 every configuration support all four targets, using the triplet to
113 determine the default.
114 * configure: Regenerate.
116 2007-06-25 Richard Sandiford <richard@codesourcery.com>
118 * Makefile.in (m16run.o): New rule.
120 2007-05-15 Thiemo Seufer <ths@mips.com>
122 * mips3264r2.igen (DSHD): Fix compile warning.
124 2007-05-14 Thiemo Seufer <ths@mips.com>
126 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
127 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
128 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
129 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
132 2007-03-01 Thiemo Seufer <ths@mips.com>
134 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
137 2007-02-20 Thiemo Seufer <ths@mips.com>
139 * dsp.igen: Update copyright notice.
140 * dsp2.igen: Fix copyright notice.
142 2007-02-20 Thiemo Seufer <ths@mips.com>
143 Chao-Ying Fu <fu@mips.com>
145 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
146 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
147 Add dsp2 to sim_igen_machine.
148 * configure: Regenerate.
149 * dsp.igen (do_ph_op): Add MUL support when op = 2.
150 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
151 (mulq_rs.ph): Use do_ph_mulq.
152 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
153 * mips.igen: Add dsp2 model and include dsp2.igen.
154 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
155 for *mips32r2, *mips64r2, *dsp.
156 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
157 for *mips32r2, *mips64r2, *dsp2.
158 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
160 2007-02-19 Thiemo Seufer <ths@mips.com>
161 Nigel Stephens <nigel@mips.com>
163 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
164 jumps with hazard barrier.
166 2007-02-19 Thiemo Seufer <ths@mips.com>
167 Nigel Stephens <nigel@mips.com>
169 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
170 after each call to sim_io_write.
172 2007-02-19 Thiemo Seufer <ths@mips.com>
173 Nigel Stephens <nigel@mips.com>
175 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
176 supported by this simulator.
177 (decode_coproc): Recognise additional CP0 Config registers
180 2007-02-19 Thiemo Seufer <ths@mips.com>
181 Nigel Stephens <nigel@mips.com>
182 David Ung <davidu@mips.com>
184 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
185 uninterpreted formats. If fmt is one of the uninterpreted types
186 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
187 fmt_word, and fmt_uninterpreted_64 like fmt_long.
188 (store_fpr): When writing an invalid odd register, set the
189 matching even register to fmt_unknown, not the following register.
190 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
191 the the memory window at offset 0 set by --memory-size command
193 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
195 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
197 (sim_monitor): When returning the memory size to the MIPS
198 application, use the value in STATE_MEM_SIZE, not an arbitrary
200 (cop_lw): Don' mess around with FPR_STATE, just pass
201 fmt_uninterpreted_32 to StoreFPR.
203 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
205 * mips.igen (not_word_value): Single version for mips32, mips64
208 2007-02-19 Thiemo Seufer <ths@mips.com>
209 Nigel Stephens <nigel@mips.com>
211 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
214 2007-02-17 Thiemo Seufer <ths@mips.com>
216 * configure.ac (mips*-sde-elf*): Move in front of generic machine
218 * configure: Regenerate.
220 2007-02-17 Thiemo Seufer <ths@mips.com>
222 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
223 Add mdmx to sim_igen_machine.
224 (mipsisa64*-*-*): Likewise. Remove dsp.
225 (mipsisa32*-*-*): Remove dsp.
226 * configure: Regenerate.
228 2007-02-13 Thiemo Seufer <ths@mips.com>
230 * configure.ac: Add mips*-sde-elf* target.
231 * configure: Regenerate.
233 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
235 * acconfig.h: Remove.
236 * config.in, configure: Regenerate.
238 2006-11-07 Thiemo Seufer <ths@mips.com>
240 * dsp.igen (do_w_op): Fix compiler warning.
242 2006-08-29 Thiemo Seufer <ths@mips.com>
243 David Ung <davidu@mips.com>
245 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
247 * configure: Regenerate.
248 * mips.igen (model): Add smartmips.
249 (MADDU): Increment ACX if carry.
250 (do_mult): Clear ACX.
251 (ROR,RORV): Add smartmips.
252 (include): Include smartmips.igen.
253 * sim-main.h (ACX): Set to REGISTERS[89].
254 * smartmips.igen: New file.
256 2006-08-29 Thiemo Seufer <ths@mips.com>
257 David Ung <davidu@mips.com>
259 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
260 mips3264r2.igen. Add missing dependency rules.
261 * m16e.igen: Support for mips16e save/restore instructions.
263 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
265 * configure: Regenerated.
267 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
269 * configure: Regenerated.
271 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
273 * configure: Regenerated.
275 2006-05-15 Chao-ying Fu <fu@mips.com>
277 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
279 2006-04-18 Nick Clifton <nickc@redhat.com>
281 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
284 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
286 * configure: Regenerate.
288 2005-12-14 Chao-ying Fu <fu@mips.com>
290 * Makefile.in (SIM_OBJS): Add dsp.o.
291 (dsp.o): New dependency.
292 (IGEN_INCLUDE): Add dsp.igen.
293 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
294 mipsisa64*-*-*): Add dsp to sim_igen_machine.
295 * configure: Regenerate.
296 * mips.igen: Add dsp model and include dsp.igen.
297 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
298 because these instructions are extended in DSP ASE.
299 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
300 adding 6 DSP accumulator registers and 1 DSP control register.
301 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
302 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
303 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
304 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
305 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
306 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
307 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
308 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
309 DSPCR_CCOND_SMASK): New define.
310 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
311 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
313 2005-07-08 Ian Lance Taylor <ian@airs.com>
315 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
317 2005-06-16 David Ung <davidu@mips.com>
318 Nigel Stephens <nigel@mips.com>
320 * mips.igen: New mips16e model and include m16e.igen.
321 (check_u64): Add mips16e tag.
322 * m16e.igen: New file for MIPS16e instructions.
323 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
324 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
326 * configure: Regenerate.
328 2005-05-26 David Ung <davidu@mips.com>
330 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
331 tags to all instructions which are applicable to the new ISAs.
332 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
334 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
336 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
338 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
339 * configure: Regenerate.
341 2005-03-23 Mark Kettenis <kettenis@gnu.org>
343 * configure: Regenerate.
345 2005-01-14 Andrew Cagney <cagney@gnu.org>
347 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
348 explicit call to AC_CONFIG_HEADER.
349 * configure: Regenerate.
351 2005-01-12 Andrew Cagney <cagney@gnu.org>
353 * configure.ac: Update to use ../common/common.m4.
354 * configure: Re-generate.
356 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
358 * configure: Regenerated to track ../common/aclocal.m4 changes.
360 2005-01-07 Andrew Cagney <cagney@gnu.org>
362 * configure.ac: Rename configure.in, require autoconf 2.59.
363 * configure: Re-generate.
365 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
367 * configure: Regenerate for ../common/aclocal.m4 update.
369 2004-09-24 Monika Chaddha <monika@acmet.com>
371 Committed by Andrew Cagney.
372 * m16.igen (CMP, CMPI): Fix assembler.
374 2004-08-18 Chris Demetriou <cgd@broadcom.com>
376 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
377 * configure: Regenerate.
379 2004-06-25 Chris Demetriou <cgd@broadcom.com>
381 * configure.in (sim_m16_machine): Include mipsIII.
382 * configure: Regenerate.
384 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
386 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
388 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
390 2004-04-10 Chris Demetriou <cgd@broadcom.com>
392 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
394 2004-04-09 Chris Demetriou <cgd@broadcom.com>
396 * mips.igen (check_fmt): Remove.
397 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
398 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
399 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
400 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
401 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
402 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
403 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
404 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
405 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
406 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
408 2004-04-09 Chris Demetriou <cgd@broadcom.com>
410 * sb1.igen (check_sbx): New function.
411 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
413 2004-03-29 Chris Demetriou <cgd@broadcom.com>
414 Richard Sandiford <rsandifo@redhat.com>
416 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
417 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
418 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
419 separate implementations for mipsIV and mipsV. Use new macros to
420 determine whether the restrictions apply.
422 2004-01-19 Chris Demetriou <cgd@broadcom.com>
424 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
425 (check_mult_hilo): Improve comments.
426 (check_div_hilo): Likewise. Also, fork off a new version
427 to handle mips32/mips64 (since there are no hazards to check
430 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
432 * mips.igen (do_dmultx): Fix check for negative operands.
434 2003-05-16 Ian Lance Taylor <ian@airs.com>
436 * Makefile.in (SHELL): Make sure this is defined.
437 (various): Use $(SHELL) whenever we invoke move-if-change.
439 2003-05-03 Chris Demetriou <cgd@broadcom.com>
441 * cp1.c: Tweak attribution slightly.
444 * mdmx.igen: Likewise.
445 * mips3d.igen: Likewise.
446 * sb1.igen: Likewise.
448 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
450 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
453 2003-02-27 Andrew Cagney <cagney@redhat.com>
455 * interp.c (sim_open): Rename _bfd to bfd.
456 (sim_create_inferior): Ditto.
458 2003-01-14 Chris Demetriou <cgd@broadcom.com>
460 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
462 2003-01-14 Chris Demetriou <cgd@broadcom.com>
464 * mips.igen (EI, DI): Remove.
466 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
468 * Makefile.in (tmp-run-multi): Fix mips16 filter.
470 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
471 Andrew Cagney <ac131313@redhat.com>
472 Gavin Romig-Koch <gavin@redhat.com>
473 Graydon Hoare <graydon@redhat.com>
474 Aldy Hernandez <aldyh@redhat.com>
475 Dave Brolley <brolley@redhat.com>
476 Chris Demetriou <cgd@broadcom.com>
478 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
479 (sim_mach_default): New variable.
480 (mips64vr-*-*, mips64vrel-*-*): New configurations.
481 Add a new simulator generator, MULTI.
482 * configure: Regenerate.
483 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
484 (multi-run.o): New dependency.
485 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
486 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
487 (tmp-multi): Combine them.
488 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
489 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
490 (distclean-extra): New rule.
491 * sim-main.h: Include bfd.h.
492 (MIPS_MACH): New macro.
493 * mips.igen (vr4120, vr5400, vr5500): New models.
494 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
495 * vr.igen: Replace with new version.
497 2003-01-04 Chris Demetriou <cgd@broadcom.com>
499 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
500 * configure: Regenerate.
502 2002-12-31 Chris Demetriou <cgd@broadcom.com>
504 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
505 * mips.igen: Remove all invocations of check_branch_bug and
508 2002-12-16 Chris Demetriou <cgd@broadcom.com>
510 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
512 2002-07-30 Chris Demetriou <cgd@broadcom.com>
514 * mips.igen (do_load_double, do_store_double): New functions.
515 (LDC1, SDC1): Rename to...
516 (LDC1b, SDC1b): respectively.
517 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
519 2002-07-29 Michael Snyder <msnyder@redhat.com>
521 * cp1.c (fp_recip2): Modify initialization expression so that
522 GCC will recognize it as constant.
524 2002-06-18 Chris Demetriou <cgd@broadcom.com>
526 * mdmx.c (SD_): Delete.
527 (Unpredictable): Re-define, for now, to directly invoke
528 unpredictable_action().
529 (mdmx_acc_op): Fix error in .ob immediate handling.
531 2002-06-18 Andrew Cagney <cagney@redhat.com>
533 * interp.c (sim_firmware_command): Initialize `address'.
535 2002-06-16 Andrew Cagney <ac131313@redhat.com>
537 * configure: Regenerated to track ../common/aclocal.m4 changes.
539 2002-06-14 Chris Demetriou <cgd@broadcom.com>
540 Ed Satterthwaite <ehs@broadcom.com>
542 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
543 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
544 * mips.igen: Include mips3d.igen.
545 (mips3d): New model name for MIPS-3D ASE instructions.
546 (CVT.W.fmt): Don't use this instruction for word (source) format
548 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
549 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
550 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
551 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
552 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
553 (RSquareRoot1, RSquareRoot2): New macros.
554 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
555 (fp_rsqrt2): New functions.
556 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
557 * configure: Regenerate.
559 2002-06-13 Chris Demetriou <cgd@broadcom.com>
560 Ed Satterthwaite <ehs@broadcom.com>
562 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
563 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
564 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
565 (convert): Note that this function is not used for paired-single
567 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
568 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
569 (check_fmt_p): Enable paired-single support.
570 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
571 (PUU.PS): New instructions.
572 (CVT.S.fmt): Don't use this instruction for paired-single format
574 * sim-main.h (FP_formats): New value 'fmt_ps.'
575 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
576 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
578 2002-06-12 Chris Demetriou <cgd@broadcom.com>
580 * mips.igen: Fix formatting of function calls in
583 2002-06-12 Chris Demetriou <cgd@broadcom.com>
585 * mips.igen (MOVN, MOVZ): Trace result.
586 (TNEI): Print "tnei" as the opcode name in traces.
587 (CEIL.W): Add disassembly string for traces.
588 (RSQRT.fmt): Make location of disassembly string consistent
589 with other instructions.
591 2002-06-12 Chris Demetriou <cgd@broadcom.com>
593 * mips.igen (X): Delete unused function.
595 2002-06-08 Andrew Cagney <cagney@redhat.com>
597 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
599 2002-06-07 Chris Demetriou <cgd@broadcom.com>
600 Ed Satterthwaite <ehs@broadcom.com>
602 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
603 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
604 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
605 (fp_nmsub): New prototypes.
606 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
607 (NegMultiplySub): New defines.
608 * mips.igen (RSQRT.fmt): Use RSquareRoot().
609 (MADD.D, MADD.S): Replace with...
610 (MADD.fmt): New instruction.
611 (MSUB.D, MSUB.S): Replace with...
612 (MSUB.fmt): New instruction.
613 (NMADD.D, NMADD.S): Replace with...
614 (NMADD.fmt): New instruction.
615 (NMSUB.D, MSUB.S): Replace with...
616 (NMSUB.fmt): New instruction.
618 2002-06-07 Chris Demetriou <cgd@broadcom.com>
619 Ed Satterthwaite <ehs@broadcom.com>
621 * cp1.c: Fix more comment spelling and formatting.
622 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
623 (denorm_mode): New function.
624 (fpu_unary, fpu_binary): Round results after operation, collect
625 status from rounding operations, and update the FCSR.
626 (convert): Collect status from integer conversions and rounding
627 operations, and update the FCSR. Adjust NaN values that result
628 from conversions. Convert to use sim_io_eprintf rather than
629 fprintf, and remove some debugging code.
630 * cp1.h (fenr_FS): New define.
632 2002-06-07 Chris Demetriou <cgd@broadcom.com>
634 * cp1.c (convert): Remove unusable debugging code, and move MIPS
635 rounding mode to sim FP rounding mode flag conversion code into...
636 (rounding_mode): New function.
638 2002-06-07 Chris Demetriou <cgd@broadcom.com>
640 * cp1.c: Clean up formatting of a few comments.
641 (value_fpr): Reformat switch statement.
643 2002-06-06 Chris Demetriou <cgd@broadcom.com>
644 Ed Satterthwaite <ehs@broadcom.com>
647 * sim-main.h: Include cp1.h.
648 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
649 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
650 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
651 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
652 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
653 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
654 * cp1.c: Don't include sim-fpu.h; already included by
655 sim-main.h. Clean up formatting of some comments.
656 (NaN, Equal, Less): Remove.
657 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
658 (fp_cmp): New functions.
659 * mips.igen (do_c_cond_fmt): Remove.
660 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
661 Compare. Add result tracing.
662 (CxC1): Remove, replace with...
663 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
664 (DMxC1): Remove, replace with...
665 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
666 (MxC1): Remove, replace with...
667 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
669 2002-06-04 Chris Demetriou <cgd@broadcom.com>
671 * sim-main.h (FGRIDX): Remove, replace all uses with...
672 (FGR_BASE): New macro.
673 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
674 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
675 (NR_FGR, FGR): Likewise.
676 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
677 * mips.igen: Likewise.
679 2002-06-04 Chris Demetriou <cgd@broadcom.com>
681 * cp1.c: Add an FSF Copyright notice to this file.
683 2002-06-04 Chris Demetriou <cgd@broadcom.com>
684 Ed Satterthwaite <ehs@broadcom.com>
686 * cp1.c (Infinity): Remove.
687 * sim-main.h (Infinity): Likewise.
689 * cp1.c (fp_unary, fp_binary): New functions.
690 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
691 (fp_sqrt): New functions, implemented in terms of the above.
692 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
693 (Recip, SquareRoot): Remove (replaced by functions above).
694 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
695 (fp_recip, fp_sqrt): New prototypes.
696 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
697 (Recip, SquareRoot): Replace prototypes with #defines which
698 invoke the functions above.
700 2002-06-03 Chris Demetriou <cgd@broadcom.com>
702 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
703 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
704 file, remove PARAMS from prototypes.
705 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
706 simulator state arguments.
707 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
708 pass simulator state arguments.
709 * cp1.c (SD): Redefine as CPU_STATE(cpu).
710 (store_fpr, convert): Remove 'sd' argument.
711 (value_fpr): Likewise. Convert to use 'SD' instead.
713 2002-06-03 Chris Demetriou <cgd@broadcom.com>
715 * cp1.c (Min, Max): Remove #if 0'd functions.
716 * sim-main.h (Min, Max): Remove.
718 2002-06-03 Chris Demetriou <cgd@broadcom.com>
720 * cp1.c: fix formatting of switch case and default labels.
721 * interp.c: Likewise.
722 * sim-main.c: Likewise.
724 2002-06-03 Chris Demetriou <cgd@broadcom.com>
726 * cp1.c: Clean up comments which describe FP formats.
727 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
729 2002-06-03 Chris Demetriou <cgd@broadcom.com>
730 Ed Satterthwaite <ehs@broadcom.com>
732 * configure.in (mipsisa64sb1*-*-*): New target for supporting
733 Broadcom SiByte SB-1 processor configurations.
734 * configure: Regenerate.
735 * sb1.igen: New file.
736 * mips.igen: Include sb1.igen.
738 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
739 * mdmx.igen: Add "sb1" model to all appropriate functions and
741 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
742 (ob_func, ob_acc): Reference the above.
743 (qh_acc): Adjust to keep the same size as ob_acc.
744 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
745 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
747 2002-06-03 Chris Demetriou <cgd@broadcom.com>
749 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
751 2002-06-02 Chris Demetriou <cgd@broadcom.com>
752 Ed Satterthwaite <ehs@broadcom.com>
754 * mips.igen (mdmx): New (pseudo-)model.
755 * mdmx.c, mdmx.igen: New files.
756 * Makefile.in (SIM_OBJS): Add mdmx.o.
757 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
759 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
760 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
761 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
762 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
763 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
764 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
765 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
766 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
767 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
768 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
769 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
770 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
771 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
772 (qh_fmtsel): New macros.
773 (_sim_cpu): New member "acc".
774 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
775 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
777 2002-05-01 Chris Demetriou <cgd@broadcom.com>
779 * interp.c: Use 'deprecated' rather than 'depreciated.'
780 * sim-main.h: Likewise.
782 2002-05-01 Chris Demetriou <cgd@broadcom.com>
784 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
785 which wouldn't compile anyway.
786 * sim-main.h (unpredictable_action): New function prototype.
787 (Unpredictable): Define to call igen function unpredictable().
788 (NotWordValue): New macro to call igen function not_word_value().
789 (UndefinedResult): Remove.
790 * interp.c (undefined_result): Remove.
791 (unpredictable_action): New function.
792 * mips.igen (not_word_value, unpredictable): New functions.
793 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
794 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
795 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
796 NotWordValue() to check for unpredictable inputs, then
797 Unpredictable() to handle them.
799 2002-02-24 Chris Demetriou <cgd@broadcom.com>
801 * mips.igen: Fix formatting of calls to Unpredictable().
803 2002-04-20 Andrew Cagney <ac131313@redhat.com>
805 * interp.c (sim_open): Revert previous change.
807 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
809 * interp.c (sim_open): Disable chunk of code that wrote code in
810 vector table entries.
812 2002-03-19 Chris Demetriou <cgd@broadcom.com>
814 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
815 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
818 2002-03-19 Chris Demetriou <cgd@broadcom.com>
820 * cp1.c: Fix many formatting issues.
822 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
824 * cp1.c (fpu_format_name): New function to replace...
825 (DOFMT): This. Delete, and update all callers.
826 (fpu_rounding_mode_name): New function to replace...
827 (RMMODE): This. Delete, and update all callers.
829 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
831 * interp.c: Move FPU support routines from here to...
832 * cp1.c: Here. New file.
833 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
836 2002-03-12 Chris Demetriou <cgd@broadcom.com>
838 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
839 * mips.igen (mips32, mips64): New models, add to all instructions
840 and functions as appropriate.
841 (loadstore_ea, check_u64): New variant for model mips64.
842 (check_fmt_p): New variant for models mipsV and mips64, remove
843 mipsV model marking fro other variant.
846 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
847 for mips32 and mips64.
848 (DCLO, DCLZ): New instructions for mips64.
850 2002-03-07 Chris Demetriou <cgd@broadcom.com>
852 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
853 immediate or code as a hex value with the "%#lx" format.
854 (ANDI): Likewise, and fix printed instruction name.
856 2002-03-05 Chris Demetriou <cgd@broadcom.com>
858 * sim-main.h (UndefinedResult, Unpredictable): New macros
859 which currently do nothing.
861 2002-03-05 Chris Demetriou <cgd@broadcom.com>
863 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
864 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
865 (status_CU3): New definitions.
867 * sim-main.h (ExceptionCause): Add new values for MIPS32
868 and MIPS64: MDMX, MCheck, CacheErr. Update comments
869 for DebugBreakPoint and NMIReset to note their status in
871 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
872 (SignalExceptionCacheErr): New exception macros.
874 2002-03-05 Chris Demetriou <cgd@broadcom.com>
876 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
877 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
879 (SignalExceptionCoProcessorUnusable): Take as argument the
880 unusable coprocessor number.
882 2002-03-05 Chris Demetriou <cgd@broadcom.com>
884 * mips.igen: Fix formatting of all SignalException calls.
886 2002-03-05 Chris Demetriou <cgd@broadcom.com>
888 * sim-main.h (SIGNEXTEND): Remove.
890 2002-03-04 Chris Demetriou <cgd@broadcom.com>
892 * mips.igen: Remove gencode comment from top of file, fix
893 spelling in another comment.
895 2002-03-04 Chris Demetriou <cgd@broadcom.com>
897 * mips.igen (check_fmt, check_fmt_p): New functions to check
898 whether specific floating point formats are usable.
899 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
900 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
901 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
902 Use the new functions.
903 (do_c_cond_fmt): Remove format checks...
904 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
906 2002-03-03 Chris Demetriou <cgd@broadcom.com>
908 * mips.igen: Fix formatting of check_fpu calls.
910 2002-03-03 Chris Demetriou <cgd@broadcom.com>
912 * mips.igen (FLOOR.L.fmt): Store correct destination register.
914 2002-03-03 Chris Demetriou <cgd@broadcom.com>
916 * mips.igen: Remove whitespace at end of lines.
918 2002-03-02 Chris Demetriou <cgd@broadcom.com>
920 * mips.igen (loadstore_ea): New function to do effective
921 address calculations.
922 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
923 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
924 CACHE): Use loadstore_ea to do effective address computations.
926 2002-03-02 Chris Demetriou <cgd@broadcom.com>
928 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
929 * mips.igen (LL, CxC1, MxC1): Likewise.
931 2002-03-02 Chris Demetriou <cgd@broadcom.com>
933 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
934 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
935 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
936 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
937 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
938 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
939 Don't split opcode fields by hand, use the opcode field values
942 2002-03-01 Chris Demetriou <cgd@broadcom.com>
944 * mips.igen (do_divu): Fix spacing.
946 * mips.igen (do_dsllv): Move to be right before DSLLV,
947 to match the rest of the do_<shift> functions.
949 2002-03-01 Chris Demetriou <cgd@broadcom.com>
951 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
952 DSRL32, do_dsrlv): Trace inputs and results.
954 2002-03-01 Chris Demetriou <cgd@broadcom.com>
956 * mips.igen (CACHE): Provide instruction-printing string.
958 * interp.c (signal_exception): Comment tokens after #endif.
960 2002-02-28 Chris Demetriou <cgd@broadcom.com>
962 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
963 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
964 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
965 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
966 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
967 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
968 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
969 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
971 2002-02-28 Chris Demetriou <cgd@broadcom.com>
973 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
974 instruction-printing string.
975 (LWU): Use '64' as the filter flag.
977 2002-02-28 Chris Demetriou <cgd@broadcom.com>
979 * mips.igen (SDXC1): Fix instruction-printing string.
981 2002-02-28 Chris Demetriou <cgd@broadcom.com>
983 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
986 2002-02-27 Chris Demetriou <cgd@broadcom.com>
988 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
991 2002-02-27 Chris Demetriou <cgd@broadcom.com>
993 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
994 add a comma) so that it more closely match the MIPS ISA
995 documentation opcode partitioning.
996 (PREF): Put useful names on opcode fields, and include
997 instruction-printing string.
999 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1001 * mips.igen (check_u64): New function which in the future will
1002 check whether 64-bit instructions are usable and signal an
1003 exception if not. Currently a no-op.
1004 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1005 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1006 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1007 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1009 * mips.igen (check_fpu): New function which in the future will
1010 check whether FPU instructions are usable and signal an exception
1011 if not. Currently a no-op.
1012 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1013 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1014 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1015 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1016 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1017 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1018 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1019 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1021 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1023 * mips.igen (do_load_left, do_load_right): Move to be immediately
1025 (do_store_left, do_store_right): Move to be immediately following
1028 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1030 * mips.igen (mipsV): New model name. Also, add it to
1031 all instructions and functions where it is appropriate.
1033 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1035 * mips.igen: For all functions and instructions, list model
1036 names that support that instruction one per line.
1038 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1040 * mips.igen: Add some additional comments about supported
1041 models, and about which instructions go where.
1042 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1043 order as is used in the rest of the file.
1045 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1047 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1048 indicating that ALU32_END or ALU64_END are there to check
1050 (DADD): Likewise, but also remove previous comment about
1053 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1055 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1056 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1057 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1058 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1059 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1060 fields (i.e., add and move commas) so that they more closely
1061 match the MIPS ISA documentation opcode partitioning.
1063 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1065 * mips.igen (ADDI): Print immediate value.
1066 (BREAK): Print code.
1067 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1068 (SLL): Print "nop" specially, and don't run the code
1069 that does the shift for the "nop" case.
1071 2001-11-17 Fred Fish <fnf@redhat.com>
1073 * sim-main.h (float_operation): Move enum declaration outside
1074 of _sim_cpu struct declaration.
1076 2001-04-12 Jim Blandy <jimb@redhat.com>
1078 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1079 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1081 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1082 PENDING_FILL, and you can get the intended effect gracefully by
1083 calling PENDING_SCHED directly.
1085 2001-02-23 Ben Elliston <bje@redhat.com>
1087 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1088 already defined elsewhere.
1090 2001-02-19 Ben Elliston <bje@redhat.com>
1092 * sim-main.h (sim_monitor): Return an int.
1093 * interp.c (sim_monitor): Add return values.
1094 (signal_exception): Handle error conditions from sim_monitor.
1096 2001-02-08 Ben Elliston <bje@redhat.com>
1098 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1099 (store_memory): Likewise, pass cia to sim_core_write*.
1101 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1103 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1104 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1106 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1108 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1109 * Makefile.in: Don't delete *.igen when cleaning directory.
1111 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1113 * m16.igen (break): Call SignalException not sim_engine_halt.
1115 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1117 From Jason Eckhardt:
1118 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1120 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1122 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1124 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1126 * mips.igen (do_dmultx): Fix typo.
1128 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1130 * configure: Regenerated to track ../common/aclocal.m4 changes.
1132 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1134 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1136 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1138 * sim-main.h (GPR_CLEAR): Define macro.
1140 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1142 * interp.c (decode_coproc): Output long using %lx and not %s.
1144 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1146 * interp.c (sim_open): Sort & extend dummy memory regions for
1147 --board=jmr3904 for eCos.
1149 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1151 * configure: Regenerated.
1153 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1155 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1156 calls, conditional on the simulator being in verbose mode.
1158 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1160 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1161 cache don't get ReservedInstruction traps.
1163 1999-11-29 Mark Salter <msalter@cygnus.com>
1165 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1166 to clear status bits in sdisr register. This is how the hardware works.
1168 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1169 being used by cygmon.
1171 1999-11-11 Andrew Haley <aph@cygnus.com>
1173 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1176 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1178 * mips.igen (MULT): Correct previous mis-applied patch.
1180 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1182 * mips.igen (delayslot32): Handle sequence like
1183 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1184 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1185 (MULT): Actually pass the third register...
1187 1999-09-03 Mark Salter <msalter@cygnus.com>
1189 * interp.c (sim_open): Added more memory aliases for additional
1190 hardware being touched by cygmon on jmr3904 board.
1192 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1194 * configure: Regenerated to track ../common/aclocal.m4 changes.
1196 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1198 * interp.c (sim_store_register): Handle case where client - GDB -
1199 specifies that a 4 byte register is 8 bytes in size.
1200 (sim_fetch_register): Ditto.
1202 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1204 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1205 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1206 (idt_monitor_base): Base address for IDT monitor traps.
1207 (pmon_monitor_base): Ditto for PMON.
1208 (lsipmon_monitor_base): Ditto for LSI PMON.
1209 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1210 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1211 (sim_firmware_command): New function.
1212 (mips_option_handler): Call it for OPTION_FIRMWARE.
1213 (sim_open): Allocate memory for idt_monitor region. If "--board"
1214 option was given, add no monitor by default. Add BREAK hooks only if
1215 monitors are also there.
1217 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1219 * interp.c (sim_monitor): Flush output before reading input.
1221 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1223 * tconfig.in (SIM_HANDLES_LMA): Always define.
1225 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1227 From Mark Salter <msalter@cygnus.com>:
1228 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1229 (sim_open): Add setup for BSP board.
1231 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1233 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1234 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1235 them as unimplemented.
1237 1999-05-08 Felix Lee <flee@cygnus.com>
1239 * configure: Regenerated to track ../common/aclocal.m4 changes.
1241 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1243 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1245 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1247 * configure.in: Any mips64vr5*-*-* target should have
1248 -DTARGET_ENABLE_FR=1.
1249 (default_endian): Any mips64vr*el-*-* target should default to
1251 * configure: Re-generate.
1253 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1255 * mips.igen (ldl): Extend from _16_, not 32.
1257 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1259 * interp.c (sim_store_register): Force registers written to by GDB
1260 into an un-interpreted state.
1262 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1264 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1265 CPU, start periodic background I/O polls.
1266 (tx3904sio_poll): New function: periodic I/O poller.
1268 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1270 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1272 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1274 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1277 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1279 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1280 (load_word): Call SIM_CORE_SIGNAL hook on error.
1281 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1282 starting. For exception dispatching, pass PC instead of NULL_CIA.
1283 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1284 * sim-main.h (COP0_BADVADDR): Define.
1285 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1286 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1287 (_sim_cpu): Add exc_* fields to store register value snapshots.
1288 * mips.igen (*): Replace memory-related SignalException* calls
1289 with references to SIM_CORE_SIGNAL hook.
1291 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1293 * sim-main.c (*): Minor warning cleanups.
1295 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1297 * m16.igen (DADDIU5): Correct type-o.
1299 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1301 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1304 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1306 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1308 (interp.o): Add dependency on itable.h
1309 (oengine.c, gencode): Delete remaining references.
1310 (BUILT_SRC_FROM_GEN): Clean up.
1312 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1315 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1316 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1317 tmp-run-hack) : New.
1318 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1319 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1320 Drop the "64" qualifier to get the HACK generator working.
1321 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1322 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1323 qualifier to get the hack generator working.
1324 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1325 (DSLL): Use do_dsll.
1326 (DSLLV): Use do_dsllv.
1327 (DSRA): Use do_dsra.
1328 (DSRL): Use do_dsrl.
1329 (DSRLV): Use do_dsrlv.
1330 (BC1): Move *vr4100 to get the HACK generator working.
1331 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1332 get the HACK generator working.
1333 (MACC) Rename to get the HACK generator working.
1334 (DMACC,MACCS,DMACCS): Add the 64.
1336 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1338 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1339 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1341 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1343 * mips/interp.c (DEBUG): Cleanups.
1345 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1347 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1348 (tx3904sio_tickle): fflush after a stdout character output.
1350 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1352 * interp.c (sim_close): Uninstall modules.
1354 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1356 * sim-main.h, interp.c (sim_monitor): Change to global
1359 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1361 * configure.in (vr4100): Only include vr4100 instructions in
1363 * configure: Re-generate.
1364 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1366 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1368 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1369 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1372 * configure.in (sim_default_gen, sim_use_gen): Replace with
1374 (--enable-sim-igen): Delete config option. Always using IGEN.
1375 * configure: Re-generate.
1377 * Makefile.in (gencode): Kill, kill, kill.
1380 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1382 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1383 bit mips16 igen simulator.
1384 * configure: Re-generate.
1386 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1387 as part of vr4100 ISA.
1388 * vr.igen: Mark all instructions as 64 bit only.
1390 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1392 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1395 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1397 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1398 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1399 * configure: Re-generate.
1401 * m16.igen (BREAK): Define breakpoint instruction.
1402 (JALX32): Mark instruction as mips16 and not r3900.
1403 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1405 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1407 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1409 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1410 insn as a debug breakpoint.
1412 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1414 (PENDING_SCHED): Clean up trace statement.
1415 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1416 (PENDING_FILL): Delay write by only one cycle.
1417 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1419 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1421 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1423 (pending_tick): Move incrementing of index to FOR statement.
1424 (pending_tick): Only update PENDING_OUT after a write has occured.
1426 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1428 * configure: Re-generate.
1430 * interp.c (sim_engine_run OLD): Delete explicit call to
1431 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1433 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1435 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1436 interrupt level number to match changed SignalExceptionInterrupt
1439 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1441 * interp.c: #include "itable.h" if WITH_IGEN.
1442 (get_insn_name): New function.
1443 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1444 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1446 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1448 * configure: Rebuilt to inhale new common/aclocal.m4.
1450 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1452 * dv-tx3904sio.c: Include sim-assert.h.
1454 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1456 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1457 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1458 Reorganize target-specific sim-hardware checks.
1459 * configure: rebuilt.
1460 * interp.c (sim_open): For tx39 target boards, set
1461 OPERATING_ENVIRONMENT, add tx3904sio devices.
1462 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1463 ROM executables. Install dv-sockser into sim-modules list.
1465 * dv-tx3904irc.c: Compiler warning clean-up.
1466 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1467 frequent hw-trace messages.
1469 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1471 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1473 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1475 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1477 * vr.igen: New file.
1478 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1479 * mips.igen: Define vr4100 model. Include vr.igen.
1480 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1482 * mips.igen (check_mf_hilo): Correct check.
1484 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1486 * sim-main.h (interrupt_event): Add prototype.
1488 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1489 register_ptr, register_value.
1490 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1492 * sim-main.h (tracefh): Make extern.
1494 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1496 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1497 Reduce unnecessarily high timer event frequency.
1498 * dv-tx3904cpu.c: Ditto for interrupt event.
1500 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1502 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1504 (interrupt_event): Made non-static.
1506 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1507 interchange of configuration values for external vs. internal
1510 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1512 * mips.igen (BREAK): Moved code to here for
1513 simulator-reserved break instructions.
1514 * gencode.c (build_instruction): Ditto.
1515 * interp.c (signal_exception): Code moved from here. Non-
1516 reserved instructions now use exception vector, rather
1518 * sim-main.h: Moved magic constants to here.
1520 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1522 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1523 register upon non-zero interrupt event level, clear upon zero
1525 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1526 by passing zero event value.
1527 (*_io_{read,write}_buffer): Endianness fixes.
1528 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1529 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1531 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1532 serial I/O and timer module at base address 0xFFFF0000.
1534 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1536 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1539 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1541 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1543 * configure: Update.
1545 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1547 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1548 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1549 * configure.in: Include tx3904tmr in hw_device list.
1550 * configure: Rebuilt.
1551 * interp.c (sim_open): Instantiate three timer instances.
1552 Fix address typo of tx3904irc instance.
1554 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1556 * interp.c (signal_exception): SystemCall exception now uses
1557 the exception vector.
1559 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1561 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1564 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1566 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1568 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1570 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1572 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1573 sim-main.h. Declare a struct hw_descriptor instead of struct
1574 hw_device_descriptor.
1576 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1578 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1579 right bits and then re-align left hand bytes to correct byte
1580 lanes. Fix incorrect computation in do_store_left when loading
1581 bytes from second word.
1583 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1585 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1586 * interp.c (sim_open): Only create a device tree when HW is
1589 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1590 * interp.c (signal_exception): Ditto.
1592 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1594 * gencode.c: Mark BEGEZALL as LIKELY.
1596 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1598 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1599 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1601 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1603 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1604 modules. Recognize TX39 target with "mips*tx39" pattern.
1605 * configure: Rebuilt.
1606 * sim-main.h (*): Added many macros defining bits in
1607 TX39 control registers.
1608 (SignalInterrupt): Send actual PC instead of NULL.
1609 (SignalNMIReset): New exception type.
1610 * interp.c (board): New variable for future use to identify
1611 a particular board being simulated.
1612 (mips_option_handler,mips_options): Added "--board" option.
1613 (interrupt_event): Send actual PC.
1614 (sim_open): Make memory layout conditional on board setting.
1615 (signal_exception): Initial implementation of hardware interrupt
1616 handling. Accept another break instruction variant for simulator
1618 (decode_coproc): Implement RFE instruction for TX39.
1619 (mips.igen): Decode RFE instruction as such.
1620 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1621 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1622 bbegin to implement memory map.
1623 * dv-tx3904cpu.c: New file.
1624 * dv-tx3904irc.c: New file.
1626 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1628 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1630 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1632 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1633 with calls to check_div_hilo.
1635 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1637 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1638 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1639 Add special r3900 version of do_mult_hilo.
1640 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1641 with calls to check_mult_hilo.
1642 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1643 with calls to check_div_hilo.
1645 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1647 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1648 Document a replacement.
1650 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1652 * interp.c (sim_monitor): Make mon_printf work.
1654 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1656 * sim-main.h (INSN_NAME): New arg `cpu'.
1658 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1660 * configure: Regenerated to track ../common/aclocal.m4 changes.
1662 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1664 * configure: Regenerated to track ../common/aclocal.m4 changes.
1667 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1669 * acconfig.h: New file.
1670 * configure.in: Reverted change of Apr 24; use sinclude again.
1672 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1674 * configure: Regenerated to track ../common/aclocal.m4 changes.
1677 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1679 * configure.in: Don't call sinclude.
1681 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1683 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1685 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1687 * mips.igen (ERET): Implement.
1689 * interp.c (decode_coproc): Return sign-extended EPC.
1691 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1693 * interp.c (signal_exception): Do not ignore Trap.
1694 (signal_exception): On TRAP, restart at exception address.
1695 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1696 (signal_exception): Update.
1697 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1698 so that TRAP instructions are caught.
1700 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1702 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1703 contains HI/LO access history.
1704 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1705 (HIACCESS, LOACCESS): Delete, replace with
1706 (HIHISTORY, LOHISTORY): New macros.
1707 (CHECKHILO): Delete all, moved to mips.igen
1709 * gencode.c (build_instruction): Do not generate checks for
1710 correct HI/LO register usage.
1712 * interp.c (old_engine_run): Delete checks for correct HI/LO
1715 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1716 check_mf_cycles): New functions.
1717 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1718 do_divu, domultx, do_mult, do_multu): Use.
1720 * tx.igen ("madd", "maddu"): Use.
1722 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1724 * mips.igen (DSRAV): Use function do_dsrav.
1725 (SRAV): Use new function do_srav.
1727 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1728 (B): Sign extend 11 bit immediate.
1729 (EXT-B*): Shift 16 bit immediate left by 1.
1730 (ADDIU*): Don't sign extend immediate value.
1732 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1734 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1736 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1739 * mips.igen (delayslot32, nullify_next_insn): New functions.
1740 (m16.igen): Always include.
1741 (do_*): Add more tracing.
1743 * m16.igen (delayslot16): Add NIA argument, could be called by a
1744 32 bit MIPS16 instruction.
1746 * interp.c (ifetch16): Move function from here.
1747 * sim-main.c (ifetch16): To here.
1749 * sim-main.c (ifetch16, ifetch32): Update to match current
1750 implementations of LH, LW.
1751 (signal_exception): Don't print out incorrect hex value of illegal
1754 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1756 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1759 * m16.igen: Implement MIPS16 instructions.
1761 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1762 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1763 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1764 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1765 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1766 bodies of corresponding code from 32 bit insn to these. Also used
1767 by MIPS16 versions of functions.
1769 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1770 (IMEM16): Drop NR argument from macro.
1772 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1774 * Makefile.in (SIM_OBJS): Add sim-main.o.
1776 * sim-main.h (address_translation, load_memory, store_memory,
1777 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1779 (pr_addr, pr_uword64): Declare.
1780 (sim-main.c): Include when H_REVEALS_MODULE_P.
1782 * interp.c (address_translation, load_memory, store_memory,
1783 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1785 * sim-main.c: To here. Fix compilation problems.
1787 * configure.in: Enable inlining.
1788 * configure: Re-config.
1790 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1792 * configure: Regenerated to track ../common/aclocal.m4 changes.
1794 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1796 * mips.igen: Include tx.igen.
1797 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1798 * tx.igen: New file, contains MADD and MADDU.
1800 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1801 the hardwired constant `7'.
1802 (store_memory): Ditto.
1803 (LOADDRMASK): Move definition to sim-main.h.
1805 mips.igen (MTC0): Enable for r3900.
1808 mips.igen (do_load_byte): Delete.
1809 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1810 do_store_right): New functions.
1811 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1813 configure.in: Let the tx39 use igen again.
1816 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1818 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1819 not an address sized quantity. Return zero for cache sizes.
1821 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1823 * mips.igen (r3900): r3900 does not support 64 bit integer
1826 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1828 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1830 * configure : Rebuild.
1832 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1834 * configure: Regenerated to track ../common/aclocal.m4 changes.
1836 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1838 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1840 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1842 * configure: Regenerated to track ../common/aclocal.m4 changes.
1843 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1845 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1847 * configure: Regenerated to track ../common/aclocal.m4 changes.
1849 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1851 * interp.c (Max, Min): Comment out functions. Not yet used.
1853 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1855 * configure: Regenerated to track ../common/aclocal.m4 changes.
1857 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1859 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1860 configurable settings for stand-alone simulator.
1862 * configure.in: Added X11 search, just in case.
1864 * configure: Regenerated.
1866 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1868 * interp.c (sim_write, sim_read, load_memory, store_memory):
1869 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1871 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1873 * sim-main.h (GETFCC): Return an unsigned value.
1875 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1877 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1878 (DADD): Result destination is RD not RT.
1880 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1882 * sim-main.h (HIACCESS, LOACCESS): Always define.
1884 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1886 * interp.c (sim_info): Delete.
1888 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1890 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1891 (mips_option_handler): New argument `cpu'.
1892 (sim_open): Update call to sim_add_option_table.
1894 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1896 * mips.igen (CxC1): Add tracing.
1898 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1900 * sim-main.h (Max, Min): Declare.
1902 * interp.c (Max, Min): New functions.
1904 * mips.igen (BC1): Add tracing.
1906 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1908 * interp.c Added memory map for stack in vr4100
1910 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1912 * interp.c (load_memory): Add missing "break"'s.
1914 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1916 * interp.c (sim_store_register, sim_fetch_register): Pass in
1917 length parameter. Return -1.
1919 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1921 * interp.c: Added hardware init hook, fixed warnings.
1923 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1925 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1927 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1929 * interp.c (ifetch16): New function.
1931 * sim-main.h (IMEM32): Rename IMEM.
1932 (IMEM16_IMMED): Define.
1934 (DELAY_SLOT): Update.
1936 * m16run.c (sim_engine_run): New file.
1938 * m16.igen: All instructions except LB.
1939 (LB): Call do_load_byte.
1940 * mips.igen (do_load_byte): New function.
1941 (LB): Call do_load_byte.
1943 * mips.igen: Move spec for insn bit size and high bit from here.
1944 * Makefile.in (tmp-igen, tmp-m16): To here.
1946 * m16.dc: New file, decode mips16 instructions.
1948 * Makefile.in (SIM_NO_ALL): Define.
1949 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1951 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1953 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1954 point unit to 32 bit registers.
1955 * configure: Re-generate.
1957 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1959 * configure.in (sim_use_gen): Make IGEN the default simulator
1960 generator for generic 32 and 64 bit mips targets.
1961 * configure: Re-generate.
1963 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1965 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1968 * interp.c (sim_fetch_register, sim_store_register): Read/write
1969 FGR from correct location.
1970 (sim_open): Set size of FGR's according to
1971 WITH_TARGET_FLOATING_POINT_BITSIZE.
1973 * sim-main.h (FGR): Store floating point registers in a separate
1976 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1978 * configure: Regenerated to track ../common/aclocal.m4 changes.
1980 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1982 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1984 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1986 * interp.c (pending_tick): New function. Deliver pending writes.
1988 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1989 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1990 it can handle mixed sized quantites and single bits.
1992 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1994 * interp.c (oengine.h): Do not include when building with IGEN.
1995 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1996 (sim_info): Ditto for PROCESSOR_64BIT.
1997 (sim_monitor): Replace ut_reg with unsigned_word.
1998 (*): Ditto for t_reg.
1999 (LOADDRMASK): Define.
2000 (sim_open): Remove defunct check that host FP is IEEE compliant,
2001 using software to emulate floating point.
2002 (value_fpr, ...): Always compile, was conditional on HASFPU.
2004 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2006 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2009 * interp.c (SD, CPU): Define.
2010 (mips_option_handler): Set flags in each CPU.
2011 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2012 (sim_close): Do not clear STATE, deleted anyway.
2013 (sim_write, sim_read): Assume CPU zero's vm should be used for
2015 (sim_create_inferior): Set the PC for all processors.
2016 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2018 (mips16_entry): Pass correct nr of args to store_word, load_word.
2019 (ColdReset): Cold reset all cpu's.
2020 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2021 (sim_monitor, load_memory, store_memory, signal_exception): Use
2022 `CPU' instead of STATE_CPU.
2025 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2028 * sim-main.h (signal_exception): Add sim_cpu arg.
2029 (SignalException*): Pass both SD and CPU to signal_exception.
2030 * interp.c (signal_exception): Update.
2032 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2034 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2035 address_translation): Ditto
2036 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2038 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2040 * configure: Regenerated to track ../common/aclocal.m4 changes.
2042 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2044 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2046 * mips.igen (model): Map processor names onto BFD name.
2048 * sim-main.h (CPU_CIA): Delete.
2049 (SET_CIA, GET_CIA): Define
2051 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2053 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2056 * configure.in (default_endian): Configure a big-endian simulator
2058 * configure: Re-generate.
2060 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2062 * configure: Regenerated to track ../common/aclocal.m4 changes.
2064 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2066 * interp.c (sim_monitor): Handle Densan monitor outbyte
2067 and inbyte functions.
2069 1997-12-29 Felix Lee <flee@cygnus.com>
2071 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2073 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2075 * Makefile.in (tmp-igen): Arrange for $zero to always be
2076 reset to zero after every instruction.
2078 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2080 * configure: Regenerated to track ../common/aclocal.m4 changes.
2083 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2085 * mips.igen (MSUB): Fix to work like MADD.
2086 * gencode.c (MSUB): Similarly.
2088 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2090 * configure: Regenerated to track ../common/aclocal.m4 changes.
2092 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2094 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2096 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2098 * sim-main.h (sim-fpu.h): Include.
2100 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2101 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2102 using host independant sim_fpu module.
2104 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2106 * interp.c (signal_exception): Report internal errors with SIGABRT
2109 * sim-main.h (C0_CONFIG): New register.
2110 (signal.h): No longer include.
2112 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2114 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2116 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2118 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2120 * mips.igen: Tag vr5000 instructions.
2121 (ANDI): Was missing mipsIV model, fix assembler syntax.
2122 (do_c_cond_fmt): New function.
2123 (C.cond.fmt): Handle mips I-III which do not support CC field
2125 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2126 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2128 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2129 vr5000 which saves LO in a GPR separatly.
2131 * configure.in (enable-sim-igen): For vr5000, select vr5000
2132 specific instructions.
2133 * configure: Re-generate.
2135 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2137 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2139 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2140 fmt_uninterpreted_64 bit cases to switch. Convert to
2143 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2145 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2146 as specified in IV3.2 spec.
2147 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2149 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2151 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2152 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2153 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2154 PENDING_FILL versions of instructions. Simplify.
2156 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2158 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2160 (MTHI, MFHI): Disable code checking HI-LO.
2162 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2164 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2166 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2168 * gencode.c (build_mips16_operands): Replace IPC with cia.
2170 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2171 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2173 (UndefinedResult): Replace function with macro/function
2175 (sim_engine_run): Don't save PC in IPC.
2177 * sim-main.h (IPC): Delete.
2180 * interp.c (signal_exception, store_word, load_word,
2181 address_translation, load_memory, store_memory, cache_op,
2182 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2183 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2184 current instruction address - cia - argument.
2185 (sim_read, sim_write): Call address_translation directly.
2186 (sim_engine_run): Rename variable vaddr to cia.
2187 (signal_exception): Pass cia to sim_monitor
2189 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2190 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2191 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2193 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2194 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2197 * interp.c (signal_exception): Pass restart address to
2200 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2201 idecode.o): Add dependency.
2203 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2205 (DELAY_SLOT): Update NIA not PC with branch address.
2206 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2208 * mips.igen: Use CIA not PC in branch calculations.
2209 (illegal): Call SignalException.
2210 (BEQ, ADDIU): Fix assembler.
2212 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2214 * m16.igen (JALX): Was missing.
2216 * configure.in (enable-sim-igen): New configuration option.
2217 * configure: Re-generate.
2219 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2221 * interp.c (load_memory, store_memory): Delete parameter RAW.
2222 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2223 bypassing {load,store}_memory.
2225 * sim-main.h (ByteSwapMem): Delete definition.
2227 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2229 * interp.c (sim_do_command, sim_commands): Delete mips specific
2230 commands. Handled by module sim-options.
2232 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2233 (WITH_MODULO_MEMORY): Define.
2235 * interp.c (sim_info): Delete code printing memory size.
2237 * interp.c (mips_size): Nee sim_size, delete function.
2239 (monitor, monitor_base, monitor_size): Delete global variables.
2240 (sim_open, sim_close): Delete code creating monitor and other
2241 memory regions. Use sim-memopts module, via sim_do_commandf, to
2242 manage memory regions.
2243 (load_memory, store_memory): Use sim-core for memory model.
2245 * interp.c (address_translation): Delete all memory map code
2246 except line forcing 32 bit addresses.
2248 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2250 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2253 * interp.c (logfh, logfile): Delete globals.
2254 (sim_open, sim_close): Delete code opening & closing log file.
2255 (mips_option_handler): Delete -l and -n options.
2256 (OPTION mips_options): Ditto.
2258 * interp.c (OPTION mips_options): Rename option trace to dinero.
2259 (mips_option_handler): Update.
2261 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2263 * interp.c (fetch_str): New function.
2264 (sim_monitor): Rewrite using sim_read & sim_write.
2265 (sim_open): Check magic number.
2266 (sim_open): Write monitor vectors into memory using sim_write.
2267 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2268 (sim_read, sim_write): Simplify - transfer data one byte at a
2270 (load_memory, store_memory): Clarify meaning of parameter RAW.
2272 * sim-main.h (isHOST): Defete definition.
2273 (isTARGET): Mark as depreciated.
2274 (address_translation): Delete parameter HOST.
2276 * interp.c (address_translation): Delete parameter HOST.
2278 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2282 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2283 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2285 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2287 * mips.igen: Add model filter field to records.
2289 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2291 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2293 interp.c (sim_engine_run): Do not compile function sim_engine_run
2294 when WITH_IGEN == 1.
2296 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2297 target architecture.
2299 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2300 igen. Replace with configuration variables sim_igen_flags /
2303 * m16.igen: New file. Copy mips16 insns here.
2304 * mips.igen: From here.
2306 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2308 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2310 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2312 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2314 * gencode.c (build_instruction): Follow sim_write's lead in using
2315 BigEndianMem instead of !ByteSwapMem.
2317 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2319 * configure.in (sim_gen): Dependent on target, select type of
2320 generator. Always select old style generator.
2322 configure: Re-generate.
2324 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2326 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2327 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2328 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2329 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2330 SIM_@sim_gen@_*, set by autoconf.
2332 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2334 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2336 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2337 CURRENT_FLOATING_POINT instead.
2339 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2340 (address_translation): Raise exception InstructionFetch when
2341 translation fails and isINSTRUCTION.
2343 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2344 sim_engine_run): Change type of of vaddr and paddr to
2346 (address_translation, prefetch, load_memory, store_memory,
2347 cache_op): Change type of vAddr and pAddr to address_word.
2349 * gencode.c (build_instruction): Change type of vaddr and paddr to
2352 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2354 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2355 macro to obtain result of ALU op.
2357 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2359 * interp.c (sim_info): Call profile_print.
2361 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2363 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2365 * sim-main.h (WITH_PROFILE): Do not define, defined in
2366 common/sim-config.h. Use sim-profile module.
2367 (simPROFILE): Delete defintion.
2369 * interp.c (PROFILE): Delete definition.
2370 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2371 (sim_close): Delete code writing profile histogram.
2372 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2374 (sim_engine_run): Delete code profiling the PC.
2376 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2378 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2380 * interp.c (sim_monitor): Make register pointers of type
2383 * sim-main.h: Make registers of type unsigned_word not
2386 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2388 * interp.c (sync_operation): Rename from SyncOperation, make
2389 global, add SD argument.
2390 (prefetch): Rename from Prefetch, make global, add SD argument.
2391 (decode_coproc): Make global.
2393 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2395 * gencode.c (build_instruction): Generate DecodeCoproc not
2396 decode_coproc calls.
2398 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2399 (SizeFGR): Move to sim-main.h
2400 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2401 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2402 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2404 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2405 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2406 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2407 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2408 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2409 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2411 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2413 (sim-alu.h): Include.
2414 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2415 (sim_cia): Typedef to instruction_address.
2417 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2419 * Makefile.in (interp.o): Rename generated file engine.c to
2424 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2426 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2428 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2430 * gencode.c (build_instruction): For "FPSQRT", output correct
2431 number of arguments to Recip.
2433 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2435 * Makefile.in (interp.o): Depends on sim-main.h
2437 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2439 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2440 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2441 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2442 STATE, DSSTATE): Define
2443 (GPR, FGRIDX, ..): Define.
2445 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2446 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2447 (GPR, FGRIDX, ...): Delete macros.
2449 * interp.c: Update names to match defines from sim-main.h
2451 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2453 * interp.c (sim_monitor): Add SD argument.
2454 (sim_warning): Delete. Replace calls with calls to
2456 (sim_error): Delete. Replace calls with sim_io_error.
2457 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2458 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2459 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2461 (mips_size): Rename from sim_size. Add SD argument.
2463 * interp.c (simulator): Delete global variable.
2464 (callback): Delete global variable.
2465 (mips_option_handler, sim_open, sim_write, sim_read,
2466 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2467 sim_size,sim_monitor): Use sim_io_* not callback->*.
2468 (sim_open): ZALLOC simulator struct.
2469 (PROFILE): Do not define.
2471 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2473 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2474 support.h with corresponding code.
2476 * sim-main.h (word64, uword64), support.h: Move definition to
2478 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2481 * Makefile.in: Update dependencies
2482 * interp.c: Do not include.
2484 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2486 * interp.c (address_translation, load_memory, store_memory,
2487 cache_op): Rename to from AddressTranslation et.al., make global,
2490 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2493 * interp.c (SignalException): Rename to signal_exception, make
2496 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2498 * sim-main.h (SignalException, SignalExceptionInterrupt,
2499 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2500 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2501 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2504 * interp.c, support.h: Use.
2506 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2508 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2509 to value_fpr / store_fpr. Add SD argument.
2510 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2511 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2513 * sim-main.h (ValueFPR, StoreFPR): Define.
2515 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2517 * interp.c (sim_engine_run): Check consistency between configure
2518 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2521 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2522 (mips_fpu): Configure WITH_FLOATING_POINT.
2523 (mips_endian): Configure WITH_TARGET_ENDIAN.
2524 * configure: Update.
2526 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2528 * configure: Regenerated to track ../common/aclocal.m4 changes.
2530 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2532 * configure: Regenerated.
2534 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2536 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2538 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2540 * gencode.c (print_igen_insn_models): Assume certain architectures
2541 include all mips* instructions.
2542 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2545 * Makefile.in (tmp.igen): Add target. Generate igen input from
2548 * gencode.c (FEATURE_IGEN): Define.
2549 (main): Add --igen option. Generate output in igen format.
2550 (process_instructions): Format output according to igen option.
2551 (print_igen_insn_format): New function.
2552 (print_igen_insn_models): New function.
2553 (process_instructions): Only issue warnings and ignore
2554 instructions when no FEATURE_IGEN.
2556 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2558 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2561 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2563 * configure: Regenerated to track ../common/aclocal.m4 changes.
2565 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2567 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2568 SIM_RESERVED_BITS): Delete, moved to common.
2569 (SIM_EXTRA_CFLAGS): Update.
2571 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2573 * configure.in: Configure non-strict memory alignment.
2574 * configure: Regenerated to track ../common/aclocal.m4 changes.
2576 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2578 * configure: Regenerated to track ../common/aclocal.m4 changes.
2580 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2582 * gencode.c (SDBBP,DERET): Added (3900) insns.
2583 (RFE): Turn on for 3900.
2584 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2585 (dsstate): Made global.
2586 (SUBTARGET_R3900): Added.
2587 (CANCELDELAYSLOT): New.
2588 (SignalException): Ignore SystemCall rather than ignore and
2589 terminate. Add DebugBreakPoint handling.
2590 (decode_coproc): New insns RFE, DERET; and new registers Debug
2591 and DEPC protected by SUBTARGET_R3900.
2592 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2594 * Makefile.in,configure.in: Add mips subtarget option.
2595 * configure: Update.
2597 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2599 * gencode.c: Add r3900 (tx39).
2602 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2604 * gencode.c (build_instruction): Don't need to subtract 4 for
2607 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2609 * interp.c: Correct some HASFPU problems.
2611 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2613 * configure: Regenerated to track ../common/aclocal.m4 changes.
2615 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2617 * interp.c (mips_options): Fix samples option short form, should
2620 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2622 * interp.c (sim_info): Enable info code. Was just returning.
2624 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2626 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2629 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2631 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2633 (build_instruction): Ditto for LL.
2635 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2637 * configure: Regenerated to track ../common/aclocal.m4 changes.
2639 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2641 * configure: Regenerated to track ../common/aclocal.m4 changes.
2644 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2646 * interp.c (sim_open): Add call to sim_analyze_program, update
2649 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2651 * interp.c (sim_kill): Delete.
2652 (sim_create_inferior): Add ABFD argument. Set PC from same.
2653 (sim_load): Move code initializing trap handlers from here.
2654 (sim_open): To here.
2655 (sim_load): Delete, use sim-hload.c.
2657 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2659 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2661 * configure: Regenerated to track ../common/aclocal.m4 changes.
2664 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2666 * interp.c (sim_open): Add ABFD argument.
2667 (sim_load): Move call to sim_config from here.
2668 (sim_open): To here. Check return status.
2670 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2672 * gencode.c (build_instruction): Two arg MADD should
2673 not assign result to $0.
2675 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2677 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2678 * sim/mips/configure.in: Regenerate.
2680 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2682 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2683 signed8, unsigned8 et.al. types.
2685 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2686 hosts when selecting subreg.
2688 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2690 * interp.c (sim_engine_run): Reset the ZERO register to zero
2691 regardless of FEATURE_WARN_ZERO.
2692 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2694 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2696 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2697 (SignalException): For BreakPoints ignore any mode bits and just
2699 (SignalException): Always set the CAUSE register.
2701 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2703 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2704 exception has been taken.
2706 * interp.c: Implement the ERET and mt/f sr instructions.
2708 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2710 * interp.c (SignalException): Don't bother restarting an
2713 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2715 * interp.c (SignalException): Really take an interrupt.
2716 (interrupt_event): Only deliver interrupts when enabled.
2718 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2720 * interp.c (sim_info): Only print info when verbose.
2721 (sim_info) Use sim_io_printf for output.
2723 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2725 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2728 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2730 * interp.c (sim_do_command): Check for common commands if a
2731 simulator specific command fails.
2733 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2735 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2736 and simBE when DEBUG is defined.
2738 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2740 * interp.c (interrupt_event): New function. Pass exception event
2741 onto exception handler.
2743 * configure.in: Check for stdlib.h.
2744 * configure: Regenerate.
2746 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2747 variable declaration.
2748 (build_instruction): Initialize memval1.
2749 (build_instruction): Add UNUSED attribute to byte, bigend,
2751 (build_operands): Ditto.
2753 * interp.c: Fix GCC warnings.
2754 (sim_get_quit_code): Delete.
2756 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2757 * Makefile.in: Ditto.
2758 * configure: Re-generate.
2760 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2762 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2764 * interp.c (mips_option_handler): New function parse argumes using
2766 (myname): Replace with STATE_MY_NAME.
2767 (sim_open): Delete check for host endianness - performed by
2769 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2770 (sim_open): Move much of the initialization from here.
2771 (sim_load): To here. After the image has been loaded and
2773 (sim_open): Move ColdReset from here.
2774 (sim_create_inferior): To here.
2775 (sim_open): Make FP check less dependant on host endianness.
2777 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2779 * interp.c (sim_set_callbacks): Delete.
2781 * interp.c (membank, membank_base, membank_size): Replace with
2782 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2783 (sim_open): Remove call to callback->init. gdb/run do this.
2787 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2789 * interp.c (big_endian_p): Delete, replaced by
2790 current_target_byte_order.
2792 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2794 * interp.c (host_read_long, host_read_word, host_swap_word,
2795 host_swap_long): Delete. Using common sim-endian.
2796 (sim_fetch_register, sim_store_register): Use H2T.
2797 (pipeline_ticks): Delete. Handled by sim-events.
2799 (sim_engine_run): Update.
2801 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2803 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2805 (SignalException): To here. Signal using sim_engine_halt.
2806 (sim_stop_reason): Delete, moved to common.
2808 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2810 * interp.c (sim_open): Add callback argument.
2811 (sim_set_callbacks): Delete SIM_DESC argument.
2814 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2816 * Makefile.in (SIM_OBJS): Add common modules.
2818 * interp.c (sim_set_callbacks): Also set SD callback.
2819 (set_endianness, xfer_*, swap_*): Delete.
2820 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2821 Change to functions using sim-endian macros.
2822 (control_c, sim_stop): Delete, use common version.
2823 (simulate): Convert into.
2824 (sim_engine_run): This function.
2825 (sim_resume): Delete.
2827 * interp.c (simulation): New variable - the simulator object.
2828 (sim_kind): Delete global - merged into simulation.
2829 (sim_load): Cleanup. Move PC assignment from here.
2830 (sim_create_inferior): To here.
2832 * sim-main.h: New file.
2833 * interp.c (sim-main.h): Include.
2835 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2837 * configure: Regenerated to track ../common/aclocal.m4 changes.
2839 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2841 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2843 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2845 * gencode.c (build_instruction): DIV instructions: check
2846 for division by zero and integer overflow before using
2847 host's division operation.
2849 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2851 * Makefile.in (SIM_OBJS): Add sim-load.o.
2852 * interp.c: #include bfd.h.
2853 (target_byte_order): Delete.
2854 (sim_kind, myname, big_endian_p): New static locals.
2855 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2856 after argument parsing. Recognize -E arg, set endianness accordingly.
2857 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2858 load file into simulator. Set PC from bfd.
2859 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2860 (set_endianness): Use big_endian_p instead of target_byte_order.
2862 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2864 * interp.c (sim_size): Delete prototype - conflicts with
2865 definition in remote-sim.h. Correct definition.
2867 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2869 * configure: Regenerated to track ../common/aclocal.m4 changes.
2872 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2874 * interp.c (sim_open): New arg `kind'.
2876 * configure: Regenerated to track ../common/aclocal.m4 changes.
2878 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2880 * configure: Regenerated to track ../common/aclocal.m4 changes.
2882 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2884 * interp.c (sim_open): Set optind to 0 before calling getopt.
2886 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2888 * configure: Regenerated to track ../common/aclocal.m4 changes.
2890 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2892 * interp.c : Replace uses of pr_addr with pr_uword64
2893 where the bit length is always 64 independent of SIM_ADDR.
2894 (pr_uword64) : added.
2896 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2898 * configure: Re-generate.
2900 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2902 * configure: Regenerate to track ../common/aclocal.m4 changes.
2904 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2906 * interp.c (sim_open): New SIM_DESC result. Argument is now
2908 (other sim_*): New SIM_DESC argument.
2910 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2912 * interp.c: Fix printing of addresses for non-64-bit targets.
2913 (pr_addr): Add function to print address based on size.
2915 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2917 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2919 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2921 * gencode.c (build_mips16_operands): Correct computation of base
2922 address for extended PC relative instruction.
2924 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2926 * interp.c (mips16_entry): Add support for floating point cases.
2927 (SignalException): Pass floating point cases to mips16_entry.
2928 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2930 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2932 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2933 and then set the state to fmt_uninterpreted.
2934 (COP_SW): Temporarily set the state to fmt_word while calling
2937 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2939 * gencode.c (build_instruction): The high order may be set in the
2940 comparison flags at any ISA level, not just ISA 4.
2942 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2944 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2945 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2946 * configure.in: sinclude ../common/aclocal.m4.
2947 * configure: Regenerated.
2949 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2951 * configure: Rebuild after change to aclocal.m4.
2953 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2955 * configure configure.in Makefile.in: Update to new configure
2956 scheme which is more compatible with WinGDB builds.
2957 * configure.in: Improve comment on how to run autoconf.
2958 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2959 * Makefile.in: Use autoconf substitution to install common
2962 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2964 * gencode.c (build_instruction): Use BigEndianCPU instead of
2967 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2969 * interp.c (sim_monitor): Make output to stdout visible in
2970 wingdb's I/O log window.
2972 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2974 * support.h: Undo previous change to SIGTRAP
2977 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2979 * interp.c (store_word, load_word): New static functions.
2980 (mips16_entry): New static function.
2981 (SignalException): Look for mips16 entry and exit instructions.
2982 (simulate): Use the correct index when setting fpr_state after
2983 doing a pending move.
2985 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2987 * interp.c: Fix byte-swapping code throughout to work on
2988 both little- and big-endian hosts.
2990 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2992 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2993 with gdb/config/i386/xm-windows.h.
2995 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2997 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2998 that messes up arithmetic shifts.
3000 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3002 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3003 SIGTRAP and SIGQUIT for _WIN32.
3005 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3007 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3008 force a 64 bit multiplication.
3009 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3010 destination register is 0, since that is the default mips16 nop
3013 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3015 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3016 (build_endian_shift): Don't check proc64.
3017 (build_instruction): Always set memval to uword64. Cast op2 to
3018 uword64 when shifting it left in memory instructions. Always use
3019 the same code for stores--don't special case proc64.
3021 * gencode.c (build_mips16_operands): Fix base PC value for PC
3023 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3025 * interp.c (simJALDELAYSLOT): Define.
3026 (JALDELAYSLOT): Define.
3027 (INDELAYSLOT, INJALDELAYSLOT): Define.
3028 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3030 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3032 * interp.c (sim_open): add flush_cache as a PMON routine
3033 (sim_monitor): handle flush_cache by ignoring it
3035 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3037 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3039 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3040 (BigEndianMem): Rename to ByteSwapMem and change sense.
3041 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3042 BigEndianMem references to !ByteSwapMem.
3043 (set_endianness): New function, with prototype.
3044 (sim_open): Call set_endianness.
3045 (sim_info): Use simBE instead of BigEndianMem.
3046 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3047 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3048 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3049 ifdefs, keeping the prototype declaration.
3050 (swap_word): Rewrite correctly.
3051 (ColdReset): Delete references to CONFIG. Delete endianness related
3052 code; moved to set_endianness.
3054 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3056 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3057 * interp.c (CHECKHILO): Define away.
3058 (simSIGINT): New macro.
3059 (membank_size): Increase from 1MB to 2MB.
3060 (control_c): New function.
3061 (sim_resume): Rename parameter signal to signal_number. Add local
3062 variable prev. Call signal before and after simulate.
3063 (sim_stop_reason): Add simSIGINT support.
3064 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3066 (sim_warning): Delete call to SignalException. Do call printf_filtered
3068 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3069 a call to sim_warning.
3071 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3073 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3074 16 bit instructions.
3076 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3078 Add support for mips16 (16 bit MIPS implementation):
3079 * gencode.c (inst_type): Add mips16 instruction encoding types.
3080 (GETDATASIZEINSN): Define.
3081 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3082 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3084 (MIPS16_DECODE): New table, for mips16 instructions.
3085 (bitmap_val): New static function.
3086 (struct mips16_op): Define.
3087 (mips16_op_table): New table, for mips16 operands.
3088 (build_mips16_operands): New static function.
3089 (process_instructions): If PC is odd, decode a mips16
3090 instruction. Break out instruction handling into new
3091 build_instruction function.
3092 (build_instruction): New static function, broken out of
3093 process_instructions. Check modifiers rather than flags for SHIFT
3094 bit count and m[ft]{hi,lo} direction.
3095 (usage): Pass program name to fprintf.
3096 (main): Remove unused variable this_option_optind. Change
3097 ``*loptarg++'' to ``loptarg++''.
3098 (my_strtoul): Parenthesize && within ||.
3099 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3100 (simulate): If PC is odd, fetch a 16 bit instruction, and
3101 increment PC by 2 rather than 4.
3102 * configure.in: Add case for mips16*-*-*.
3103 * configure: Rebuild.
3105 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3107 * interp.c: Allow -t to enable tracing in standalone simulator.
3108 Fix garbage output in trace file and error messages.
3110 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3112 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3113 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3114 * configure.in: Simplify using macros in ../common/aclocal.m4.
3115 * configure: Regenerated.
3116 * tconfig.in: New file.
3118 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3120 * interp.c: Fix bugs in 64-bit port.
3121 Use ansi function declarations for msvc compiler.
3122 Initialize and test file pointer in trace code.
3123 Prevent duplicate definition of LAST_EMED_REGNUM.
3125 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3127 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3129 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3131 * interp.c (SignalException): Check for explicit terminating
3133 * gencode.c: Pass instruction value through SignalException()
3134 calls for Trap, Breakpoint and Syscall.
3136 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3138 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3139 only used on those hosts that provide it.
3140 * configure.in: Add sqrt() to list of functions to be checked for.
3141 * config.in: Re-generated.
3142 * configure: Re-generated.
3144 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3146 * gencode.c (process_instructions): Call build_endian_shift when
3147 expanding STORE RIGHT, to fix swr.
3148 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3149 clear the high bits.
3150 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3151 Fix float to int conversions to produce signed values.
3153 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3155 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3156 (process_instructions): Correct handling of nor instruction.
3157 Correct shift count for 32 bit shift instructions. Correct sign
3158 extension for arithmetic shifts to not shift the number of bits in
3159 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3160 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3162 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3163 It's OK to have a mult follow a mult. What's not OK is to have a
3164 mult follow an mfhi.
3165 (Convert): Comment out incorrect rounding code.
3167 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3169 * interp.c (sim_monitor): Improved monitor printf
3170 simulation. Tidied up simulator warnings, and added "--log" option
3171 for directing warning message output.
3172 * gencode.c: Use sim_warning() rather than WARNING macro.
3174 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3176 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3177 getopt1.o, rather than on gencode.c. Link objects together.
3178 Don't link against -liberty.
3179 (gencode.o, getopt.o, getopt1.o): New targets.
3180 * gencode.c: Include <ctype.h> and "ansidecl.h".
3181 (AND): Undefine after including "ansidecl.h".
3182 (ULONG_MAX): Define if not defined.
3183 (OP_*): Don't define macros; now defined in opcode/mips.h.
3184 (main): Call my_strtoul rather than strtoul.
3185 (my_strtoul): New static function.
3187 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3189 * gencode.c (process_instructions): Generate word64 and uword64
3190 instead of `long long' and `unsigned long long' data types.
3191 * interp.c: #include sysdep.h to get signals, and define default
3193 * (Convert): Work around for Visual-C++ compiler bug with type
3195 * support.h: Make things compile under Visual-C++ by using
3196 __int64 instead of `long long'. Change many refs to long long
3197 into word64/uword64 typedefs.
3199 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3201 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3202 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3204 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3205 (AC_PROG_INSTALL): Added.
3206 (AC_PROG_CC): Moved to before configure.host call.
3207 * configure: Rebuilt.
3209 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3211 * configure.in: Define @SIMCONF@ depending on mips target.
3212 * configure: Rebuild.
3213 * Makefile.in (run): Add @SIMCONF@ to control simulator
3215 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3216 * interp.c: Remove some debugging, provide more detailed error
3217 messages, update memory accesses to use LOADDRMASK.
3219 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3221 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3222 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3224 * configure: Rebuild.
3225 * config.in: New file, generated by autoheader.
3226 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3227 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3228 HAVE_ANINT and HAVE_AINT, as appropriate.
3229 * Makefile.in (run): Use @LIBS@ rather than -lm.
3230 (interp.o): Depend upon config.h.
3231 (Makefile): Just rebuild Makefile.
3232 (clean): Remove stamp-h.
3233 (mostlyclean): Make the same as clean, not as distclean.
3234 (config.h, stamp-h): New targets.
3236 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3238 * interp.c (ColdReset): Fix boolean test. Make all simulator
3241 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3243 * interp.c (xfer_direct_word, xfer_direct_long,
3244 swap_direct_word, swap_direct_long, xfer_big_word,
3245 xfer_big_long, xfer_little_word, xfer_little_long,
3246 swap_word,swap_long): Added.
3247 * interp.c (ColdReset): Provide function indirection to
3248 host<->simulated_target transfer routines.
3249 * interp.c (sim_store_register, sim_fetch_register): Updated to
3250 make use of indirected transfer routines.
3252 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3254 * gencode.c (process_instructions): Ensure FP ABS instruction
3256 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3257 system call support.
3259 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3261 * interp.c (sim_do_command): Complain if callback structure not
3264 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3266 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3267 support for Sun hosts.
3268 * Makefile.in (gencode): Ensure the host compiler and libraries
3269 used for cross-hosted build.
3271 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3273 * interp.c, gencode.c: Some more (TODO) tidying.
3275 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3277 * gencode.c, interp.c: Replaced explicit long long references with
3278 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3279 * support.h (SET64LO, SET64HI): Macros added.
3281 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3283 * configure: Regenerate with autoconf 2.7.
3285 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3287 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3288 * support.h: Remove superfluous "1" from #if.
3289 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3291 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3293 * interp.c (StoreFPR): Control UndefinedResult() call on
3294 WARN_RESULT manifest.
3296 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3298 * gencode.c: Tidied instruction decoding, and added FP instruction
3301 * interp.c: Added dineroIII, and BSD profiling support. Also
3302 run-time FP handling.
3304 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3306 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3307 gencode.c, interp.c, support.h: created.