1 2013-05-10 Freddie Chopin <freddie_chopin@op.pl>
5 2013-03-26 Mike Frysinger <vapier@gentoo.org>
7 * configure: Regenerate.
9 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
11 * configure.ac: Address use of dv-sockser.o.
12 * tconfig.in: Conditionalize use of dv_sockser_install.
13 * configure: Regenerated.
14 * config.in: Regenerated.
16 2012-10-04 Chao-ying Fu <fu@mips.com>
17 Steve Ellcey <sellcey@mips.com>
19 * mips/mips3264r2.igen (rdhwr): New.
21 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
23 * configure.ac: Always link against dv-sockser.o.
24 * configure: Regenerate.
26 2012-06-15 Joel Brobecker <brobecker@adacore.com>
28 * config.in, configure: Regenerate.
30 2012-05-18 Nick Clifton <nickc@redhat.com>
33 * interp.c: Include config.h before system header files.
35 2012-03-24 Mike Frysinger <vapier@gentoo.org>
37 * aclocal.m4, config.in, configure: Regenerate.
39 2011-12-03 Mike Frysinger <vapier@gentoo.org>
41 * aclocal.m4: New file.
42 * configure: Regenerate.
44 2011-10-19 Mike Frysinger <vapier@gentoo.org>
46 * configure: Regenerate after common/acinclude.m4 update.
48 2011-10-17 Mike Frysinger <vapier@gentoo.org>
50 * configure.ac: Change include to common/acinclude.m4.
52 2011-10-17 Mike Frysinger <vapier@gentoo.org>
54 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
55 call. Replace common.m4 include with SIM_AC_COMMON.
56 * configure: Regenerate.
58 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
60 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
62 (tmp-mach-multi): Exit early when igen fails.
64 2011-07-05 Mike Frysinger <vapier@gentoo.org>
66 * interp.c (sim_do_command): Delete.
68 2011-02-14 Mike Frysinger <vapier@gentoo.org>
70 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
71 (tx3904sio_fifo_reset): Likewise.
72 * interp.c (sim_monitor): Likewise.
74 2010-04-14 Mike Frysinger <vapier@gentoo.org>
76 * interp.c (sim_write): Add const to buffer arg.
78 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
80 * interp.c: Don't include sysdep.h
82 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
84 * configure: Regenerate.
86 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
88 * config.in: Regenerate.
89 * configure: Likewise.
91 * configure: Regenerate.
93 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
95 * configure: Regenerate to track ../common/common.m4 changes.
98 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
99 Daniel Jacobowitz <dan@codesourcery.com>
100 Joseph Myers <joseph@codesourcery.com>
102 * configure: Regenerate.
104 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
106 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
107 that unconditionally allows fmt_ps.
108 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
109 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
110 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
111 filter from 64,f to 32,f.
112 (PREFX): Change filter from 64 to 32.
113 (LDXC1, LUXC1): Provide separate mips32r2 implementations
114 that use do_load_double instead of do_load. Make both LUXC1
115 versions unpredictable if SizeFGR () != 64.
116 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
117 instead of do_store. Remove unused variable. Make both SUXC1
118 versions unpredictable if SizeFGR () != 64.
120 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
122 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
123 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
124 shifts for that case.
126 2007-09-04 Nick Clifton <nickc@redhat.com>
128 * interp.c (options enum): Add OPTION_INFO_MEMORY.
129 (display_mem_info): New static variable.
130 (mips_option_handler): Handle OPTION_INFO_MEMORY.
131 (mips_options): Add info-memory and memory-info.
132 (sim_open): After processing the command line and board
133 specification, check display_mem_info. If it is set then
134 call the real handler for the --memory-info command line
137 2007-08-24 Joel Brobecker <brobecker@adacore.com>
139 * configure.ac: Change license of multi-run.c to GPL version 3.
140 * configure: Regenerate.
142 2007-06-28 Richard Sandiford <richard@codesourcery.com>
144 * configure.ac, configure: Revert last patch.
146 2007-06-26 Richard Sandiford <richard@codesourcery.com>
148 * configure.ac (sim_mipsisa3264_configs): New variable.
149 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
150 every configuration support all four targets, using the triplet to
151 determine the default.
152 * configure: Regenerate.
154 2007-06-25 Richard Sandiford <richard@codesourcery.com>
156 * Makefile.in (m16run.o): New rule.
158 2007-05-15 Thiemo Seufer <ths@mips.com>
160 * mips3264r2.igen (DSHD): Fix compile warning.
162 2007-05-14 Thiemo Seufer <ths@mips.com>
164 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
165 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
166 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
167 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
170 2007-03-01 Thiemo Seufer <ths@mips.com>
172 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
175 2007-02-20 Thiemo Seufer <ths@mips.com>
177 * dsp.igen: Update copyright notice.
178 * dsp2.igen: Fix copyright notice.
180 2007-02-20 Thiemo Seufer <ths@mips.com>
181 Chao-Ying Fu <fu@mips.com>
183 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
184 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
185 Add dsp2 to sim_igen_machine.
186 * configure: Regenerate.
187 * dsp.igen (do_ph_op): Add MUL support when op = 2.
188 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
189 (mulq_rs.ph): Use do_ph_mulq.
190 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
191 * mips.igen: Add dsp2 model and include dsp2.igen.
192 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
193 for *mips32r2, *mips64r2, *dsp.
194 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
195 for *mips32r2, *mips64r2, *dsp2.
196 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
198 2007-02-19 Thiemo Seufer <ths@mips.com>
199 Nigel Stephens <nigel@mips.com>
201 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
202 jumps with hazard barrier.
204 2007-02-19 Thiemo Seufer <ths@mips.com>
205 Nigel Stephens <nigel@mips.com>
207 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
208 after each call to sim_io_write.
210 2007-02-19 Thiemo Seufer <ths@mips.com>
211 Nigel Stephens <nigel@mips.com>
213 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
214 supported by this simulator.
215 (decode_coproc): Recognise additional CP0 Config registers
218 2007-02-19 Thiemo Seufer <ths@mips.com>
219 Nigel Stephens <nigel@mips.com>
220 David Ung <davidu@mips.com>
222 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
223 uninterpreted formats. If fmt is one of the uninterpreted types
224 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
225 fmt_word, and fmt_uninterpreted_64 like fmt_long.
226 (store_fpr): When writing an invalid odd register, set the
227 matching even register to fmt_unknown, not the following register.
228 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
229 the the memory window at offset 0 set by --memory-size command
231 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
233 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
235 (sim_monitor): When returning the memory size to the MIPS
236 application, use the value in STATE_MEM_SIZE, not an arbitrary
238 (cop_lw): Don' mess around with FPR_STATE, just pass
239 fmt_uninterpreted_32 to StoreFPR.
241 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
243 * mips.igen (not_word_value): Single version for mips32, mips64
246 2007-02-19 Thiemo Seufer <ths@mips.com>
247 Nigel Stephens <nigel@mips.com>
249 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
252 2007-02-17 Thiemo Seufer <ths@mips.com>
254 * configure.ac (mips*-sde-elf*): Move in front of generic machine
256 * configure: Regenerate.
258 2007-02-17 Thiemo Seufer <ths@mips.com>
260 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
261 Add mdmx to sim_igen_machine.
262 (mipsisa64*-*-*): Likewise. Remove dsp.
263 (mipsisa32*-*-*): Remove dsp.
264 * configure: Regenerate.
266 2007-02-13 Thiemo Seufer <ths@mips.com>
268 * configure.ac: Add mips*-sde-elf* target.
269 * configure: Regenerate.
271 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
273 * acconfig.h: Remove.
274 * config.in, configure: Regenerate.
276 2006-11-07 Thiemo Seufer <ths@mips.com>
278 * dsp.igen (do_w_op): Fix compiler warning.
280 2006-08-29 Thiemo Seufer <ths@mips.com>
281 David Ung <davidu@mips.com>
283 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
285 * configure: Regenerate.
286 * mips.igen (model): Add smartmips.
287 (MADDU): Increment ACX if carry.
288 (do_mult): Clear ACX.
289 (ROR,RORV): Add smartmips.
290 (include): Include smartmips.igen.
291 * sim-main.h (ACX): Set to REGISTERS[89].
292 * smartmips.igen: New file.
294 2006-08-29 Thiemo Seufer <ths@mips.com>
295 David Ung <davidu@mips.com>
297 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
298 mips3264r2.igen. Add missing dependency rules.
299 * m16e.igen: Support for mips16e save/restore instructions.
301 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
303 * configure: Regenerated.
305 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
307 * configure: Regenerated.
309 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
311 * configure: Regenerated.
313 2006-05-15 Chao-ying Fu <fu@mips.com>
315 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
317 2006-04-18 Nick Clifton <nickc@redhat.com>
319 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
322 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
324 * configure: Regenerate.
326 2005-12-14 Chao-ying Fu <fu@mips.com>
328 * Makefile.in (SIM_OBJS): Add dsp.o.
329 (dsp.o): New dependency.
330 (IGEN_INCLUDE): Add dsp.igen.
331 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
332 mipsisa64*-*-*): Add dsp to sim_igen_machine.
333 * configure: Regenerate.
334 * mips.igen: Add dsp model and include dsp.igen.
335 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
336 because these instructions are extended in DSP ASE.
337 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
338 adding 6 DSP accumulator registers and 1 DSP control register.
339 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
340 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
341 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
342 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
343 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
344 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
345 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
346 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
347 DSPCR_CCOND_SMASK): New define.
348 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
349 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
351 2005-07-08 Ian Lance Taylor <ian@airs.com>
353 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
355 2005-06-16 David Ung <davidu@mips.com>
356 Nigel Stephens <nigel@mips.com>
358 * mips.igen: New mips16e model and include m16e.igen.
359 (check_u64): Add mips16e tag.
360 * m16e.igen: New file for MIPS16e instructions.
361 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
362 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
364 * configure: Regenerate.
366 2005-05-26 David Ung <davidu@mips.com>
368 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
369 tags to all instructions which are applicable to the new ISAs.
370 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
372 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
374 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
376 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
377 * configure: Regenerate.
379 2005-03-23 Mark Kettenis <kettenis@gnu.org>
381 * configure: Regenerate.
383 2005-01-14 Andrew Cagney <cagney@gnu.org>
385 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
386 explicit call to AC_CONFIG_HEADER.
387 * configure: Regenerate.
389 2005-01-12 Andrew Cagney <cagney@gnu.org>
391 * configure.ac: Update to use ../common/common.m4.
392 * configure: Re-generate.
394 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
396 * configure: Regenerated to track ../common/aclocal.m4 changes.
398 2005-01-07 Andrew Cagney <cagney@gnu.org>
400 * configure.ac: Rename configure.in, require autoconf 2.59.
401 * configure: Re-generate.
403 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
405 * configure: Regenerate for ../common/aclocal.m4 update.
407 2004-09-24 Monika Chaddha <monika@acmet.com>
409 Committed by Andrew Cagney.
410 * m16.igen (CMP, CMPI): Fix assembler.
412 2004-08-18 Chris Demetriou <cgd@broadcom.com>
414 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
415 * configure: Regenerate.
417 2004-06-25 Chris Demetriou <cgd@broadcom.com>
419 * configure.in (sim_m16_machine): Include mipsIII.
420 * configure: Regenerate.
422 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
424 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
426 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
428 2004-04-10 Chris Demetriou <cgd@broadcom.com>
430 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
432 2004-04-09 Chris Demetriou <cgd@broadcom.com>
434 * mips.igen (check_fmt): Remove.
435 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
436 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
437 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
438 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
439 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
440 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
441 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
442 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
443 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
444 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
446 2004-04-09 Chris Demetriou <cgd@broadcom.com>
448 * sb1.igen (check_sbx): New function.
449 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
451 2004-03-29 Chris Demetriou <cgd@broadcom.com>
452 Richard Sandiford <rsandifo@redhat.com>
454 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
455 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
456 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
457 separate implementations for mipsIV and mipsV. Use new macros to
458 determine whether the restrictions apply.
460 2004-01-19 Chris Demetriou <cgd@broadcom.com>
462 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
463 (check_mult_hilo): Improve comments.
464 (check_div_hilo): Likewise. Also, fork off a new version
465 to handle mips32/mips64 (since there are no hazards to check
468 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
470 * mips.igen (do_dmultx): Fix check for negative operands.
472 2003-05-16 Ian Lance Taylor <ian@airs.com>
474 * Makefile.in (SHELL): Make sure this is defined.
475 (various): Use $(SHELL) whenever we invoke move-if-change.
477 2003-05-03 Chris Demetriou <cgd@broadcom.com>
479 * cp1.c: Tweak attribution slightly.
482 * mdmx.igen: Likewise.
483 * mips3d.igen: Likewise.
484 * sb1.igen: Likewise.
486 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
488 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
491 2003-02-27 Andrew Cagney <cagney@redhat.com>
493 * interp.c (sim_open): Rename _bfd to bfd.
494 (sim_create_inferior): Ditto.
496 2003-01-14 Chris Demetriou <cgd@broadcom.com>
498 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
500 2003-01-14 Chris Demetriou <cgd@broadcom.com>
502 * mips.igen (EI, DI): Remove.
504 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
506 * Makefile.in (tmp-run-multi): Fix mips16 filter.
508 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
509 Andrew Cagney <ac131313@redhat.com>
510 Gavin Romig-Koch <gavin@redhat.com>
511 Graydon Hoare <graydon@redhat.com>
512 Aldy Hernandez <aldyh@redhat.com>
513 Dave Brolley <brolley@redhat.com>
514 Chris Demetriou <cgd@broadcom.com>
516 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
517 (sim_mach_default): New variable.
518 (mips64vr-*-*, mips64vrel-*-*): New configurations.
519 Add a new simulator generator, MULTI.
520 * configure: Regenerate.
521 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
522 (multi-run.o): New dependency.
523 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
524 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
525 (tmp-multi): Combine them.
526 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
527 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
528 (distclean-extra): New rule.
529 * sim-main.h: Include bfd.h.
530 (MIPS_MACH): New macro.
531 * mips.igen (vr4120, vr5400, vr5500): New models.
532 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
533 * vr.igen: Replace with new version.
535 2003-01-04 Chris Demetriou <cgd@broadcom.com>
537 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
538 * configure: Regenerate.
540 2002-12-31 Chris Demetriou <cgd@broadcom.com>
542 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
543 * mips.igen: Remove all invocations of check_branch_bug and
546 2002-12-16 Chris Demetriou <cgd@broadcom.com>
548 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
550 2002-07-30 Chris Demetriou <cgd@broadcom.com>
552 * mips.igen (do_load_double, do_store_double): New functions.
553 (LDC1, SDC1): Rename to...
554 (LDC1b, SDC1b): respectively.
555 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
557 2002-07-29 Michael Snyder <msnyder@redhat.com>
559 * cp1.c (fp_recip2): Modify initialization expression so that
560 GCC will recognize it as constant.
562 2002-06-18 Chris Demetriou <cgd@broadcom.com>
564 * mdmx.c (SD_): Delete.
565 (Unpredictable): Re-define, for now, to directly invoke
566 unpredictable_action().
567 (mdmx_acc_op): Fix error in .ob immediate handling.
569 2002-06-18 Andrew Cagney <cagney@redhat.com>
571 * interp.c (sim_firmware_command): Initialize `address'.
573 2002-06-16 Andrew Cagney <ac131313@redhat.com>
575 * configure: Regenerated to track ../common/aclocal.m4 changes.
577 2002-06-14 Chris Demetriou <cgd@broadcom.com>
578 Ed Satterthwaite <ehs@broadcom.com>
580 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
581 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
582 * mips.igen: Include mips3d.igen.
583 (mips3d): New model name for MIPS-3D ASE instructions.
584 (CVT.W.fmt): Don't use this instruction for word (source) format
586 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
587 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
588 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
589 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
590 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
591 (RSquareRoot1, RSquareRoot2): New macros.
592 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
593 (fp_rsqrt2): New functions.
594 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
595 * configure: Regenerate.
597 2002-06-13 Chris Demetriou <cgd@broadcom.com>
598 Ed Satterthwaite <ehs@broadcom.com>
600 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
601 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
602 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
603 (convert): Note that this function is not used for paired-single
605 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
606 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
607 (check_fmt_p): Enable paired-single support.
608 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
609 (PUU.PS): New instructions.
610 (CVT.S.fmt): Don't use this instruction for paired-single format
612 * sim-main.h (FP_formats): New value 'fmt_ps.'
613 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
614 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
616 2002-06-12 Chris Demetriou <cgd@broadcom.com>
618 * mips.igen: Fix formatting of function calls in
621 2002-06-12 Chris Demetriou <cgd@broadcom.com>
623 * mips.igen (MOVN, MOVZ): Trace result.
624 (TNEI): Print "tnei" as the opcode name in traces.
625 (CEIL.W): Add disassembly string for traces.
626 (RSQRT.fmt): Make location of disassembly string consistent
627 with other instructions.
629 2002-06-12 Chris Demetriou <cgd@broadcom.com>
631 * mips.igen (X): Delete unused function.
633 2002-06-08 Andrew Cagney <cagney@redhat.com>
635 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
637 2002-06-07 Chris Demetriou <cgd@broadcom.com>
638 Ed Satterthwaite <ehs@broadcom.com>
640 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
641 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
642 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
643 (fp_nmsub): New prototypes.
644 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
645 (NegMultiplySub): New defines.
646 * mips.igen (RSQRT.fmt): Use RSquareRoot().
647 (MADD.D, MADD.S): Replace with...
648 (MADD.fmt): New instruction.
649 (MSUB.D, MSUB.S): Replace with...
650 (MSUB.fmt): New instruction.
651 (NMADD.D, NMADD.S): Replace with...
652 (NMADD.fmt): New instruction.
653 (NMSUB.D, MSUB.S): Replace with...
654 (NMSUB.fmt): New instruction.
656 2002-06-07 Chris Demetriou <cgd@broadcom.com>
657 Ed Satterthwaite <ehs@broadcom.com>
659 * cp1.c: Fix more comment spelling and formatting.
660 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
661 (denorm_mode): New function.
662 (fpu_unary, fpu_binary): Round results after operation, collect
663 status from rounding operations, and update the FCSR.
664 (convert): Collect status from integer conversions and rounding
665 operations, and update the FCSR. Adjust NaN values that result
666 from conversions. Convert to use sim_io_eprintf rather than
667 fprintf, and remove some debugging code.
668 * cp1.h (fenr_FS): New define.
670 2002-06-07 Chris Demetriou <cgd@broadcom.com>
672 * cp1.c (convert): Remove unusable debugging code, and move MIPS
673 rounding mode to sim FP rounding mode flag conversion code into...
674 (rounding_mode): New function.
676 2002-06-07 Chris Demetriou <cgd@broadcom.com>
678 * cp1.c: Clean up formatting of a few comments.
679 (value_fpr): Reformat switch statement.
681 2002-06-06 Chris Demetriou <cgd@broadcom.com>
682 Ed Satterthwaite <ehs@broadcom.com>
685 * sim-main.h: Include cp1.h.
686 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
687 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
688 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
689 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
690 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
691 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
692 * cp1.c: Don't include sim-fpu.h; already included by
693 sim-main.h. Clean up formatting of some comments.
694 (NaN, Equal, Less): Remove.
695 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
696 (fp_cmp): New functions.
697 * mips.igen (do_c_cond_fmt): Remove.
698 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
699 Compare. Add result tracing.
700 (CxC1): Remove, replace with...
701 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
702 (DMxC1): Remove, replace with...
703 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
704 (MxC1): Remove, replace with...
705 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
707 2002-06-04 Chris Demetriou <cgd@broadcom.com>
709 * sim-main.h (FGRIDX): Remove, replace all uses with...
710 (FGR_BASE): New macro.
711 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
712 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
713 (NR_FGR, FGR): Likewise.
714 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
715 * mips.igen: Likewise.
717 2002-06-04 Chris Demetriou <cgd@broadcom.com>
719 * cp1.c: Add an FSF Copyright notice to this file.
721 2002-06-04 Chris Demetriou <cgd@broadcom.com>
722 Ed Satterthwaite <ehs@broadcom.com>
724 * cp1.c (Infinity): Remove.
725 * sim-main.h (Infinity): Likewise.
727 * cp1.c (fp_unary, fp_binary): New functions.
728 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
729 (fp_sqrt): New functions, implemented in terms of the above.
730 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
731 (Recip, SquareRoot): Remove (replaced by functions above).
732 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
733 (fp_recip, fp_sqrt): New prototypes.
734 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
735 (Recip, SquareRoot): Replace prototypes with #defines which
736 invoke the functions above.
738 2002-06-03 Chris Demetriou <cgd@broadcom.com>
740 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
741 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
742 file, remove PARAMS from prototypes.
743 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
744 simulator state arguments.
745 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
746 pass simulator state arguments.
747 * cp1.c (SD): Redefine as CPU_STATE(cpu).
748 (store_fpr, convert): Remove 'sd' argument.
749 (value_fpr): Likewise. Convert to use 'SD' instead.
751 2002-06-03 Chris Demetriou <cgd@broadcom.com>
753 * cp1.c (Min, Max): Remove #if 0'd functions.
754 * sim-main.h (Min, Max): Remove.
756 2002-06-03 Chris Demetriou <cgd@broadcom.com>
758 * cp1.c: fix formatting of switch case and default labels.
759 * interp.c: Likewise.
760 * sim-main.c: Likewise.
762 2002-06-03 Chris Demetriou <cgd@broadcom.com>
764 * cp1.c: Clean up comments which describe FP formats.
765 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
767 2002-06-03 Chris Demetriou <cgd@broadcom.com>
768 Ed Satterthwaite <ehs@broadcom.com>
770 * configure.in (mipsisa64sb1*-*-*): New target for supporting
771 Broadcom SiByte SB-1 processor configurations.
772 * configure: Regenerate.
773 * sb1.igen: New file.
774 * mips.igen: Include sb1.igen.
776 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
777 * mdmx.igen: Add "sb1" model to all appropriate functions and
779 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
780 (ob_func, ob_acc): Reference the above.
781 (qh_acc): Adjust to keep the same size as ob_acc.
782 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
783 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
785 2002-06-03 Chris Demetriou <cgd@broadcom.com>
787 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
789 2002-06-02 Chris Demetriou <cgd@broadcom.com>
790 Ed Satterthwaite <ehs@broadcom.com>
792 * mips.igen (mdmx): New (pseudo-)model.
793 * mdmx.c, mdmx.igen: New files.
794 * Makefile.in (SIM_OBJS): Add mdmx.o.
795 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
797 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
798 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
799 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
800 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
801 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
802 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
803 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
804 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
805 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
806 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
807 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
808 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
809 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
810 (qh_fmtsel): New macros.
811 (_sim_cpu): New member "acc".
812 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
813 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
815 2002-05-01 Chris Demetriou <cgd@broadcom.com>
817 * interp.c: Use 'deprecated' rather than 'depreciated.'
818 * sim-main.h: Likewise.
820 2002-05-01 Chris Demetriou <cgd@broadcom.com>
822 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
823 which wouldn't compile anyway.
824 * sim-main.h (unpredictable_action): New function prototype.
825 (Unpredictable): Define to call igen function unpredictable().
826 (NotWordValue): New macro to call igen function not_word_value().
827 (UndefinedResult): Remove.
828 * interp.c (undefined_result): Remove.
829 (unpredictable_action): New function.
830 * mips.igen (not_word_value, unpredictable): New functions.
831 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
832 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
833 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
834 NotWordValue() to check for unpredictable inputs, then
835 Unpredictable() to handle them.
837 2002-02-24 Chris Demetriou <cgd@broadcom.com>
839 * mips.igen: Fix formatting of calls to Unpredictable().
841 2002-04-20 Andrew Cagney <ac131313@redhat.com>
843 * interp.c (sim_open): Revert previous change.
845 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
847 * interp.c (sim_open): Disable chunk of code that wrote code in
848 vector table entries.
850 2002-03-19 Chris Demetriou <cgd@broadcom.com>
852 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
853 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
856 2002-03-19 Chris Demetriou <cgd@broadcom.com>
858 * cp1.c: Fix many formatting issues.
860 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
862 * cp1.c (fpu_format_name): New function to replace...
863 (DOFMT): This. Delete, and update all callers.
864 (fpu_rounding_mode_name): New function to replace...
865 (RMMODE): This. Delete, and update all callers.
867 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
869 * interp.c: Move FPU support routines from here to...
870 * cp1.c: Here. New file.
871 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
874 2002-03-12 Chris Demetriou <cgd@broadcom.com>
876 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
877 * mips.igen (mips32, mips64): New models, add to all instructions
878 and functions as appropriate.
879 (loadstore_ea, check_u64): New variant for model mips64.
880 (check_fmt_p): New variant for models mipsV and mips64, remove
881 mipsV model marking fro other variant.
884 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
885 for mips32 and mips64.
886 (DCLO, DCLZ): New instructions for mips64.
888 2002-03-07 Chris Demetriou <cgd@broadcom.com>
890 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
891 immediate or code as a hex value with the "%#lx" format.
892 (ANDI): Likewise, and fix printed instruction name.
894 2002-03-05 Chris Demetriou <cgd@broadcom.com>
896 * sim-main.h (UndefinedResult, Unpredictable): New macros
897 which currently do nothing.
899 2002-03-05 Chris Demetriou <cgd@broadcom.com>
901 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
902 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
903 (status_CU3): New definitions.
905 * sim-main.h (ExceptionCause): Add new values for MIPS32
906 and MIPS64: MDMX, MCheck, CacheErr. Update comments
907 for DebugBreakPoint and NMIReset to note their status in
909 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
910 (SignalExceptionCacheErr): New exception macros.
912 2002-03-05 Chris Demetriou <cgd@broadcom.com>
914 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
915 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
917 (SignalExceptionCoProcessorUnusable): Take as argument the
918 unusable coprocessor number.
920 2002-03-05 Chris Demetriou <cgd@broadcom.com>
922 * mips.igen: Fix formatting of all SignalException calls.
924 2002-03-05 Chris Demetriou <cgd@broadcom.com>
926 * sim-main.h (SIGNEXTEND): Remove.
928 2002-03-04 Chris Demetriou <cgd@broadcom.com>
930 * mips.igen: Remove gencode comment from top of file, fix
931 spelling in another comment.
933 2002-03-04 Chris Demetriou <cgd@broadcom.com>
935 * mips.igen (check_fmt, check_fmt_p): New functions to check
936 whether specific floating point formats are usable.
937 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
938 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
939 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
940 Use the new functions.
941 (do_c_cond_fmt): Remove format checks...
942 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
944 2002-03-03 Chris Demetriou <cgd@broadcom.com>
946 * mips.igen: Fix formatting of check_fpu calls.
948 2002-03-03 Chris Demetriou <cgd@broadcom.com>
950 * mips.igen (FLOOR.L.fmt): Store correct destination register.
952 2002-03-03 Chris Demetriou <cgd@broadcom.com>
954 * mips.igen: Remove whitespace at end of lines.
956 2002-03-02 Chris Demetriou <cgd@broadcom.com>
958 * mips.igen (loadstore_ea): New function to do effective
959 address calculations.
960 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
961 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
962 CACHE): Use loadstore_ea to do effective address computations.
964 2002-03-02 Chris Demetriou <cgd@broadcom.com>
966 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
967 * mips.igen (LL, CxC1, MxC1): Likewise.
969 2002-03-02 Chris Demetriou <cgd@broadcom.com>
971 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
972 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
973 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
974 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
975 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
976 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
977 Don't split opcode fields by hand, use the opcode field values
980 2002-03-01 Chris Demetriou <cgd@broadcom.com>
982 * mips.igen (do_divu): Fix spacing.
984 * mips.igen (do_dsllv): Move to be right before DSLLV,
985 to match the rest of the do_<shift> functions.
987 2002-03-01 Chris Demetriou <cgd@broadcom.com>
989 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
990 DSRL32, do_dsrlv): Trace inputs and results.
992 2002-03-01 Chris Demetriou <cgd@broadcom.com>
994 * mips.igen (CACHE): Provide instruction-printing string.
996 * interp.c (signal_exception): Comment tokens after #endif.
998 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1000 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1001 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1002 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1003 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1004 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1005 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1006 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1007 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1009 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1011 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1012 instruction-printing string.
1013 (LWU): Use '64' as the filter flag.
1015 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1017 * mips.igen (SDXC1): Fix instruction-printing string.
1019 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1021 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1022 filter flags "32,f".
1024 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1026 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1029 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1031 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1032 add a comma) so that it more closely match the MIPS ISA
1033 documentation opcode partitioning.
1034 (PREF): Put useful names on opcode fields, and include
1035 instruction-printing string.
1037 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1039 * mips.igen (check_u64): New function which in the future will
1040 check whether 64-bit instructions are usable and signal an
1041 exception if not. Currently a no-op.
1042 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1043 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1044 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1045 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1047 * mips.igen (check_fpu): New function which in the future will
1048 check whether FPU instructions are usable and signal an exception
1049 if not. Currently a no-op.
1050 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1051 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1052 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1053 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1054 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1055 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1056 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1057 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1059 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1061 * mips.igen (do_load_left, do_load_right): Move to be immediately
1063 (do_store_left, do_store_right): Move to be immediately following
1066 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1068 * mips.igen (mipsV): New model name. Also, add it to
1069 all instructions and functions where it is appropriate.
1071 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1073 * mips.igen: For all functions and instructions, list model
1074 names that support that instruction one per line.
1076 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1078 * mips.igen: Add some additional comments about supported
1079 models, and about which instructions go where.
1080 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1081 order as is used in the rest of the file.
1083 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1085 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1086 indicating that ALU32_END or ALU64_END are there to check
1088 (DADD): Likewise, but also remove previous comment about
1091 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1093 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1094 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1095 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1096 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1097 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1098 fields (i.e., add and move commas) so that they more closely
1099 match the MIPS ISA documentation opcode partitioning.
1101 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1103 * mips.igen (ADDI): Print immediate value.
1104 (BREAK): Print code.
1105 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1106 (SLL): Print "nop" specially, and don't run the code
1107 that does the shift for the "nop" case.
1109 2001-11-17 Fred Fish <fnf@redhat.com>
1111 * sim-main.h (float_operation): Move enum declaration outside
1112 of _sim_cpu struct declaration.
1114 2001-04-12 Jim Blandy <jimb@redhat.com>
1116 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1117 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1119 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1120 PENDING_FILL, and you can get the intended effect gracefully by
1121 calling PENDING_SCHED directly.
1123 2001-02-23 Ben Elliston <bje@redhat.com>
1125 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1126 already defined elsewhere.
1128 2001-02-19 Ben Elliston <bje@redhat.com>
1130 * sim-main.h (sim_monitor): Return an int.
1131 * interp.c (sim_monitor): Add return values.
1132 (signal_exception): Handle error conditions from sim_monitor.
1134 2001-02-08 Ben Elliston <bje@redhat.com>
1136 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1137 (store_memory): Likewise, pass cia to sim_core_write*.
1139 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1141 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1142 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1144 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1146 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1147 * Makefile.in: Don't delete *.igen when cleaning directory.
1149 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1151 * m16.igen (break): Call SignalException not sim_engine_halt.
1153 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1155 From Jason Eckhardt:
1156 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1158 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1160 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1162 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1164 * mips.igen (do_dmultx): Fix typo.
1166 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1168 * configure: Regenerated to track ../common/aclocal.m4 changes.
1170 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1172 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1174 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1176 * sim-main.h (GPR_CLEAR): Define macro.
1178 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1180 * interp.c (decode_coproc): Output long using %lx and not %s.
1182 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1184 * interp.c (sim_open): Sort & extend dummy memory regions for
1185 --board=jmr3904 for eCos.
1187 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1189 * configure: Regenerated.
1191 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1193 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1194 calls, conditional on the simulator being in verbose mode.
1196 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1198 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1199 cache don't get ReservedInstruction traps.
1201 1999-11-29 Mark Salter <msalter@cygnus.com>
1203 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1204 to clear status bits in sdisr register. This is how the hardware works.
1206 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1207 being used by cygmon.
1209 1999-11-11 Andrew Haley <aph@cygnus.com>
1211 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1214 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1216 * mips.igen (MULT): Correct previous mis-applied patch.
1218 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1220 * mips.igen (delayslot32): Handle sequence like
1221 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1222 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1223 (MULT): Actually pass the third register...
1225 1999-09-03 Mark Salter <msalter@cygnus.com>
1227 * interp.c (sim_open): Added more memory aliases for additional
1228 hardware being touched by cygmon on jmr3904 board.
1230 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1232 * configure: Regenerated to track ../common/aclocal.m4 changes.
1234 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1236 * interp.c (sim_store_register): Handle case where client - GDB -
1237 specifies that a 4 byte register is 8 bytes in size.
1238 (sim_fetch_register): Ditto.
1240 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1242 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1243 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1244 (idt_monitor_base): Base address for IDT monitor traps.
1245 (pmon_monitor_base): Ditto for PMON.
1246 (lsipmon_monitor_base): Ditto for LSI PMON.
1247 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1248 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1249 (sim_firmware_command): New function.
1250 (mips_option_handler): Call it for OPTION_FIRMWARE.
1251 (sim_open): Allocate memory for idt_monitor region. If "--board"
1252 option was given, add no monitor by default. Add BREAK hooks only if
1253 monitors are also there.
1255 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1257 * interp.c (sim_monitor): Flush output before reading input.
1259 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1261 * tconfig.in (SIM_HANDLES_LMA): Always define.
1263 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1265 From Mark Salter <msalter@cygnus.com>:
1266 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1267 (sim_open): Add setup for BSP board.
1269 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1271 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1272 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1273 them as unimplemented.
1275 1999-05-08 Felix Lee <flee@cygnus.com>
1277 * configure: Regenerated to track ../common/aclocal.m4 changes.
1279 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1281 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1283 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1285 * configure.in: Any mips64vr5*-*-* target should have
1286 -DTARGET_ENABLE_FR=1.
1287 (default_endian): Any mips64vr*el-*-* target should default to
1289 * configure: Re-generate.
1291 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1293 * mips.igen (ldl): Extend from _16_, not 32.
1295 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1297 * interp.c (sim_store_register): Force registers written to by GDB
1298 into an un-interpreted state.
1300 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1302 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1303 CPU, start periodic background I/O polls.
1304 (tx3904sio_poll): New function: periodic I/O poller.
1306 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1308 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1310 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1312 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1315 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1317 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1318 (load_word): Call SIM_CORE_SIGNAL hook on error.
1319 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1320 starting. For exception dispatching, pass PC instead of NULL_CIA.
1321 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1322 * sim-main.h (COP0_BADVADDR): Define.
1323 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1324 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1325 (_sim_cpu): Add exc_* fields to store register value snapshots.
1326 * mips.igen (*): Replace memory-related SignalException* calls
1327 with references to SIM_CORE_SIGNAL hook.
1329 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1331 * sim-main.c (*): Minor warning cleanups.
1333 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1335 * m16.igen (DADDIU5): Correct type-o.
1337 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1339 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1342 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1344 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1346 (interp.o): Add dependency on itable.h
1347 (oengine.c, gencode): Delete remaining references.
1348 (BUILT_SRC_FROM_GEN): Clean up.
1350 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1353 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1354 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1355 tmp-run-hack) : New.
1356 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1357 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1358 Drop the "64" qualifier to get the HACK generator working.
1359 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1360 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1361 qualifier to get the hack generator working.
1362 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1363 (DSLL): Use do_dsll.
1364 (DSLLV): Use do_dsllv.
1365 (DSRA): Use do_dsra.
1366 (DSRL): Use do_dsrl.
1367 (DSRLV): Use do_dsrlv.
1368 (BC1): Move *vr4100 to get the HACK generator working.
1369 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1370 get the HACK generator working.
1371 (MACC) Rename to get the HACK generator working.
1372 (DMACC,MACCS,DMACCS): Add the 64.
1374 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1376 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1377 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1379 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1381 * mips/interp.c (DEBUG): Cleanups.
1383 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1385 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1386 (tx3904sio_tickle): fflush after a stdout character output.
1388 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1390 * interp.c (sim_close): Uninstall modules.
1392 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1394 * sim-main.h, interp.c (sim_monitor): Change to global
1397 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1399 * configure.in (vr4100): Only include vr4100 instructions in
1401 * configure: Re-generate.
1402 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1404 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1406 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1407 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1410 * configure.in (sim_default_gen, sim_use_gen): Replace with
1412 (--enable-sim-igen): Delete config option. Always using IGEN.
1413 * configure: Re-generate.
1415 * Makefile.in (gencode): Kill, kill, kill.
1418 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1420 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1421 bit mips16 igen simulator.
1422 * configure: Re-generate.
1424 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1425 as part of vr4100 ISA.
1426 * vr.igen: Mark all instructions as 64 bit only.
1428 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1430 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1433 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1435 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1436 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1437 * configure: Re-generate.
1439 * m16.igen (BREAK): Define breakpoint instruction.
1440 (JALX32): Mark instruction as mips16 and not r3900.
1441 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1443 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1445 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1447 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1448 insn as a debug breakpoint.
1450 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1452 (PENDING_SCHED): Clean up trace statement.
1453 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1454 (PENDING_FILL): Delay write by only one cycle.
1455 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1457 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1459 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1461 (pending_tick): Move incrementing of index to FOR statement.
1462 (pending_tick): Only update PENDING_OUT after a write has occured.
1464 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1466 * configure: Re-generate.
1468 * interp.c (sim_engine_run OLD): Delete explicit call to
1469 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1471 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1473 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1474 interrupt level number to match changed SignalExceptionInterrupt
1477 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1479 * interp.c: #include "itable.h" if WITH_IGEN.
1480 (get_insn_name): New function.
1481 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1482 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1484 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1486 * configure: Rebuilt to inhale new common/aclocal.m4.
1488 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1490 * dv-tx3904sio.c: Include sim-assert.h.
1492 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1494 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1495 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1496 Reorganize target-specific sim-hardware checks.
1497 * configure: rebuilt.
1498 * interp.c (sim_open): For tx39 target boards, set
1499 OPERATING_ENVIRONMENT, add tx3904sio devices.
1500 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1501 ROM executables. Install dv-sockser into sim-modules list.
1503 * dv-tx3904irc.c: Compiler warning clean-up.
1504 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1505 frequent hw-trace messages.
1507 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1509 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1511 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1513 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1515 * vr.igen: New file.
1516 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1517 * mips.igen: Define vr4100 model. Include vr.igen.
1518 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1520 * mips.igen (check_mf_hilo): Correct check.
1522 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1524 * sim-main.h (interrupt_event): Add prototype.
1526 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1527 register_ptr, register_value.
1528 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1530 * sim-main.h (tracefh): Make extern.
1532 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1534 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1535 Reduce unnecessarily high timer event frequency.
1536 * dv-tx3904cpu.c: Ditto for interrupt event.
1538 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1540 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1542 (interrupt_event): Made non-static.
1544 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1545 interchange of configuration values for external vs. internal
1548 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1550 * mips.igen (BREAK): Moved code to here for
1551 simulator-reserved break instructions.
1552 * gencode.c (build_instruction): Ditto.
1553 * interp.c (signal_exception): Code moved from here. Non-
1554 reserved instructions now use exception vector, rather
1556 * sim-main.h: Moved magic constants to here.
1558 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1560 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1561 register upon non-zero interrupt event level, clear upon zero
1563 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1564 by passing zero event value.
1565 (*_io_{read,write}_buffer): Endianness fixes.
1566 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1567 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1569 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1570 serial I/O and timer module at base address 0xFFFF0000.
1572 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1574 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1577 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1579 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1581 * configure: Update.
1583 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1585 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1586 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1587 * configure.in: Include tx3904tmr in hw_device list.
1588 * configure: Rebuilt.
1589 * interp.c (sim_open): Instantiate three timer instances.
1590 Fix address typo of tx3904irc instance.
1592 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1594 * interp.c (signal_exception): SystemCall exception now uses
1595 the exception vector.
1597 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1599 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1602 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1604 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1606 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1608 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1610 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1611 sim-main.h. Declare a struct hw_descriptor instead of struct
1612 hw_device_descriptor.
1614 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1616 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1617 right bits and then re-align left hand bytes to correct byte
1618 lanes. Fix incorrect computation in do_store_left when loading
1619 bytes from second word.
1621 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1623 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1624 * interp.c (sim_open): Only create a device tree when HW is
1627 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1628 * interp.c (signal_exception): Ditto.
1630 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1632 * gencode.c: Mark BEGEZALL as LIKELY.
1634 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1636 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1637 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1639 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1641 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1642 modules. Recognize TX39 target with "mips*tx39" pattern.
1643 * configure: Rebuilt.
1644 * sim-main.h (*): Added many macros defining bits in
1645 TX39 control registers.
1646 (SignalInterrupt): Send actual PC instead of NULL.
1647 (SignalNMIReset): New exception type.
1648 * interp.c (board): New variable for future use to identify
1649 a particular board being simulated.
1650 (mips_option_handler,mips_options): Added "--board" option.
1651 (interrupt_event): Send actual PC.
1652 (sim_open): Make memory layout conditional on board setting.
1653 (signal_exception): Initial implementation of hardware interrupt
1654 handling. Accept another break instruction variant for simulator
1656 (decode_coproc): Implement RFE instruction for TX39.
1657 (mips.igen): Decode RFE instruction as such.
1658 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1659 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1660 bbegin to implement memory map.
1661 * dv-tx3904cpu.c: New file.
1662 * dv-tx3904irc.c: New file.
1664 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1666 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1668 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1670 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1671 with calls to check_div_hilo.
1673 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1675 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1676 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1677 Add special r3900 version of do_mult_hilo.
1678 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1679 with calls to check_mult_hilo.
1680 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1681 with calls to check_div_hilo.
1683 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1685 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1686 Document a replacement.
1688 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1690 * interp.c (sim_monitor): Make mon_printf work.
1692 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1694 * sim-main.h (INSN_NAME): New arg `cpu'.
1696 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1698 * configure: Regenerated to track ../common/aclocal.m4 changes.
1700 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1702 * configure: Regenerated to track ../common/aclocal.m4 changes.
1705 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1707 * acconfig.h: New file.
1708 * configure.in: Reverted change of Apr 24; use sinclude again.
1710 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1712 * configure: Regenerated to track ../common/aclocal.m4 changes.
1715 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1717 * configure.in: Don't call sinclude.
1719 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1721 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1723 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1725 * mips.igen (ERET): Implement.
1727 * interp.c (decode_coproc): Return sign-extended EPC.
1729 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1731 * interp.c (signal_exception): Do not ignore Trap.
1732 (signal_exception): On TRAP, restart at exception address.
1733 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1734 (signal_exception): Update.
1735 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1736 so that TRAP instructions are caught.
1738 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1740 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1741 contains HI/LO access history.
1742 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1743 (HIACCESS, LOACCESS): Delete, replace with
1744 (HIHISTORY, LOHISTORY): New macros.
1745 (CHECKHILO): Delete all, moved to mips.igen
1747 * gencode.c (build_instruction): Do not generate checks for
1748 correct HI/LO register usage.
1750 * interp.c (old_engine_run): Delete checks for correct HI/LO
1753 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1754 check_mf_cycles): New functions.
1755 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1756 do_divu, domultx, do_mult, do_multu): Use.
1758 * tx.igen ("madd", "maddu"): Use.
1760 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1762 * mips.igen (DSRAV): Use function do_dsrav.
1763 (SRAV): Use new function do_srav.
1765 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1766 (B): Sign extend 11 bit immediate.
1767 (EXT-B*): Shift 16 bit immediate left by 1.
1768 (ADDIU*): Don't sign extend immediate value.
1770 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1772 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1774 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1777 * mips.igen (delayslot32, nullify_next_insn): New functions.
1778 (m16.igen): Always include.
1779 (do_*): Add more tracing.
1781 * m16.igen (delayslot16): Add NIA argument, could be called by a
1782 32 bit MIPS16 instruction.
1784 * interp.c (ifetch16): Move function from here.
1785 * sim-main.c (ifetch16): To here.
1787 * sim-main.c (ifetch16, ifetch32): Update to match current
1788 implementations of LH, LW.
1789 (signal_exception): Don't print out incorrect hex value of illegal
1792 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1794 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1797 * m16.igen: Implement MIPS16 instructions.
1799 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1800 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1801 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1802 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1803 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1804 bodies of corresponding code from 32 bit insn to these. Also used
1805 by MIPS16 versions of functions.
1807 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1808 (IMEM16): Drop NR argument from macro.
1810 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1812 * Makefile.in (SIM_OBJS): Add sim-main.o.
1814 * sim-main.h (address_translation, load_memory, store_memory,
1815 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1817 (pr_addr, pr_uword64): Declare.
1818 (sim-main.c): Include when H_REVEALS_MODULE_P.
1820 * interp.c (address_translation, load_memory, store_memory,
1821 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1823 * sim-main.c: To here. Fix compilation problems.
1825 * configure.in: Enable inlining.
1826 * configure: Re-config.
1828 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1830 * configure: Regenerated to track ../common/aclocal.m4 changes.
1832 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1834 * mips.igen: Include tx.igen.
1835 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1836 * tx.igen: New file, contains MADD and MADDU.
1838 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1839 the hardwired constant `7'.
1840 (store_memory): Ditto.
1841 (LOADDRMASK): Move definition to sim-main.h.
1843 mips.igen (MTC0): Enable for r3900.
1846 mips.igen (do_load_byte): Delete.
1847 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1848 do_store_right): New functions.
1849 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1851 configure.in: Let the tx39 use igen again.
1854 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1856 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1857 not an address sized quantity. Return zero for cache sizes.
1859 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1861 * mips.igen (r3900): r3900 does not support 64 bit integer
1864 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1866 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1868 * configure : Rebuild.
1870 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1872 * configure: Regenerated to track ../common/aclocal.m4 changes.
1874 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1876 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1878 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1880 * configure: Regenerated to track ../common/aclocal.m4 changes.
1881 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1883 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1885 * configure: Regenerated to track ../common/aclocal.m4 changes.
1887 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1889 * interp.c (Max, Min): Comment out functions. Not yet used.
1891 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1893 * configure: Regenerated to track ../common/aclocal.m4 changes.
1895 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1897 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1898 configurable settings for stand-alone simulator.
1900 * configure.in: Added X11 search, just in case.
1902 * configure: Regenerated.
1904 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1906 * interp.c (sim_write, sim_read, load_memory, store_memory):
1907 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1909 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1911 * sim-main.h (GETFCC): Return an unsigned value.
1913 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1915 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1916 (DADD): Result destination is RD not RT.
1918 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1920 * sim-main.h (HIACCESS, LOACCESS): Always define.
1922 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1924 * interp.c (sim_info): Delete.
1926 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1928 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1929 (mips_option_handler): New argument `cpu'.
1930 (sim_open): Update call to sim_add_option_table.
1932 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1934 * mips.igen (CxC1): Add tracing.
1936 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1938 * sim-main.h (Max, Min): Declare.
1940 * interp.c (Max, Min): New functions.
1942 * mips.igen (BC1): Add tracing.
1944 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1946 * interp.c Added memory map for stack in vr4100
1948 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1950 * interp.c (load_memory): Add missing "break"'s.
1952 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1954 * interp.c (sim_store_register, sim_fetch_register): Pass in
1955 length parameter. Return -1.
1957 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1959 * interp.c: Added hardware init hook, fixed warnings.
1961 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1963 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1965 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1967 * interp.c (ifetch16): New function.
1969 * sim-main.h (IMEM32): Rename IMEM.
1970 (IMEM16_IMMED): Define.
1972 (DELAY_SLOT): Update.
1974 * m16run.c (sim_engine_run): New file.
1976 * m16.igen: All instructions except LB.
1977 (LB): Call do_load_byte.
1978 * mips.igen (do_load_byte): New function.
1979 (LB): Call do_load_byte.
1981 * mips.igen: Move spec for insn bit size and high bit from here.
1982 * Makefile.in (tmp-igen, tmp-m16): To here.
1984 * m16.dc: New file, decode mips16 instructions.
1986 * Makefile.in (SIM_NO_ALL): Define.
1987 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1989 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1991 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1992 point unit to 32 bit registers.
1993 * configure: Re-generate.
1995 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1997 * configure.in (sim_use_gen): Make IGEN the default simulator
1998 generator for generic 32 and 64 bit mips targets.
1999 * configure: Re-generate.
2001 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2003 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2006 * interp.c (sim_fetch_register, sim_store_register): Read/write
2007 FGR from correct location.
2008 (sim_open): Set size of FGR's according to
2009 WITH_TARGET_FLOATING_POINT_BITSIZE.
2011 * sim-main.h (FGR): Store floating point registers in a separate
2014 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2016 * configure: Regenerated to track ../common/aclocal.m4 changes.
2018 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2020 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2022 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2024 * interp.c (pending_tick): New function. Deliver pending writes.
2026 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2027 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2028 it can handle mixed sized quantites and single bits.
2030 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2032 * interp.c (oengine.h): Do not include when building with IGEN.
2033 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2034 (sim_info): Ditto for PROCESSOR_64BIT.
2035 (sim_monitor): Replace ut_reg with unsigned_word.
2036 (*): Ditto for t_reg.
2037 (LOADDRMASK): Define.
2038 (sim_open): Remove defunct check that host FP is IEEE compliant,
2039 using software to emulate floating point.
2040 (value_fpr, ...): Always compile, was conditional on HASFPU.
2042 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2044 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2047 * interp.c (SD, CPU): Define.
2048 (mips_option_handler): Set flags in each CPU.
2049 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2050 (sim_close): Do not clear STATE, deleted anyway.
2051 (sim_write, sim_read): Assume CPU zero's vm should be used for
2053 (sim_create_inferior): Set the PC for all processors.
2054 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2056 (mips16_entry): Pass correct nr of args to store_word, load_word.
2057 (ColdReset): Cold reset all cpu's.
2058 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2059 (sim_monitor, load_memory, store_memory, signal_exception): Use
2060 `CPU' instead of STATE_CPU.
2063 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2066 * sim-main.h (signal_exception): Add sim_cpu arg.
2067 (SignalException*): Pass both SD and CPU to signal_exception.
2068 * interp.c (signal_exception): Update.
2070 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2072 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2073 address_translation): Ditto
2074 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2076 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2078 * configure: Regenerated to track ../common/aclocal.m4 changes.
2080 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2082 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2084 * mips.igen (model): Map processor names onto BFD name.
2086 * sim-main.h (CPU_CIA): Delete.
2087 (SET_CIA, GET_CIA): Define
2089 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2091 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2094 * configure.in (default_endian): Configure a big-endian simulator
2096 * configure: Re-generate.
2098 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2100 * configure: Regenerated to track ../common/aclocal.m4 changes.
2102 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2104 * interp.c (sim_monitor): Handle Densan monitor outbyte
2105 and inbyte functions.
2107 1997-12-29 Felix Lee <flee@cygnus.com>
2109 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2111 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2113 * Makefile.in (tmp-igen): Arrange for $zero to always be
2114 reset to zero after every instruction.
2116 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2118 * configure: Regenerated to track ../common/aclocal.m4 changes.
2121 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2123 * mips.igen (MSUB): Fix to work like MADD.
2124 * gencode.c (MSUB): Similarly.
2126 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2128 * configure: Regenerated to track ../common/aclocal.m4 changes.
2130 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2132 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2134 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2136 * sim-main.h (sim-fpu.h): Include.
2138 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2139 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2140 using host independant sim_fpu module.
2142 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2144 * interp.c (signal_exception): Report internal errors with SIGABRT
2147 * sim-main.h (C0_CONFIG): New register.
2148 (signal.h): No longer include.
2150 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2152 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2154 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2156 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2158 * mips.igen: Tag vr5000 instructions.
2159 (ANDI): Was missing mipsIV model, fix assembler syntax.
2160 (do_c_cond_fmt): New function.
2161 (C.cond.fmt): Handle mips I-III which do not support CC field
2163 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2164 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2166 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2167 vr5000 which saves LO in a GPR separatly.
2169 * configure.in (enable-sim-igen): For vr5000, select vr5000
2170 specific instructions.
2171 * configure: Re-generate.
2173 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2175 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2177 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2178 fmt_uninterpreted_64 bit cases to switch. Convert to
2181 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2183 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2184 as specified in IV3.2 spec.
2185 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2187 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2189 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2190 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2191 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2192 PENDING_FILL versions of instructions. Simplify.
2194 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2196 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2198 (MTHI, MFHI): Disable code checking HI-LO.
2200 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2202 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2204 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2206 * gencode.c (build_mips16_operands): Replace IPC with cia.
2208 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2209 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2211 (UndefinedResult): Replace function with macro/function
2213 (sim_engine_run): Don't save PC in IPC.
2215 * sim-main.h (IPC): Delete.
2218 * interp.c (signal_exception, store_word, load_word,
2219 address_translation, load_memory, store_memory, cache_op,
2220 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2221 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2222 current instruction address - cia - argument.
2223 (sim_read, sim_write): Call address_translation directly.
2224 (sim_engine_run): Rename variable vaddr to cia.
2225 (signal_exception): Pass cia to sim_monitor
2227 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2228 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2229 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2231 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2232 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2235 * interp.c (signal_exception): Pass restart address to
2238 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2239 idecode.o): Add dependency.
2241 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2243 (DELAY_SLOT): Update NIA not PC with branch address.
2244 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2246 * mips.igen: Use CIA not PC in branch calculations.
2247 (illegal): Call SignalException.
2248 (BEQ, ADDIU): Fix assembler.
2250 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2252 * m16.igen (JALX): Was missing.
2254 * configure.in (enable-sim-igen): New configuration option.
2255 * configure: Re-generate.
2257 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2259 * interp.c (load_memory, store_memory): Delete parameter RAW.
2260 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2261 bypassing {load,store}_memory.
2263 * sim-main.h (ByteSwapMem): Delete definition.
2265 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2267 * interp.c (sim_do_command, sim_commands): Delete mips specific
2268 commands. Handled by module sim-options.
2270 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2271 (WITH_MODULO_MEMORY): Define.
2273 * interp.c (sim_info): Delete code printing memory size.
2275 * interp.c (mips_size): Nee sim_size, delete function.
2277 (monitor, monitor_base, monitor_size): Delete global variables.
2278 (sim_open, sim_close): Delete code creating monitor and other
2279 memory regions. Use sim-memopts module, via sim_do_commandf, to
2280 manage memory regions.
2281 (load_memory, store_memory): Use sim-core for memory model.
2283 * interp.c (address_translation): Delete all memory map code
2284 except line forcing 32 bit addresses.
2286 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2288 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2291 * interp.c (logfh, logfile): Delete globals.
2292 (sim_open, sim_close): Delete code opening & closing log file.
2293 (mips_option_handler): Delete -l and -n options.
2294 (OPTION mips_options): Ditto.
2296 * interp.c (OPTION mips_options): Rename option trace to dinero.
2297 (mips_option_handler): Update.
2299 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2301 * interp.c (fetch_str): New function.
2302 (sim_monitor): Rewrite using sim_read & sim_write.
2303 (sim_open): Check magic number.
2304 (sim_open): Write monitor vectors into memory using sim_write.
2305 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2306 (sim_read, sim_write): Simplify - transfer data one byte at a
2308 (load_memory, store_memory): Clarify meaning of parameter RAW.
2310 * sim-main.h (isHOST): Defete definition.
2311 (isTARGET): Mark as depreciated.
2312 (address_translation): Delete parameter HOST.
2314 * interp.c (address_translation): Delete parameter HOST.
2316 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2320 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2321 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2323 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2325 * mips.igen: Add model filter field to records.
2327 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2329 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2331 interp.c (sim_engine_run): Do not compile function sim_engine_run
2332 when WITH_IGEN == 1.
2334 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2335 target architecture.
2337 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2338 igen. Replace with configuration variables sim_igen_flags /
2341 * m16.igen: New file. Copy mips16 insns here.
2342 * mips.igen: From here.
2344 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2346 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2348 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2350 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2352 * gencode.c (build_instruction): Follow sim_write's lead in using
2353 BigEndianMem instead of !ByteSwapMem.
2355 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2357 * configure.in (sim_gen): Dependent on target, select type of
2358 generator. Always select old style generator.
2360 configure: Re-generate.
2362 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2364 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2365 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2366 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2367 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2368 SIM_@sim_gen@_*, set by autoconf.
2370 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2372 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2374 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2375 CURRENT_FLOATING_POINT instead.
2377 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2378 (address_translation): Raise exception InstructionFetch when
2379 translation fails and isINSTRUCTION.
2381 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2382 sim_engine_run): Change type of of vaddr and paddr to
2384 (address_translation, prefetch, load_memory, store_memory,
2385 cache_op): Change type of vAddr and pAddr to address_word.
2387 * gencode.c (build_instruction): Change type of vaddr and paddr to
2390 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2392 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2393 macro to obtain result of ALU op.
2395 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2397 * interp.c (sim_info): Call profile_print.
2399 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2401 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2403 * sim-main.h (WITH_PROFILE): Do not define, defined in
2404 common/sim-config.h. Use sim-profile module.
2405 (simPROFILE): Delete defintion.
2407 * interp.c (PROFILE): Delete definition.
2408 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2409 (sim_close): Delete code writing profile histogram.
2410 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2412 (sim_engine_run): Delete code profiling the PC.
2414 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2416 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2418 * interp.c (sim_monitor): Make register pointers of type
2421 * sim-main.h: Make registers of type unsigned_word not
2424 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2426 * interp.c (sync_operation): Rename from SyncOperation, make
2427 global, add SD argument.
2428 (prefetch): Rename from Prefetch, make global, add SD argument.
2429 (decode_coproc): Make global.
2431 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2433 * gencode.c (build_instruction): Generate DecodeCoproc not
2434 decode_coproc calls.
2436 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2437 (SizeFGR): Move to sim-main.h
2438 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2439 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2440 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2442 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2443 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2444 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2445 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2446 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2447 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2449 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2451 (sim-alu.h): Include.
2452 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2453 (sim_cia): Typedef to instruction_address.
2455 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2457 * Makefile.in (interp.o): Rename generated file engine.c to
2462 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2464 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2466 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2468 * gencode.c (build_instruction): For "FPSQRT", output correct
2469 number of arguments to Recip.
2471 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2473 * Makefile.in (interp.o): Depends on sim-main.h
2475 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2477 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2478 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2479 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2480 STATE, DSSTATE): Define
2481 (GPR, FGRIDX, ..): Define.
2483 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2484 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2485 (GPR, FGRIDX, ...): Delete macros.
2487 * interp.c: Update names to match defines from sim-main.h
2489 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2491 * interp.c (sim_monitor): Add SD argument.
2492 (sim_warning): Delete. Replace calls with calls to
2494 (sim_error): Delete. Replace calls with sim_io_error.
2495 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2496 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2497 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2499 (mips_size): Rename from sim_size. Add SD argument.
2501 * interp.c (simulator): Delete global variable.
2502 (callback): Delete global variable.
2503 (mips_option_handler, sim_open, sim_write, sim_read,
2504 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2505 sim_size,sim_monitor): Use sim_io_* not callback->*.
2506 (sim_open): ZALLOC simulator struct.
2507 (PROFILE): Do not define.
2509 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2511 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2512 support.h with corresponding code.
2514 * sim-main.h (word64, uword64), support.h: Move definition to
2516 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2519 * Makefile.in: Update dependencies
2520 * interp.c: Do not include.
2522 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2524 * interp.c (address_translation, load_memory, store_memory,
2525 cache_op): Rename to from AddressTranslation et.al., make global,
2528 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2531 * interp.c (SignalException): Rename to signal_exception, make
2534 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2536 * sim-main.h (SignalException, SignalExceptionInterrupt,
2537 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2538 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2539 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2542 * interp.c, support.h: Use.
2544 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2546 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2547 to value_fpr / store_fpr. Add SD argument.
2548 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2549 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2551 * sim-main.h (ValueFPR, StoreFPR): Define.
2553 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2555 * interp.c (sim_engine_run): Check consistency between configure
2556 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2559 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2560 (mips_fpu): Configure WITH_FLOATING_POINT.
2561 (mips_endian): Configure WITH_TARGET_ENDIAN.
2562 * configure: Update.
2564 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2566 * configure: Regenerated to track ../common/aclocal.m4 changes.
2568 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2570 * configure: Regenerated.
2572 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2574 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2576 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2578 * gencode.c (print_igen_insn_models): Assume certain architectures
2579 include all mips* instructions.
2580 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2583 * Makefile.in (tmp.igen): Add target. Generate igen input from
2586 * gencode.c (FEATURE_IGEN): Define.
2587 (main): Add --igen option. Generate output in igen format.
2588 (process_instructions): Format output according to igen option.
2589 (print_igen_insn_format): New function.
2590 (print_igen_insn_models): New function.
2591 (process_instructions): Only issue warnings and ignore
2592 instructions when no FEATURE_IGEN.
2594 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2596 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2599 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2601 * configure: Regenerated to track ../common/aclocal.m4 changes.
2603 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2605 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2606 SIM_RESERVED_BITS): Delete, moved to common.
2607 (SIM_EXTRA_CFLAGS): Update.
2609 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2611 * configure.in: Configure non-strict memory alignment.
2612 * configure: Regenerated to track ../common/aclocal.m4 changes.
2614 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2616 * configure: Regenerated to track ../common/aclocal.m4 changes.
2618 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2620 * gencode.c (SDBBP,DERET): Added (3900) insns.
2621 (RFE): Turn on for 3900.
2622 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2623 (dsstate): Made global.
2624 (SUBTARGET_R3900): Added.
2625 (CANCELDELAYSLOT): New.
2626 (SignalException): Ignore SystemCall rather than ignore and
2627 terminate. Add DebugBreakPoint handling.
2628 (decode_coproc): New insns RFE, DERET; and new registers Debug
2629 and DEPC protected by SUBTARGET_R3900.
2630 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2632 * Makefile.in,configure.in: Add mips subtarget option.
2633 * configure: Update.
2635 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2637 * gencode.c: Add r3900 (tx39).
2640 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2642 * gencode.c (build_instruction): Don't need to subtract 4 for
2645 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2647 * interp.c: Correct some HASFPU problems.
2649 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2651 * configure: Regenerated to track ../common/aclocal.m4 changes.
2653 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2655 * interp.c (mips_options): Fix samples option short form, should
2658 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2660 * interp.c (sim_info): Enable info code. Was just returning.
2662 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2664 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2667 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2669 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2671 (build_instruction): Ditto for LL.
2673 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2675 * configure: Regenerated to track ../common/aclocal.m4 changes.
2677 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2679 * configure: Regenerated to track ../common/aclocal.m4 changes.
2682 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2684 * interp.c (sim_open): Add call to sim_analyze_program, update
2687 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2689 * interp.c (sim_kill): Delete.
2690 (sim_create_inferior): Add ABFD argument. Set PC from same.
2691 (sim_load): Move code initializing trap handlers from here.
2692 (sim_open): To here.
2693 (sim_load): Delete, use sim-hload.c.
2695 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2697 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2699 * configure: Regenerated to track ../common/aclocal.m4 changes.
2702 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2704 * interp.c (sim_open): Add ABFD argument.
2705 (sim_load): Move call to sim_config from here.
2706 (sim_open): To here. Check return status.
2708 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2710 * gencode.c (build_instruction): Two arg MADD should
2711 not assign result to $0.
2713 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2715 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2716 * sim/mips/configure.in: Regenerate.
2718 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2720 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2721 signed8, unsigned8 et.al. types.
2723 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2724 hosts when selecting subreg.
2726 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2728 * interp.c (sim_engine_run): Reset the ZERO register to zero
2729 regardless of FEATURE_WARN_ZERO.
2730 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2732 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2734 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2735 (SignalException): For BreakPoints ignore any mode bits and just
2737 (SignalException): Always set the CAUSE register.
2739 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2741 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2742 exception has been taken.
2744 * interp.c: Implement the ERET and mt/f sr instructions.
2746 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2748 * interp.c (SignalException): Don't bother restarting an
2751 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2753 * interp.c (SignalException): Really take an interrupt.
2754 (interrupt_event): Only deliver interrupts when enabled.
2756 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2758 * interp.c (sim_info): Only print info when verbose.
2759 (sim_info) Use sim_io_printf for output.
2761 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2763 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2766 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2768 * interp.c (sim_do_command): Check for common commands if a
2769 simulator specific command fails.
2771 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2773 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2774 and simBE when DEBUG is defined.
2776 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2778 * interp.c (interrupt_event): New function. Pass exception event
2779 onto exception handler.
2781 * configure.in: Check for stdlib.h.
2782 * configure: Regenerate.
2784 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2785 variable declaration.
2786 (build_instruction): Initialize memval1.
2787 (build_instruction): Add UNUSED attribute to byte, bigend,
2789 (build_operands): Ditto.
2791 * interp.c: Fix GCC warnings.
2792 (sim_get_quit_code): Delete.
2794 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2795 * Makefile.in: Ditto.
2796 * configure: Re-generate.
2798 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2800 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2802 * interp.c (mips_option_handler): New function parse argumes using
2804 (myname): Replace with STATE_MY_NAME.
2805 (sim_open): Delete check for host endianness - performed by
2807 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2808 (sim_open): Move much of the initialization from here.
2809 (sim_load): To here. After the image has been loaded and
2811 (sim_open): Move ColdReset from here.
2812 (sim_create_inferior): To here.
2813 (sim_open): Make FP check less dependant on host endianness.
2815 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2817 * interp.c (sim_set_callbacks): Delete.
2819 * interp.c (membank, membank_base, membank_size): Replace with
2820 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2821 (sim_open): Remove call to callback->init. gdb/run do this.
2825 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2827 * interp.c (big_endian_p): Delete, replaced by
2828 current_target_byte_order.
2830 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2832 * interp.c (host_read_long, host_read_word, host_swap_word,
2833 host_swap_long): Delete. Using common sim-endian.
2834 (sim_fetch_register, sim_store_register): Use H2T.
2835 (pipeline_ticks): Delete. Handled by sim-events.
2837 (sim_engine_run): Update.
2839 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2841 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2843 (SignalException): To here. Signal using sim_engine_halt.
2844 (sim_stop_reason): Delete, moved to common.
2846 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2848 * interp.c (sim_open): Add callback argument.
2849 (sim_set_callbacks): Delete SIM_DESC argument.
2852 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2854 * Makefile.in (SIM_OBJS): Add common modules.
2856 * interp.c (sim_set_callbacks): Also set SD callback.
2857 (set_endianness, xfer_*, swap_*): Delete.
2858 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2859 Change to functions using sim-endian macros.
2860 (control_c, sim_stop): Delete, use common version.
2861 (simulate): Convert into.
2862 (sim_engine_run): This function.
2863 (sim_resume): Delete.
2865 * interp.c (simulation): New variable - the simulator object.
2866 (sim_kind): Delete global - merged into simulation.
2867 (sim_load): Cleanup. Move PC assignment from here.
2868 (sim_create_inferior): To here.
2870 * sim-main.h: New file.
2871 * interp.c (sim-main.h): Include.
2873 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2875 * configure: Regenerated to track ../common/aclocal.m4 changes.
2877 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2879 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2881 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2883 * gencode.c (build_instruction): DIV instructions: check
2884 for division by zero and integer overflow before using
2885 host's division operation.
2887 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2889 * Makefile.in (SIM_OBJS): Add sim-load.o.
2890 * interp.c: #include bfd.h.
2891 (target_byte_order): Delete.
2892 (sim_kind, myname, big_endian_p): New static locals.
2893 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2894 after argument parsing. Recognize -E arg, set endianness accordingly.
2895 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2896 load file into simulator. Set PC from bfd.
2897 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2898 (set_endianness): Use big_endian_p instead of target_byte_order.
2900 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2902 * interp.c (sim_size): Delete prototype - conflicts with
2903 definition in remote-sim.h. Correct definition.
2905 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2907 * configure: Regenerated to track ../common/aclocal.m4 changes.
2910 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2912 * interp.c (sim_open): New arg `kind'.
2914 * configure: Regenerated to track ../common/aclocal.m4 changes.
2916 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2918 * configure: Regenerated to track ../common/aclocal.m4 changes.
2920 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2922 * interp.c (sim_open): Set optind to 0 before calling getopt.
2924 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2926 * configure: Regenerated to track ../common/aclocal.m4 changes.
2928 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2930 * interp.c : Replace uses of pr_addr with pr_uword64
2931 where the bit length is always 64 independent of SIM_ADDR.
2932 (pr_uword64) : added.
2934 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2936 * configure: Re-generate.
2938 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2940 * configure: Regenerate to track ../common/aclocal.m4 changes.
2942 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2944 * interp.c (sim_open): New SIM_DESC result. Argument is now
2946 (other sim_*): New SIM_DESC argument.
2948 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2950 * interp.c: Fix printing of addresses for non-64-bit targets.
2951 (pr_addr): Add function to print address based on size.
2953 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2955 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2957 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2959 * gencode.c (build_mips16_operands): Correct computation of base
2960 address for extended PC relative instruction.
2962 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2964 * interp.c (mips16_entry): Add support for floating point cases.
2965 (SignalException): Pass floating point cases to mips16_entry.
2966 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2968 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2970 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2971 and then set the state to fmt_uninterpreted.
2972 (COP_SW): Temporarily set the state to fmt_word while calling
2975 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2977 * gencode.c (build_instruction): The high order may be set in the
2978 comparison flags at any ISA level, not just ISA 4.
2980 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2982 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2983 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2984 * configure.in: sinclude ../common/aclocal.m4.
2985 * configure: Regenerated.
2987 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2989 * configure: Rebuild after change to aclocal.m4.
2991 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2993 * configure configure.in Makefile.in: Update to new configure
2994 scheme which is more compatible with WinGDB builds.
2995 * configure.in: Improve comment on how to run autoconf.
2996 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2997 * Makefile.in: Use autoconf substitution to install common
3000 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3002 * gencode.c (build_instruction): Use BigEndianCPU instead of
3005 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3007 * interp.c (sim_monitor): Make output to stdout visible in
3008 wingdb's I/O log window.
3010 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3012 * support.h: Undo previous change to SIGTRAP
3015 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3017 * interp.c (store_word, load_word): New static functions.
3018 (mips16_entry): New static function.
3019 (SignalException): Look for mips16 entry and exit instructions.
3020 (simulate): Use the correct index when setting fpr_state after
3021 doing a pending move.
3023 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3025 * interp.c: Fix byte-swapping code throughout to work on
3026 both little- and big-endian hosts.
3028 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3030 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3031 with gdb/config/i386/xm-windows.h.
3033 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3035 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3036 that messes up arithmetic shifts.
3038 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3040 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3041 SIGTRAP and SIGQUIT for _WIN32.
3043 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3045 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3046 force a 64 bit multiplication.
3047 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3048 destination register is 0, since that is the default mips16 nop
3051 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3053 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3054 (build_endian_shift): Don't check proc64.
3055 (build_instruction): Always set memval to uword64. Cast op2 to
3056 uword64 when shifting it left in memory instructions. Always use
3057 the same code for stores--don't special case proc64.
3059 * gencode.c (build_mips16_operands): Fix base PC value for PC
3061 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3063 * interp.c (simJALDELAYSLOT): Define.
3064 (JALDELAYSLOT): Define.
3065 (INDELAYSLOT, INJALDELAYSLOT): Define.
3066 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3068 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3070 * interp.c (sim_open): add flush_cache as a PMON routine
3071 (sim_monitor): handle flush_cache by ignoring it
3073 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3075 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3077 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3078 (BigEndianMem): Rename to ByteSwapMem and change sense.
3079 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3080 BigEndianMem references to !ByteSwapMem.
3081 (set_endianness): New function, with prototype.
3082 (sim_open): Call set_endianness.
3083 (sim_info): Use simBE instead of BigEndianMem.
3084 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3085 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3086 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3087 ifdefs, keeping the prototype declaration.
3088 (swap_word): Rewrite correctly.
3089 (ColdReset): Delete references to CONFIG. Delete endianness related
3090 code; moved to set_endianness.
3092 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3094 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3095 * interp.c (CHECKHILO): Define away.
3096 (simSIGINT): New macro.
3097 (membank_size): Increase from 1MB to 2MB.
3098 (control_c): New function.
3099 (sim_resume): Rename parameter signal to signal_number. Add local
3100 variable prev. Call signal before and after simulate.
3101 (sim_stop_reason): Add simSIGINT support.
3102 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3104 (sim_warning): Delete call to SignalException. Do call printf_filtered
3106 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3107 a call to sim_warning.
3109 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3111 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3112 16 bit instructions.
3114 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3116 Add support for mips16 (16 bit MIPS implementation):
3117 * gencode.c (inst_type): Add mips16 instruction encoding types.
3118 (GETDATASIZEINSN): Define.
3119 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3120 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3122 (MIPS16_DECODE): New table, for mips16 instructions.
3123 (bitmap_val): New static function.
3124 (struct mips16_op): Define.
3125 (mips16_op_table): New table, for mips16 operands.
3126 (build_mips16_operands): New static function.
3127 (process_instructions): If PC is odd, decode a mips16
3128 instruction. Break out instruction handling into new
3129 build_instruction function.
3130 (build_instruction): New static function, broken out of
3131 process_instructions. Check modifiers rather than flags for SHIFT
3132 bit count and m[ft]{hi,lo} direction.
3133 (usage): Pass program name to fprintf.
3134 (main): Remove unused variable this_option_optind. Change
3135 ``*loptarg++'' to ``loptarg++''.
3136 (my_strtoul): Parenthesize && within ||.
3137 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3138 (simulate): If PC is odd, fetch a 16 bit instruction, and
3139 increment PC by 2 rather than 4.
3140 * configure.in: Add case for mips16*-*-*.
3141 * configure: Rebuild.
3143 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3145 * interp.c: Allow -t to enable tracing in standalone simulator.
3146 Fix garbage output in trace file and error messages.
3148 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3150 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3151 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3152 * configure.in: Simplify using macros in ../common/aclocal.m4.
3153 * configure: Regenerated.
3154 * tconfig.in: New file.
3156 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3158 * interp.c: Fix bugs in 64-bit port.
3159 Use ansi function declarations for msvc compiler.
3160 Initialize and test file pointer in trace code.
3161 Prevent duplicate definition of LAST_EMED_REGNUM.
3163 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3165 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3167 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3169 * interp.c (SignalException): Check for explicit terminating
3171 * gencode.c: Pass instruction value through SignalException()
3172 calls for Trap, Breakpoint and Syscall.
3174 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3176 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3177 only used on those hosts that provide it.
3178 * configure.in: Add sqrt() to list of functions to be checked for.
3179 * config.in: Re-generated.
3180 * configure: Re-generated.
3182 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3184 * gencode.c (process_instructions): Call build_endian_shift when
3185 expanding STORE RIGHT, to fix swr.
3186 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3187 clear the high bits.
3188 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3189 Fix float to int conversions to produce signed values.
3191 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3193 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3194 (process_instructions): Correct handling of nor instruction.
3195 Correct shift count for 32 bit shift instructions. Correct sign
3196 extension for arithmetic shifts to not shift the number of bits in
3197 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3198 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3200 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3201 It's OK to have a mult follow a mult. What's not OK is to have a
3202 mult follow an mfhi.
3203 (Convert): Comment out incorrect rounding code.
3205 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3207 * interp.c (sim_monitor): Improved monitor printf
3208 simulation. Tidied up simulator warnings, and added "--log" option
3209 for directing warning message output.
3210 * gencode.c: Use sim_warning() rather than WARNING macro.
3212 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3214 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3215 getopt1.o, rather than on gencode.c. Link objects together.
3216 Don't link against -liberty.
3217 (gencode.o, getopt.o, getopt1.o): New targets.
3218 * gencode.c: Include <ctype.h> and "ansidecl.h".
3219 (AND): Undefine after including "ansidecl.h".
3220 (ULONG_MAX): Define if not defined.
3221 (OP_*): Don't define macros; now defined in opcode/mips.h.
3222 (main): Call my_strtoul rather than strtoul.
3223 (my_strtoul): New static function.
3225 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3227 * gencode.c (process_instructions): Generate word64 and uword64
3228 instead of `long long' and `unsigned long long' data types.
3229 * interp.c: #include sysdep.h to get signals, and define default
3231 * (Convert): Work around for Visual-C++ compiler bug with type
3233 * support.h: Make things compile under Visual-C++ by using
3234 __int64 instead of `long long'. Change many refs to long long
3235 into word64/uword64 typedefs.
3237 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3239 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3240 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3242 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3243 (AC_PROG_INSTALL): Added.
3244 (AC_PROG_CC): Moved to before configure.host call.
3245 * configure: Rebuilt.
3247 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3249 * configure.in: Define @SIMCONF@ depending on mips target.
3250 * configure: Rebuild.
3251 * Makefile.in (run): Add @SIMCONF@ to control simulator
3253 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3254 * interp.c: Remove some debugging, provide more detailed error
3255 messages, update memory accesses to use LOADDRMASK.
3257 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3259 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3260 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3262 * configure: Rebuild.
3263 * config.in: New file, generated by autoheader.
3264 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3265 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3266 HAVE_ANINT and HAVE_AINT, as appropriate.
3267 * Makefile.in (run): Use @LIBS@ rather than -lm.
3268 (interp.o): Depend upon config.h.
3269 (Makefile): Just rebuild Makefile.
3270 (clean): Remove stamp-h.
3271 (mostlyclean): Make the same as clean, not as distclean.
3272 (config.h, stamp-h): New targets.
3274 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3276 * interp.c (ColdReset): Fix boolean test. Make all simulator
3279 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3281 * interp.c (xfer_direct_word, xfer_direct_long,
3282 swap_direct_word, swap_direct_long, xfer_big_word,
3283 xfer_big_long, xfer_little_word, xfer_little_long,
3284 swap_word,swap_long): Added.
3285 * interp.c (ColdReset): Provide function indirection to
3286 host<->simulated_target transfer routines.
3287 * interp.c (sim_store_register, sim_fetch_register): Updated to
3288 make use of indirected transfer routines.
3290 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3292 * gencode.c (process_instructions): Ensure FP ABS instruction
3294 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3295 system call support.
3297 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3299 * interp.c (sim_do_command): Complain if callback structure not
3302 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3304 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3305 support for Sun hosts.
3306 * Makefile.in (gencode): Ensure the host compiler and libraries
3307 used for cross-hosted build.
3309 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3311 * interp.c, gencode.c: Some more (TODO) tidying.
3313 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3315 * gencode.c, interp.c: Replaced explicit long long references with
3316 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3317 * support.h (SET64LO, SET64HI): Macros added.
3319 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3321 * configure: Regenerate with autoconf 2.7.
3323 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3325 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3326 * support.h: Remove superfluous "1" from #if.
3327 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3329 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3331 * interp.c (StoreFPR): Control UndefinedResult() call on
3332 WARN_RESULT manifest.
3334 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3336 * gencode.c: Tidied instruction decoding, and added FP instruction
3339 * interp.c: Added dineroIII, and BSD profiling support. Also
3340 run-time FP handling.
3342 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3344 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3345 gencode.c, interp.c, support.h: created.