1 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
3 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
6 * m16.igen: Implement MIPS16 instructions.
8 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
9 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
10 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
11 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
12 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
13 bodies of corresponding code from 32 bit insn to these. Also used
14 by MIPS16 versions of functions.
16 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
17 (IMEM16): Drop NR argument from macro.
20 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
22 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
23 of VU lower instruction.
27 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
29 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
32 * sim-main.h: Removed attempt at allowing 128-bit access.
36 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
38 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
40 * interp.c (decode_coproc): Refer to VU CIA as a "special"
41 register, not as a "misc" register. Aha. Add activity
42 assertions after VCALLMS* instructions.
46 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
48 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
49 to upper code of generated VU instruction.
53 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
55 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
57 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
60 * r5900.igen (SQC2): Thinko.
64 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
66 * interp.c (*): Adapt code to merged VU device & state structs.
67 (decode_coproc): Execute COP2 each macroinstruction without
68 pipelining, by stepping VU to completion state. Adapted to
69 read_vu_*_reg style of register access.
71 * mips.igen ([SL]QC2): Removed these COP2 instructions.
73 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
75 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
78 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
80 * Makefile.in (SIM_OBJS): Add sim-main.o.
82 * sim-main.h (address_translation, load_memory, store_memory,
83 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
85 (pr_addr, pr_uword64): Declare.
86 (sim-main.c): Include when H_REVEALS_MODULE_P.
88 * interp.c (address_translation, load_memory, store_memory,
89 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
91 * sim-main.c: To here. Fix compilation problems.
93 * configure.in: Enable inlining.
94 * configure: Re-config.
96 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
98 * configure: Regenerated to track ../common/aclocal.m4 changes.
100 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
102 * mips.igen: Include tx.igen.
103 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
104 * tx.igen: New file, contains MADD and MADDU.
106 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
107 the hardwired constant `7'.
108 (store_memory): Ditto.
109 (LOADDRMASK): Move definition to sim-main.h.
111 mips.igen (MTC0): Enable for r3900.
114 mips.igen (do_load_byte): Delete.
115 (do_load, do_store, do_load_left, do_load_write, do_store_left,
116 do_store_right): New functions.
117 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
119 configure.in: Let the tx39 use igen again.
122 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
124 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
125 not an address sized quantity. Return zero for cache sizes.
127 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
129 * mips.igen (r3900): r3900 does not support 64 bit integer
133 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
135 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
139 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
141 * interp.c (decode_coproc): Continuing COP2 work.
142 (cop_[ls]q): Make sky-target-only.
144 * sim-main.h (COP_[LS]Q): Make sky-target-only.
146 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
148 * configure.in (mipstx39*-*-*): Use gencode simulator rather
150 * configure : Rebuild.
153 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
155 * interp.c (decode_coproc): Added a missing TARGET_SKY check
156 around COP2 implementation skeleton.
160 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
162 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
164 * interp.c (sim_{load,store}_register): Use new vu[01]_device
165 static to access VU registers.
166 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
167 decoding. Work in progress.
169 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
170 overlapping/redundant bit pattern.
171 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
174 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
177 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
178 access to coprocessor registers.
180 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
182 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
184 * configure: Regenerated to track ../common/aclocal.m4 changes.
186 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
188 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
190 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
192 * configure: Regenerated to track ../common/aclocal.m4 changes.
193 * config.in: Regenerated to track ../common/aclocal.m4 changes.
195 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
197 * configure: Regenerated to track ../common/aclocal.m4 changes.
199 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
201 * interp.c (Max, Min): Comment out functions. Not yet used.
203 start-sanitize-vr4320
204 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
206 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
209 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
211 * configure: Regenerated to track ../common/aclocal.m4 changes.
213 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
215 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
216 configurable settings for stand-alone simulator.
219 * configure.in: Added --with-sim-gpu2 option to specify path of
220 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
221 links/compiles stand-alone simulator with this library.
223 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
225 * configure.in: Added X11 search, just in case.
227 * configure: Regenerated.
229 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
231 * interp.c (sim_write, sim_read, load_memory, store_memory):
232 Replace sim_core_*_map with read_map, write_map, exec_map resp.
234 start-sanitize-vr4320
235 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
237 * vr4320.igen (clz,dclz) : Added.
238 (dmac): Replaced 99, with LO.
241 start-sanitize-vr5400
242 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
244 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
247 start-sanitize-vr4320
248 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
250 * vr4320.igen: New file.
251 * Makefile.in (vr4320.igen) : Added.
252 * configure.in (mips64vr4320-*-*): Added.
253 * configure : Rebuilt.
254 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
255 Add the vr4320 model entry and mark the vr4320 insn as necessary.
258 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
260 * sim-main.h (GETFCC): Return an unsigned value.
263 * r5900.igen: Use an unsigned array index variable `i'.
264 (QFSRV): Ditto for variable bytes.
267 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
269 * mips.igen (DIV): Fix check for -1 / MIN_INT.
270 (DADD): Result destination is RD not RT.
273 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
274 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
278 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
280 * sim-main.h (HIACCESS, LOACCESS): Always define.
282 * mdmx.igen (Maxi, Mini): Rename Max, Min.
284 * interp.c (sim_info): Delete.
286 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
288 * interp.c (DECLARE_OPTION_HANDLER): Use it.
289 (mips_option_handler): New argument `cpu'.
290 (sim_open): Update call to sim_add_option_table.
292 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
294 * mips.igen (CxC1): Add tracing.
297 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
299 * r5900.igen (StoreFP): Delete.
300 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
302 (rsqrt.s, sqrt.s): Implement.
303 (r59cond): New function.
304 (C.COND.S): Call r59cond in assembler line.
305 (cvt.w.s, cvt.s.w): Implement.
307 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
310 * sim-main.h: Define an enum of r5900 FCSR bit fields.
314 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
316 * r5900.igen: Add tracing to all p* instructions.
318 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
320 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
321 to get gdb talking to re-aranged sim_cpu register structure.
324 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
326 * sim-main.h (Max, Min): Declare.
328 * interp.c (Max, Min): New functions.
330 * mips.igen (BC1): Add tracing.
332 start-sanitize-vr5400
333 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
335 * mdmx.igen: Tag all functions as requiring either with mdmx or
340 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
342 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
344 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
346 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
348 * r5900.igen: Rewrite.
350 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
352 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
353 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
356 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
358 * interp.c Added memory map for stack in vr4100
360 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
362 * interp.c (load_memory): Add missing "break"'s.
364 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
366 * interp.c (sim_store_register, sim_fetch_register): Pass in
367 length parameter. Return -1.
369 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
371 * interp.c: Added hardware init hook, fixed warnings.
373 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
375 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
377 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
379 * interp.c (ifetch16): New function.
381 * sim-main.h (IMEM32): Rename IMEM.
382 (IMEM16_IMMED): Define.
384 (DELAY_SLOT): Update.
386 * m16run.c (sim_engine_run): New file.
388 * m16.igen: All instructions except LB.
389 (LB): Call do_load_byte.
390 * mips.igen (do_load_byte): New function.
391 (LB): Call do_load_byte.
393 * mips.igen: Move spec for insn bit size and high bit from here.
394 * Makefile.in (tmp-igen, tmp-m16): To here.
396 * m16.dc: New file, decode mips16 instructions.
398 * Makefile.in (SIM_NO_ALL): Define.
399 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
402 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
406 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
408 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
409 point unit to 32 bit registers.
410 * configure: Re-generate.
412 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
414 * configure.in (sim_use_gen): Make IGEN the default simulator
415 generator for generic 32 and 64 bit mips targets.
416 * configure: Re-generate.
418 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
420 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
423 * interp.c (sim_fetch_register, sim_store_register): Read/write
424 FGR from correct location.
425 (sim_open): Set size of FGR's according to
426 WITH_TARGET_FLOATING_POINT_BITSIZE.
428 * sim-main.h (FGR): Store floating point registers in a separate
431 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
433 * configure: Regenerated to track ../common/aclocal.m4 changes.
435 start-sanitize-vr5400
436 * mdmx.igen: Mark all instructions as 64bit/fp specific.
439 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
441 * interp.c (ColdReset): Call PENDING_INVALIDATE.
443 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
445 * interp.c (pending_tick): New function. Deliver pending writes.
447 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
448 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
449 it can handle mixed sized quantites and single bits.
451 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
453 * interp.c (oengine.h): Do not include when building with IGEN.
454 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
455 (sim_info): Ditto for PROCESSOR_64BIT.
456 (sim_monitor): Replace ut_reg with unsigned_word.
457 (*): Ditto for t_reg.
458 (LOADDRMASK): Define.
459 (sim_open): Remove defunct check that host FP is IEEE compliant,
460 using software to emulate floating point.
461 (value_fpr, ...): Always compile, was conditional on HASFPU.
463 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
465 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
468 * interp.c (SD, CPU): Define.
469 (mips_option_handler): Set flags in each CPU.
470 (interrupt_event): Assume CPU 0 is the one being iterrupted.
471 (sim_close): Do not clear STATE, deleted anyway.
472 (sim_write, sim_read): Assume CPU zero's vm should be used for
474 (sim_create_inferior): Set the PC for all processors.
475 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
477 (mips16_entry): Pass correct nr of args to store_word, load_word.
478 (ColdReset): Cold reset all cpu's.
479 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
480 (sim_monitor, load_memory, store_memory, signal_exception): Use
481 `CPU' instead of STATE_CPU.
484 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
487 * sim-main.h (signal_exception): Add sim_cpu arg.
488 (SignalException*): Pass both SD and CPU to signal_exception.
489 * interp.c (signal_exception): Update.
491 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
493 (sync_operation, prefetch, cache_op, store_memory, load_memory,
494 address_translation): Ditto
495 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
497 start-sanitize-vr5400
498 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
500 (ByteAlign): Use StoreFPR, pass args in correct order.
504 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
506 * configure.in (sim_igen_filter): For r5900, configure as SMP.
509 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
511 * configure: Regenerated to track ../common/aclocal.m4 changes.
513 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
516 * configure.in (sim_igen_filter): For r5900, use igen.
517 * configure: Re-generate.
520 * interp.c (sim_engine_run): Add `nr_cpus' argument.
522 * mips.igen (model): Map processor names onto BFD name.
524 * sim-main.h (CPU_CIA): Delete.
525 (SET_CIA, GET_CIA): Define
527 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
529 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
532 * configure.in (default_endian): Configure a big-endian simulator
534 * configure: Re-generate.
536 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
538 * configure: Regenerated to track ../common/aclocal.m4 changes.
540 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
542 * interp.c (sim_monitor): Handle Densan monitor outbyte
543 and inbyte functions.
545 1997-12-29 Felix Lee <flee@cygnus.com>
547 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
549 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
551 * Makefile.in (tmp-igen): Arrange for $zero to always be
552 reset to zero after every instruction.
554 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
556 * configure: Regenerated to track ../common/aclocal.m4 changes.
559 start-sanitize-vr5400
560 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
562 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
566 start-sanitize-vr5400
567 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
569 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
570 vr5400 with the vr5000 as the default.
573 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
575 * mips.igen (MSUB): Fix to work like MADD.
576 * gencode.c (MSUB): Similarly.
578 start-sanitize-vr5400
579 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
581 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
585 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
587 * configure: Regenerated to track ../common/aclocal.m4 changes.
589 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
591 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
593 start-sanitize-vr5400
594 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
595 (value_cc, store_cc): Implement.
597 * sim-main.h: Add 8*3*8 bit accumulator.
599 * vr5400.igen: Move mdmx instructins from here
600 * mdmx.igen: To here - new file. Add/fix missing instructions.
601 * mips.igen: Include mdmx.igen.
602 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
605 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
607 * sim-main.h (sim-fpu.h): Include.
609 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
610 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
611 using host independant sim_fpu module.
613 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
615 * interp.c (signal_exception): Report internal errors with SIGABRT
618 * sim-main.h (C0_CONFIG): New register.
619 (signal.h): No longer include.
621 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
623 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
625 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
627 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
629 * mips.igen: Tag vr5000 instructions.
630 (ANDI): Was missing mipsIV model, fix assembler syntax.
631 (do_c_cond_fmt): New function.
632 (C.cond.fmt): Handle mips I-III which do not support CC field
634 (bc1): Handle mips IV which do not have a delaed FCC separatly.
635 (SDR): Mask paddr when BigEndianMem, not the converse as specified
637 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
638 vr5000 which saves LO in a GPR separatly.
640 * configure.in (enable-sim-igen): For vr5000, select vr5000
641 specific instructions.
642 * configure: Re-generate.
644 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
646 * Makefile.in (SIM_OBJS): Add sim-fpu module.
648 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
649 fmt_uninterpreted_64 bit cases to switch. Convert to
652 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
654 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
655 as specified in IV3.2 spec.
656 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
658 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
660 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
661 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
662 (start-sanitize-r5900):
663 (LWXC1, SWXC1): Delete from r5900 instruction set.
664 (end-sanitize-r5900):
665 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
666 PENDING_FILL versions of instructions. Simplify.
668 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
670 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
672 (MTHI, MFHI): Disable code checking HI-LO.
674 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
676 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
678 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
680 * gencode.c (build_mips16_operands): Replace IPC with cia.
682 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
683 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
685 (UndefinedResult): Replace function with macro/function
687 (sim_engine_run): Don't save PC in IPC.
689 * sim-main.h (IPC): Delete.
691 start-sanitize-vr5400
692 * vr5400.igen (vr): Add missing cia argument to value_fpr.
693 (do_select): Rename function select.
696 * interp.c (signal_exception, store_word, load_word,
697 address_translation, load_memory, store_memory, cache_op,
698 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
699 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
700 current instruction address - cia - argument.
701 (sim_read, sim_write): Call address_translation directly.
702 (sim_engine_run): Rename variable vaddr to cia.
703 (signal_exception): Pass cia to sim_monitor
705 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
706 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
707 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
709 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
710 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
713 * interp.c (signal_exception): Pass restart address to
716 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
717 idecode.o): Add dependency.
719 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
721 (DELAY_SLOT): Update NIA not PC with branch address.
722 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
724 * mips.igen: Use CIA not PC in branch calculations.
725 (illegal): Call SignalException.
726 (BEQ, ADDIU): Fix assembler.
728 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
730 * m16.igen (JALX): Was missing.
732 * configure.in (enable-sim-igen): New configuration option.
733 * configure: Re-generate.
735 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
737 * interp.c (load_memory, store_memory): Delete parameter RAW.
738 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
739 bypassing {load,store}_memory.
741 * sim-main.h (ByteSwapMem): Delete definition.
743 * Makefile.in (SIM_OBJS): Add sim-memopt module.
745 * interp.c (sim_do_command, sim_commands): Delete mips specific
746 commands. Handled by module sim-options.
748 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
749 (WITH_MODULO_MEMORY): Define.
751 * interp.c (sim_info): Delete code printing memory size.
753 * interp.c (mips_size): Nee sim_size, delete function.
755 (monitor, monitor_base, monitor_size): Delete global variables.
756 (sim_open, sim_close): Delete code creating monitor and other
757 memory regions. Use sim-memopts module, via sim_do_commandf, to
758 manage memory regions.
759 (load_memory, store_memory): Use sim-core for memory model.
761 * interp.c (address_translation): Delete all memory map code
762 except line forcing 32 bit addresses.
764 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
766 * sim-main.h (WITH_TRACE): Delete definition. Enables common
769 * interp.c (logfh, logfile): Delete globals.
770 (sim_open, sim_close): Delete code opening & closing log file.
771 (mips_option_handler): Delete -l and -n options.
772 (OPTION mips_options): Ditto.
774 * interp.c (OPTION mips_options): Rename option trace to dinero.
775 (mips_option_handler): Update.
777 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
779 * interp.c (fetch_str): New function.
780 (sim_monitor): Rewrite using sim_read & sim_write.
781 (sim_open): Check magic number.
782 (sim_open): Write monitor vectors into memory using sim_write.
783 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
784 (sim_read, sim_write): Simplify - transfer data one byte at a
786 (load_memory, store_memory): Clarify meaning of parameter RAW.
788 * sim-main.h (isHOST): Defete definition.
789 (isTARGET): Mark as depreciated.
790 (address_translation): Delete parameter HOST.
792 * interp.c (address_translation): Delete parameter HOST.
795 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
797 * gencode.c: Add tx49 configury and insns.
798 * configure.in: Add tx49 configury.
802 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
806 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
807 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
809 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
811 * mips.igen: Add model filter field to records.
813 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
815 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
817 interp.c (sim_engine_run): Do not compile function sim_engine_run
820 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
823 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
824 igen. Replace with configuration variables sim_igen_flags /
828 * r5900.igen: New file. Copy r5900 insns here.
830 start-sanitize-vr5400
831 * vr5400.igen: New file.
833 * m16.igen: New file. Copy mips16 insns here.
834 * mips.igen: From here.
836 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
838 start-sanitize-vr5400
839 * mips.igen: Tag all mipsIV instructions with vr5400 model.
841 * configure.in: Add mips64vr5400 target.
842 * configure: Re-generate.
845 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
847 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
849 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
851 * gencode.c (build_instruction): Follow sim_write's lead in using
852 BigEndianMem instead of !ByteSwapMem.
854 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
856 * configure.in (sim_gen): Dependent on target, select type of
857 generator. Always select old style generator.
859 configure: Re-generate.
861 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
863 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
864 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
865 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
866 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
867 SIM_@sim_gen@_*, set by autoconf.
869 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
871 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
873 * interp.c (ColdReset): Remove #ifdef HASFPU, check
874 CURRENT_FLOATING_POINT instead.
876 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
877 (address_translation): Raise exception InstructionFetch when
878 translation fails and isINSTRUCTION.
880 * interp.c (sim_open, sim_write, sim_monitor, store_word,
881 sim_engine_run): Change type of of vaddr and paddr to
883 (address_translation, prefetch, load_memory, store_memory,
884 cache_op): Change type of vAddr and pAddr to address_word.
886 * gencode.c (build_instruction): Change type of vaddr and paddr to
889 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
891 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
892 macro to obtain result of ALU op.
894 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
896 * interp.c (sim_info): Call profile_print.
898 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
900 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
902 * sim-main.h (WITH_PROFILE): Do not define, defined in
903 common/sim-config.h. Use sim-profile module.
904 (simPROFILE): Delete defintion.
906 * interp.c (PROFILE): Delete definition.
907 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
908 (sim_close): Delete code writing profile histogram.
909 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
911 (sim_engine_run): Delete code profiling the PC.
913 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
915 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
917 * interp.c (sim_monitor): Make register pointers of type
920 * sim-main.h: Make registers of type unsigned_word not
923 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
926 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
927 ...): Move to sim-main.h
930 * interp.c (sync_operation): Rename from SyncOperation, make
931 global, add SD argument.
932 (prefetch): Rename from Prefetch, make global, add SD argument.
933 (decode_coproc): Make global.
935 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
937 * gencode.c (build_instruction): Generate DecodeCoproc not
940 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
941 (SizeFGR): Move to sim-main.h
942 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
943 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
944 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
946 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
947 FP_RM_TOMINF, GETRM): Move to sim-main.h.
948 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
949 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
950 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
951 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
953 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
955 (sim-alu.h): Include.
956 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
957 (sim_cia): Typedef to instruction_address.
959 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
961 * Makefile.in (interp.o): Rename generated file engine.c to
966 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
968 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
970 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
972 * gencode.c (build_instruction): For "FPSQRT", output correct
973 number of arguments to Recip.
975 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
977 * Makefile.in (interp.o): Depends on sim-main.h
979 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
981 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
982 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
983 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
984 STATE, DSSTATE): Define
985 (GPR, FGRIDX, ..): Define.
987 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
988 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
989 (GPR, FGRIDX, ...): Delete macros.
991 * interp.c: Update names to match defines from sim-main.h
993 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
995 * interp.c (sim_monitor): Add SD argument.
996 (sim_warning): Delete. Replace calls with calls to
998 (sim_error): Delete. Replace calls with sim_io_error.
999 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1000 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1001 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1003 (mips_size): Rename from sim_size. Add SD argument.
1005 * interp.c (simulator): Delete global variable.
1006 (callback): Delete global variable.
1007 (mips_option_handler, sim_open, sim_write, sim_read,
1008 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1009 sim_size,sim_monitor): Use sim_io_* not callback->*.
1010 (sim_open): ZALLOC simulator struct.
1011 (PROFILE): Do not define.
1013 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1015 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1016 support.h with corresponding code.
1018 * sim-main.h (word64, uword64), support.h: Move definition to
1020 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1023 * Makefile.in: Update dependencies
1024 * interp.c: Do not include.
1026 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1028 * interp.c (address_translation, load_memory, store_memory,
1029 cache_op): Rename to from AddressTranslation et.al., make global,
1032 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1035 * interp.c (SignalException): Rename to signal_exception, make
1038 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1040 * sim-main.h (SignalException, SignalExceptionInterrupt,
1041 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1042 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1043 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1046 * interp.c, support.h: Use.
1048 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1050 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1051 to value_fpr / store_fpr. Add SD argument.
1052 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1053 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1055 * sim-main.h (ValueFPR, StoreFPR): Define.
1057 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1059 * interp.c (sim_engine_run): Check consistency between configure
1060 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1063 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1064 (mips_fpu): Configure WITH_FLOATING_POINT.
1065 (mips_endian): Configure WITH_TARGET_ENDIAN.
1066 * configure: Update.
1068 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1070 * configure: Regenerated to track ../common/aclocal.m4 changes.
1072 start-sanitize-r5900
1073 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1075 * interp.c (MAX_REG): Allow up-to 128 registers.
1076 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1077 (REGISTER_SA): Ditto.
1078 (sim_open): Initialize register_widths for r5900 specific
1080 (sim_fetch_register, sim_store_register): Check for request of
1081 r5900 specific SA register. Check for request for hi 64 bits of
1082 r5900 specific registers.
1085 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1087 * configure: Regenerated.
1089 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1091 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1093 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1095 * gencode.c (print_igen_insn_models): Assume certain architectures
1096 include all mips* instructions.
1097 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1100 * Makefile.in (tmp.igen): Add target. Generate igen input from
1103 * gencode.c (FEATURE_IGEN): Define.
1104 (main): Add --igen option. Generate output in igen format.
1105 (process_instructions): Format output according to igen option.
1106 (print_igen_insn_format): New function.
1107 (print_igen_insn_models): New function.
1108 (process_instructions): Only issue warnings and ignore
1109 instructions when no FEATURE_IGEN.
1111 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1113 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1116 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1118 * configure: Regenerated to track ../common/aclocal.m4 changes.
1120 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1122 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1123 SIM_RESERVED_BITS): Delete, moved to common.
1124 (SIM_EXTRA_CFLAGS): Update.
1126 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1128 * configure.in: Configure non-strict memory alignment.
1129 * configure: Regenerated to track ../common/aclocal.m4 changes.
1131 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1133 * configure: Regenerated to track ../common/aclocal.m4 changes.
1135 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1137 * gencode.c (SDBBP,DERET): Added (3900) insns.
1138 (RFE): Turn on for 3900.
1139 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1140 (dsstate): Made global.
1141 (SUBTARGET_R3900): Added.
1142 (CANCELDELAYSLOT): New.
1143 (SignalException): Ignore SystemCall rather than ignore and
1144 terminate. Add DebugBreakPoint handling.
1145 (decode_coproc): New insns RFE, DERET; and new registers Debug
1146 and DEPC protected by SUBTARGET_R3900.
1147 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1149 * Makefile.in,configure.in: Add mips subtarget option.
1150 * configure: Update.
1152 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1154 * gencode.c: Add r3900 (tx39).
1157 * gencode.c: Fix some configuration problems by improving
1158 the relationship between tx19 and tx39.
1161 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1163 * gencode.c (build_instruction): Don't need to subtract 4 for
1166 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1168 * interp.c: Correct some HASFPU problems.
1170 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1172 * configure: Regenerated to track ../common/aclocal.m4 changes.
1174 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1176 * interp.c (mips_options): Fix samples option short form, should
1179 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1181 * interp.c (sim_info): Enable info code. Was just returning.
1183 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1185 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1188 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1190 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1192 (build_instruction): Ditto for LL.
1195 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1197 * mips/configure.in, mips/gencode: Add tx19/r1900.
1200 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1202 * configure: Regenerated to track ../common/aclocal.m4 changes.
1204 start-sanitize-r5900
1205 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1207 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1208 for overflow due to ABS of MININT, set result to MAXINT.
1209 (build_instruction): For "psrlvw", signextend bit 31.
1212 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1214 * configure: Regenerated to track ../common/aclocal.m4 changes.
1217 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1219 * interp.c (sim_open): Add call to sim_analyze_program, update
1222 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1224 * interp.c (sim_kill): Delete.
1225 (sim_create_inferior): Add ABFD argument. Set PC from same.
1226 (sim_load): Move code initializing trap handlers from here.
1227 (sim_open): To here.
1228 (sim_load): Delete, use sim-hload.c.
1230 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1232 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1234 * configure: Regenerated to track ../common/aclocal.m4 changes.
1237 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1239 * interp.c (sim_open): Add ABFD argument.
1240 (sim_load): Move call to sim_config from here.
1241 (sim_open): To here. Check return status.
1243 start-sanitize-r5900
1244 * gencode.c (build_instruction): Do not define x8000000000000000,
1245 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1248 start-sanitize-r5900
1249 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1251 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1252 "pdivuw" check for overflow due to signed divide by -1.
1255 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1257 * gencode.c (build_instruction): Two arg MADD should
1258 not assign result to $0.
1260 start-sanitize-r5900
1261 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1263 * gencode.c (build_instruction): For "ppac5" use unsigned
1264 arrithmetic so that the sign bit doesn't smear when right shifted.
1265 (build_instruction): For "pdiv" perform sign extension when
1266 storing results in HI and LO.
1267 (build_instructions): For "pdiv" and "pdivbw" check for
1269 (build_instruction): For "pmfhl.slw" update hi part of dest
1270 register as well as low part.
1271 (build_instruction): For "pmfhl" portably handle long long values.
1272 (build_instruction): For "pmfhl.sh" correctly negative values.
1273 Store half words 2 and three in the correct place.
1274 (build_instruction): For "psllvw", sign extend value after shift.
1277 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1279 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1280 * sim/mips/configure.in: Regenerate.
1282 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1284 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1285 signed8, unsigned8 et.al. types.
1287 start-sanitize-r5900
1288 * gencode.c (build_instruction): For PMULTU* do not sign extend
1289 registers. Make generated code easier to debug.
1292 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1293 hosts when selecting subreg.
1295 start-sanitize-r5900
1296 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1298 * gencode.c (type_for_data_len): For 32bit operations concerned
1299 with overflow, perform op using 64bits.
1300 (build_instruction): For PADD, always compute operation using type
1301 returned by type_for_data_len.
1302 (build_instruction): For PSUBU, when overflow, saturate to zero as
1306 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1308 start-sanitize-r5900
1309 * gencode.c (build_instruction): Handle "pext5" according to
1310 version 1.95 of the r5900 ISA.
1312 * gencode.c (build_instruction): Handle "ppac5" according to
1313 version 1.95 of the r5900 ISA.
1316 * interp.c (sim_engine_run): Reset the ZERO register to zero
1317 regardless of FEATURE_WARN_ZERO.
1318 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1320 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1322 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1323 (SignalException): For BreakPoints ignore any mode bits and just
1325 (SignalException): Always set the CAUSE register.
1327 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1329 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1330 exception has been taken.
1332 * interp.c: Implement the ERET and mt/f sr instructions.
1334 start-sanitize-r5900
1335 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1337 * gencode.c (build_instruction): For paddu, extract unsigned
1340 * gencode.c (build_instruction): Saturate padds instead of padd
1344 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1346 * interp.c (SignalException): Don't bother restarting an
1349 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1351 * interp.c (SignalException): Really take an interrupt.
1352 (interrupt_event): Only deliver interrupts when enabled.
1354 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1356 * interp.c (sim_info): Only print info when verbose.
1357 (sim_info) Use sim_io_printf for output.
1359 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1361 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1364 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1366 * interp.c (sim_do_command): Check for common commands if a
1367 simulator specific command fails.
1369 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1371 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1372 and simBE when DEBUG is defined.
1374 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1376 * interp.c (interrupt_event): New function. Pass exception event
1377 onto exception handler.
1379 * configure.in: Check for stdlib.h.
1380 * configure: Regenerate.
1382 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1383 variable declaration.
1384 (build_instruction): Initialize memval1.
1385 (build_instruction): Add UNUSED attribute to byte, bigend,
1387 (build_operands): Ditto.
1389 * interp.c: Fix GCC warnings.
1390 (sim_get_quit_code): Delete.
1392 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1393 * Makefile.in: Ditto.
1394 * configure: Re-generate.
1396 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1398 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1400 * interp.c (mips_option_handler): New function parse argumes using
1402 (myname): Replace with STATE_MY_NAME.
1403 (sim_open): Delete check for host endianness - performed by
1405 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1406 (sim_open): Move much of the initialization from here.
1407 (sim_load): To here. After the image has been loaded and
1409 (sim_open): Move ColdReset from here.
1410 (sim_create_inferior): To here.
1411 (sim_open): Make FP check less dependant on host endianness.
1413 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1415 * interp.c (sim_set_callbacks): Delete.
1417 * interp.c (membank, membank_base, membank_size): Replace with
1418 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1419 (sim_open): Remove call to callback->init. gdb/run do this.
1423 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1425 * interp.c (big_endian_p): Delete, replaced by
1426 current_target_byte_order.
1428 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1430 * interp.c (host_read_long, host_read_word, host_swap_word,
1431 host_swap_long): Delete. Using common sim-endian.
1432 (sim_fetch_register, sim_store_register): Use H2T.
1433 (pipeline_ticks): Delete. Handled by sim-events.
1435 (sim_engine_run): Update.
1437 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1439 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1441 (SignalException): To here. Signal using sim_engine_halt.
1442 (sim_stop_reason): Delete, moved to common.
1444 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1446 * interp.c (sim_open): Add callback argument.
1447 (sim_set_callbacks): Delete SIM_DESC argument.
1450 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1452 * Makefile.in (SIM_OBJS): Add common modules.
1454 * interp.c (sim_set_callbacks): Also set SD callback.
1455 (set_endianness, xfer_*, swap_*): Delete.
1456 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1457 Change to functions using sim-endian macros.
1458 (control_c, sim_stop): Delete, use common version.
1459 (simulate): Convert into.
1460 (sim_engine_run): This function.
1461 (sim_resume): Delete.
1463 * interp.c (simulation): New variable - the simulator object.
1464 (sim_kind): Delete global - merged into simulation.
1465 (sim_load): Cleanup. Move PC assignment from here.
1466 (sim_create_inferior): To here.
1468 * sim-main.h: New file.
1469 * interp.c (sim-main.h): Include.
1471 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1473 * configure: Regenerated to track ../common/aclocal.m4 changes.
1475 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1477 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1479 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1481 * gencode.c (build_instruction): DIV instructions: check
1482 for division by zero and integer overflow before using
1483 host's division operation.
1485 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1487 * Makefile.in (SIM_OBJS): Add sim-load.o.
1488 * interp.c: #include bfd.h.
1489 (target_byte_order): Delete.
1490 (sim_kind, myname, big_endian_p): New static locals.
1491 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1492 after argument parsing. Recognize -E arg, set endianness accordingly.
1493 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1494 load file into simulator. Set PC from bfd.
1495 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1496 (set_endianness): Use big_endian_p instead of target_byte_order.
1498 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1500 * interp.c (sim_size): Delete prototype - conflicts with
1501 definition in remote-sim.h. Correct definition.
1503 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1505 * configure: Regenerated to track ../common/aclocal.m4 changes.
1508 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1510 * interp.c (sim_open): New arg `kind'.
1512 * configure: Regenerated to track ../common/aclocal.m4 changes.
1514 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1516 * configure: Regenerated to track ../common/aclocal.m4 changes.
1518 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1520 * interp.c (sim_open): Set optind to 0 before calling getopt.
1522 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1524 * configure: Regenerated to track ../common/aclocal.m4 changes.
1526 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1528 * interp.c : Replace uses of pr_addr with pr_uword64
1529 where the bit length is always 64 independent of SIM_ADDR.
1530 (pr_uword64) : added.
1532 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1534 * configure: Re-generate.
1536 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1538 * configure: Regenerate to track ../common/aclocal.m4 changes.
1540 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1542 * interp.c (sim_open): New SIM_DESC result. Argument is now
1544 (other sim_*): New SIM_DESC argument.
1546 start-sanitize-r5900
1547 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1549 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1550 Change values to avoid overloading DOUBLEWORD which is tested
1552 * gencode.c: reinstate "offending code".
1555 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1557 * interp.c: Fix printing of addresses for non-64-bit targets.
1558 (pr_addr): Add function to print address based on size.
1559 start-sanitize-r5900
1560 * gencode.c: #ifdef out offending code until a permanent fix
1561 can be added. Code is causing build errors for non-5900 mips targets.
1564 start-sanitize-r5900
1565 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1567 * gencode.c (process_instructions): Correct test for ISA dependent
1568 architecture bits in isa field of MIPS_DECODE.
1571 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1573 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1575 start-sanitize-r5900
1576 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
1578 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1582 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1584 * gencode.c (build_mips16_operands): Correct computation of base
1585 address for extended PC relative instruction.
1587 start-sanitize-r5900
1588 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
1590 * Makefile.in, configure, configure.in, gencode.c,
1591 interp.c, support.h: add r5900.
1594 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1596 * interp.c (mips16_entry): Add support for floating point cases.
1597 (SignalException): Pass floating point cases to mips16_entry.
1598 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1600 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1602 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1603 and then set the state to fmt_uninterpreted.
1604 (COP_SW): Temporarily set the state to fmt_word while calling
1607 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1609 * gencode.c (build_instruction): The high order may be set in the
1610 comparison flags at any ISA level, not just ISA 4.
1612 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1614 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1615 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1616 * configure.in: sinclude ../common/aclocal.m4.
1617 * configure: Regenerated.
1619 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1621 * configure: Rebuild after change to aclocal.m4.
1623 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1625 * configure configure.in Makefile.in: Update to new configure
1626 scheme which is more compatible with WinGDB builds.
1627 * configure.in: Improve comment on how to run autoconf.
1628 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1629 * Makefile.in: Use autoconf substitution to install common
1632 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1634 * gencode.c (build_instruction): Use BigEndianCPU instead of
1637 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1639 * interp.c (sim_monitor): Make output to stdout visible in
1640 wingdb's I/O log window.
1642 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1644 * support.h: Undo previous change to SIGTRAP
1647 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1649 * interp.c (store_word, load_word): New static functions.
1650 (mips16_entry): New static function.
1651 (SignalException): Look for mips16 entry and exit instructions.
1652 (simulate): Use the correct index when setting fpr_state after
1653 doing a pending move.
1655 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1657 * interp.c: Fix byte-swapping code throughout to work on
1658 both little- and big-endian hosts.
1660 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1662 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1663 with gdb/config/i386/xm-windows.h.
1665 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1667 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1668 that messes up arithmetic shifts.
1670 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1672 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1673 SIGTRAP and SIGQUIT for _WIN32.
1675 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1677 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1678 force a 64 bit multiplication.
1679 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1680 destination register is 0, since that is the default mips16 nop
1683 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1685 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1686 (build_endian_shift): Don't check proc64.
1687 (build_instruction): Always set memval to uword64. Cast op2 to
1688 uword64 when shifting it left in memory instructions. Always use
1689 the same code for stores--don't special case proc64.
1691 * gencode.c (build_mips16_operands): Fix base PC value for PC
1693 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1695 * interp.c (simJALDELAYSLOT): Define.
1696 (JALDELAYSLOT): Define.
1697 (INDELAYSLOT, INJALDELAYSLOT): Define.
1698 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1700 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1702 * interp.c (sim_open): add flush_cache as a PMON routine
1703 (sim_monitor): handle flush_cache by ignoring it
1705 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1707 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1709 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1710 (BigEndianMem): Rename to ByteSwapMem and change sense.
1711 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1712 BigEndianMem references to !ByteSwapMem.
1713 (set_endianness): New function, with prototype.
1714 (sim_open): Call set_endianness.
1715 (sim_info): Use simBE instead of BigEndianMem.
1716 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1717 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1718 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1719 ifdefs, keeping the prototype declaration.
1720 (swap_word): Rewrite correctly.
1721 (ColdReset): Delete references to CONFIG. Delete endianness related
1722 code; moved to set_endianness.
1724 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1726 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1727 * interp.c (CHECKHILO): Define away.
1728 (simSIGINT): New macro.
1729 (membank_size): Increase from 1MB to 2MB.
1730 (control_c): New function.
1731 (sim_resume): Rename parameter signal to signal_number. Add local
1732 variable prev. Call signal before and after simulate.
1733 (sim_stop_reason): Add simSIGINT support.
1734 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1736 (sim_warning): Delete call to SignalException. Do call printf_filtered
1738 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1739 a call to sim_warning.
1741 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1743 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1744 16 bit instructions.
1746 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1748 Add support for mips16 (16 bit MIPS implementation):
1749 * gencode.c (inst_type): Add mips16 instruction encoding types.
1750 (GETDATASIZEINSN): Define.
1751 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1752 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1754 (MIPS16_DECODE): New table, for mips16 instructions.
1755 (bitmap_val): New static function.
1756 (struct mips16_op): Define.
1757 (mips16_op_table): New table, for mips16 operands.
1758 (build_mips16_operands): New static function.
1759 (process_instructions): If PC is odd, decode a mips16
1760 instruction. Break out instruction handling into new
1761 build_instruction function.
1762 (build_instruction): New static function, broken out of
1763 process_instructions. Check modifiers rather than flags for SHIFT
1764 bit count and m[ft]{hi,lo} direction.
1765 (usage): Pass program name to fprintf.
1766 (main): Remove unused variable this_option_optind. Change
1767 ``*loptarg++'' to ``loptarg++''.
1768 (my_strtoul): Parenthesize && within ||.
1769 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1770 (simulate): If PC is odd, fetch a 16 bit instruction, and
1771 increment PC by 2 rather than 4.
1772 * configure.in: Add case for mips16*-*-*.
1773 * configure: Rebuild.
1775 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1777 * interp.c: Allow -t to enable tracing in standalone simulator.
1778 Fix garbage output in trace file and error messages.
1780 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1782 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1783 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1784 * configure.in: Simplify using macros in ../common/aclocal.m4.
1785 * configure: Regenerated.
1786 * tconfig.in: New file.
1788 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1790 * interp.c: Fix bugs in 64-bit port.
1791 Use ansi function declarations for msvc compiler.
1792 Initialize and test file pointer in trace code.
1793 Prevent duplicate definition of LAST_EMED_REGNUM.
1795 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1797 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1799 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1801 * interp.c (SignalException): Check for explicit terminating
1803 * gencode.c: Pass instruction value through SignalException()
1804 calls for Trap, Breakpoint and Syscall.
1806 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1808 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1809 only used on those hosts that provide it.
1810 * configure.in: Add sqrt() to list of functions to be checked for.
1811 * config.in: Re-generated.
1812 * configure: Re-generated.
1814 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1816 * gencode.c (process_instructions): Call build_endian_shift when
1817 expanding STORE RIGHT, to fix swr.
1818 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1819 clear the high bits.
1820 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1821 Fix float to int conversions to produce signed values.
1823 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1825 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1826 (process_instructions): Correct handling of nor instruction.
1827 Correct shift count for 32 bit shift instructions. Correct sign
1828 extension for arithmetic shifts to not shift the number of bits in
1829 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1830 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1832 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1833 It's OK to have a mult follow a mult. What's not OK is to have a
1834 mult follow an mfhi.
1835 (Convert): Comment out incorrect rounding code.
1837 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1839 * interp.c (sim_monitor): Improved monitor printf
1840 simulation. Tidied up simulator warnings, and added "--log" option
1841 for directing warning message output.
1842 * gencode.c: Use sim_warning() rather than WARNING macro.
1844 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
1846 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1847 getopt1.o, rather than on gencode.c. Link objects together.
1848 Don't link against -liberty.
1849 (gencode.o, getopt.o, getopt1.o): New targets.
1850 * gencode.c: Include <ctype.h> and "ansidecl.h".
1851 (AND): Undefine after including "ansidecl.h".
1852 (ULONG_MAX): Define if not defined.
1853 (OP_*): Don't define macros; now defined in opcode/mips.h.
1854 (main): Call my_strtoul rather than strtoul.
1855 (my_strtoul): New static function.
1857 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
1859 * gencode.c (process_instructions): Generate word64 and uword64
1860 instead of `long long' and `unsigned long long' data types.
1861 * interp.c: #include sysdep.h to get signals, and define default
1863 * (Convert): Work around for Visual-C++ compiler bug with type
1865 * support.h: Make things compile under Visual-C++ by using
1866 __int64 instead of `long long'. Change many refs to long long
1867 into word64/uword64 typedefs.
1869 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
1871 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
1872 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
1874 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
1875 (AC_PROG_INSTALL): Added.
1876 (AC_PROG_CC): Moved to before configure.host call.
1877 * configure: Rebuilt.
1879 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
1881 * configure.in: Define @SIMCONF@ depending on mips target.
1882 * configure: Rebuild.
1883 * Makefile.in (run): Add @SIMCONF@ to control simulator
1885 * gencode.c: Change LOADDRMASK to 64bit memory model only.
1886 * interp.c: Remove some debugging, provide more detailed error
1887 messages, update memory accesses to use LOADDRMASK.
1889 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
1891 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
1892 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
1894 * configure: Rebuild.
1895 * config.in: New file, generated by autoheader.
1896 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
1897 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
1898 HAVE_ANINT and HAVE_AINT, as appropriate.
1899 * Makefile.in (run): Use @LIBS@ rather than -lm.
1900 (interp.o): Depend upon config.h.
1901 (Makefile): Just rebuild Makefile.
1902 (clean): Remove stamp-h.
1903 (mostlyclean): Make the same as clean, not as distclean.
1904 (config.h, stamp-h): New targets.
1906 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1908 * interp.c (ColdReset): Fix boolean test. Make all simulator
1911 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
1913 * interp.c (xfer_direct_word, xfer_direct_long,
1914 swap_direct_word, swap_direct_long, xfer_big_word,
1915 xfer_big_long, xfer_little_word, xfer_little_long,
1916 swap_word,swap_long): Added.
1917 * interp.c (ColdReset): Provide function indirection to
1918 host<->simulated_target transfer routines.
1919 * interp.c (sim_store_register, sim_fetch_register): Updated to
1920 make use of indirected transfer routines.
1922 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
1924 * gencode.c (process_instructions): Ensure FP ABS instruction
1926 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
1927 system call support.
1929 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
1931 * interp.c (sim_do_command): Complain if callback structure not
1934 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
1936 * interp.c (Convert): Provide round-to-nearest and round-to-zero
1937 support for Sun hosts.
1938 * Makefile.in (gencode): Ensure the host compiler and libraries
1939 used for cross-hosted build.
1941 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
1943 * interp.c, gencode.c: Some more (TODO) tidying.
1945 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
1947 * gencode.c, interp.c: Replaced explicit long long references with
1948 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
1949 * support.h (SET64LO, SET64HI): Macros added.
1951 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
1953 * configure: Regenerate with autoconf 2.7.
1955 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
1957 * interp.c (LoadMemory): Enclose text following #endif in /* */.
1958 * support.h: Remove superfluous "1" from #if.
1959 * support.h (CHECKSIM): Remove stray 'a' at end of line.
1961 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
1963 * interp.c (StoreFPR): Control UndefinedResult() call on
1964 WARN_RESULT manifest.
1966 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
1968 * gencode.c: Tidied instruction decoding, and added FP instruction
1971 * interp.c: Added dineroIII, and BSD profiling support. Also
1972 run-time FP handling.
1974 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
1976 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
1977 gencode.c, interp.c, support.h: created.