1 2002-06-03 Chris Demetriou <cgd@broadcom.com>
3 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
5 2002-06-02 Chris Demetriou <cgd@broadcom.com>
6 Ed Satterthwaite <ehs@broadcom.com>
8 * mips.igen (mdmx): New (pseudo-)model.
9 * mdmx.c, mdmx.igen: New files.
10 * Makefile.in (SIM_OBJS): Add mdmx.o.
11 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
13 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
14 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
15 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
16 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
17 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
18 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
19 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
20 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
21 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
22 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
23 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
24 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
25 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
26 (qh_fmtsel): New macros.
27 (_sim_cpu): New member "acc".
28 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
29 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
31 2002-05-01 Chris Demetriou <cgd@broadcom.com>
33 * interp.c: Use 'deprecated' rather than 'depreciated.'
34 * sim-main.h: Likewise.
36 2002-05-01 Chris Demetriou <cgd@broadcom.com>
38 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
39 which wouldn't compile anyway.
40 * sim-main.h (unpredictable_action): New function prototype.
41 (Unpredictable): Define to call igen function unpredictable().
42 (NotWordValue): New macro to call igen function not_word_value().
43 (UndefinedResult): Remove.
44 * interp.c (undefined_result): Remove.
45 (unpredictable_action): New function.
46 * mips.igen (not_word_value, unpredictable): New functions.
47 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
48 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
49 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
50 NotWordValue() to check for unpredictable inputs, then
51 Unpredictable() to handle them.
53 2002-02-24 Chris Demetriou <cgd@broadcom.com>
55 * mips.igen: Fix formatting of calls to Unpredictable().
57 2002-04-20 Andrew Cagney <ac131313@redhat.com>
59 * interp.c (sim_open): Revert previous change.
61 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
63 * interp.c (sim_open): Disable chunk of code that wrote code in
66 2002-03-19 Chris Demetriou <cgd@broadcom.com>
68 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
69 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
72 2002-03-19 Chris Demetriou <cgd@broadcom.com>
74 * cp1.c: Fix many formatting issues.
76 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
78 * cp1.c (fpu_format_name): New function to replace...
79 (DOFMT): This. Delete, and update all callers.
80 (fpu_rounding_mode_name): New function to replace...
81 (RMMODE): This. Delete, and update all callers.
83 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
85 * interp.c: Move FPU support routines from here to...
86 * cp1.c: Here. New file.
87 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
90 2002-03-12 Chris Demetriou <cgd@broadcom.com>
92 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
93 * mips.igen (mips32, mips64): New models, add to all instructions
94 and functions as appropriate.
95 (loadstore_ea, check_u64): New variant for model mips64.
96 (check_fmt_p): New variant for models mipsV and mips64, remove
97 mipsV model marking fro other variant.
100 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
101 for mips32 and mips64.
102 (DCLO, DCLZ): New instructions for mips64.
104 2002-03-07 Chris Demetriou <cgd@broadcom.com>
106 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
107 immediate or code as a hex value with the "%#lx" format.
108 (ANDI): Likewise, and fix printed instruction name.
110 2002-03-05 Chris Demetriou <cgd@broadcom.com>
112 * sim-main.h (UndefinedResult, Unpredictable): New macros
113 which currently do nothing.
115 2002-03-05 Chris Demetriou <cgd@broadcom.com>
117 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
118 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
119 (status_CU3): New definitions.
121 * sim-main.h (ExceptionCause): Add new values for MIPS32
122 and MIPS64: MDMX, MCheck, CacheErr. Update comments
123 for DebugBreakPoint and NMIReset to note their status in
125 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
126 (SignalExceptionCacheErr): New exception macros.
128 2002-03-05 Chris Demetriou <cgd@broadcom.com>
130 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
131 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
133 (SignalExceptionCoProcessorUnusable): Take as argument the
134 unusable coprocessor number.
136 2002-03-05 Chris Demetriou <cgd@broadcom.com>
138 * mips.igen: Fix formatting of all SignalException calls.
140 2002-03-05 Chris Demetriou <cgd@broadcom.com>
142 * sim-main.h (SIGNEXTEND): Remove.
144 2002-03-04 Chris Demetriou <cgd@broadcom.com>
146 * mips.igen: Remove gencode comment from top of file, fix
147 spelling in another comment.
149 2002-03-04 Chris Demetriou <cgd@broadcom.com>
151 * mips.igen (check_fmt, check_fmt_p): New functions to check
152 whether specific floating point formats are usable.
153 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
154 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
155 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
156 Use the new functions.
157 (do_c_cond_fmt): Remove format checks...
158 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
160 2002-03-03 Chris Demetriou <cgd@broadcom.com>
162 * mips.igen: Fix formatting of check_fpu calls.
164 2002-03-03 Chris Demetriou <cgd@broadcom.com>
166 * mips.igen (FLOOR.L.fmt): Store correct destination register.
168 2002-03-03 Chris Demetriou <cgd@broadcom.com>
170 * mips.igen: Remove whitespace at end of lines.
172 2002-03-02 Chris Demetriou <cgd@broadcom.com>
174 * mips.igen (loadstore_ea): New function to do effective
175 address calculations.
176 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
177 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
178 CACHE): Use loadstore_ea to do effective address computations.
180 2002-03-02 Chris Demetriou <cgd@broadcom.com>
182 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
183 * mips.igen (LL, CxC1, MxC1): Likewise.
185 2002-03-02 Chris Demetriou <cgd@broadcom.com>
187 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
188 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
189 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
190 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
191 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
192 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
193 Don't split opcode fields by hand, use the opcode field values
196 2002-03-01 Chris Demetriou <cgd@broadcom.com>
198 * mips.igen (do_divu): Fix spacing.
200 * mips.igen (do_dsllv): Move to be right before DSLLV,
201 to match the rest of the do_<shift> functions.
203 2002-03-01 Chris Demetriou <cgd@broadcom.com>
205 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
206 DSRL32, do_dsrlv): Trace inputs and results.
208 2002-03-01 Chris Demetriou <cgd@broadcom.com>
210 * mips.igen (CACHE): Provide instruction-printing string.
212 * interp.c (signal_exception): Comment tokens after #endif.
214 2002-02-28 Chris Demetriou <cgd@broadcom.com>
216 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
217 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
218 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
219 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
220 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
221 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
222 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
223 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
225 2002-02-28 Chris Demetriou <cgd@broadcom.com>
227 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
228 instruction-printing string.
229 (LWU): Use '64' as the filter flag.
231 2002-02-28 Chris Demetriou <cgd@broadcom.com>
233 * mips.igen (SDXC1): Fix instruction-printing string.
235 2002-02-28 Chris Demetriou <cgd@broadcom.com>
237 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
240 2002-02-27 Chris Demetriou <cgd@broadcom.com>
242 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
245 2002-02-27 Chris Demetriou <cgd@broadcom.com>
247 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
248 add a comma) so that it more closely match the MIPS ISA
249 documentation opcode partitioning.
250 (PREF): Put useful names on opcode fields, and include
251 instruction-printing string.
253 2002-02-27 Chris Demetriou <cgd@broadcom.com>
255 * mips.igen (check_u64): New function which in the future will
256 check whether 64-bit instructions are usable and signal an
257 exception if not. Currently a no-op.
258 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
259 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
260 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
261 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
263 * mips.igen (check_fpu): New function which in the future will
264 check whether FPU instructions are usable and signal an exception
265 if not. Currently a no-op.
266 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
267 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
268 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
269 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
270 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
271 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
272 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
273 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
275 2002-02-27 Chris Demetriou <cgd@broadcom.com>
277 * mips.igen (do_load_left, do_load_right): Move to be immediately
279 (do_store_left, do_store_right): Move to be immediately following
282 2002-02-27 Chris Demetriou <cgd@broadcom.com>
284 * mips.igen (mipsV): New model name. Also, add it to
285 all instructions and functions where it is appropriate.
287 2002-02-18 Chris Demetriou <cgd@broadcom.com>
289 * mips.igen: For all functions and instructions, list model
290 names that support that instruction one per line.
292 2002-02-11 Chris Demetriou <cgd@broadcom.com>
294 * mips.igen: Add some additional comments about supported
295 models, and about which instructions go where.
296 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
297 order as is used in the rest of the file.
299 2002-02-11 Chris Demetriou <cgd@broadcom.com>
301 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
302 indicating that ALU32_END or ALU64_END are there to check
304 (DADD): Likewise, but also remove previous comment about
307 2002-02-10 Chris Demetriou <cgd@broadcom.com>
309 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
310 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
311 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
312 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
313 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
314 fields (i.e., add and move commas) so that they more closely
315 match the MIPS ISA documentation opcode partitioning.
317 2002-02-10 Chris Demetriou <cgd@broadcom.com>
319 * mips.igen (ADDI): Print immediate value.
321 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
322 (SLL): Print "nop" specially, and don't run the code
323 that does the shift for the "nop" case.
325 2001-11-17 Fred Fish <fnf@redhat.com>
327 * sim-main.h (float_operation): Move enum declaration outside
328 of _sim_cpu struct declaration.
330 2001-04-12 Jim Blandy <jimb@redhat.com>
332 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
333 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
335 * sim-main.h (COCIDX): Remove definition; this isn't supported by
336 PENDING_FILL, and you can get the intended effect gracefully by
337 calling PENDING_SCHED directly.
339 2001-02-23 Ben Elliston <bje@redhat.com>
341 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
342 already defined elsewhere.
344 2001-02-19 Ben Elliston <bje@redhat.com>
346 * sim-main.h (sim_monitor): Return an int.
347 * interp.c (sim_monitor): Add return values.
348 (signal_exception): Handle error conditions from sim_monitor.
350 2001-02-08 Ben Elliston <bje@redhat.com>
352 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
353 (store_memory): Likewise, pass cia to sim_core_write*.
355 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
357 On advice from Chris G. Demetriou <cgd@sibyte.com>:
358 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
360 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
362 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
363 * Makefile.in: Don't delete *.igen when cleaning directory.
365 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
367 * m16.igen (break): Call SignalException not sim_engine_halt.
369 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
372 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
374 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
376 * mips.igen (MxC1, DMxC1): Fix printf formatting.
378 2000-05-24 Michael Hayes <mhayes@cygnus.com>
380 * mips.igen (do_dmultx): Fix typo.
382 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
384 * configure: Regenerated to track ../common/aclocal.m4 changes.
386 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
388 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
390 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
392 * sim-main.h (GPR_CLEAR): Define macro.
394 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
396 * interp.c (decode_coproc): Output long using %lx and not %s.
398 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
400 * interp.c (sim_open): Sort & extend dummy memory regions for
401 --board=jmr3904 for eCos.
403 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
405 * configure: Regenerated.
407 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
409 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
410 calls, conditional on the simulator being in verbose mode.
412 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
414 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
415 cache don't get ReservedInstruction traps.
417 1999-11-29 Mark Salter <msalter@cygnus.com>
419 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
420 to clear status bits in sdisr register. This is how the hardware works.
422 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
423 being used by cygmon.
425 1999-11-11 Andrew Haley <aph@cygnus.com>
427 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
430 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
432 * mips.igen (MULT): Correct previous mis-applied patch.
434 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
436 * mips.igen (delayslot32): Handle sequence like
437 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
438 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
439 (MULT): Actually pass the third register...
441 1999-09-03 Mark Salter <msalter@cygnus.com>
443 * interp.c (sim_open): Added more memory aliases for additional
444 hardware being touched by cygmon on jmr3904 board.
446 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
448 * configure: Regenerated to track ../common/aclocal.m4 changes.
450 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
452 * interp.c (sim_store_register): Handle case where client - GDB -
453 specifies that a 4 byte register is 8 bytes in size.
454 (sim_fetch_register): Ditto.
456 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
458 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
459 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
460 (idt_monitor_base): Base address for IDT monitor traps.
461 (pmon_monitor_base): Ditto for PMON.
462 (lsipmon_monitor_base): Ditto for LSI PMON.
463 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
464 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
465 (sim_firmware_command): New function.
466 (mips_option_handler): Call it for OPTION_FIRMWARE.
467 (sim_open): Allocate memory for idt_monitor region. If "--board"
468 option was given, add no monitor by default. Add BREAK hooks only if
469 monitors are also there.
471 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
473 * interp.c (sim_monitor): Flush output before reading input.
475 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
477 * tconfig.in (SIM_HANDLES_LMA): Always define.
479 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
481 From Mark Salter <msalter@cygnus.com>:
482 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
483 (sim_open): Add setup for BSP board.
485 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
487 * mips.igen (MULT, MULTU): Add syntax for two operand version.
488 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
489 them as unimplemented.
491 1999-05-08 Felix Lee <flee@cygnus.com>
493 * configure: Regenerated to track ../common/aclocal.m4 changes.
495 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
497 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
499 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
501 * configure.in: Any mips64vr5*-*-* target should have
502 -DTARGET_ENABLE_FR=1.
503 (default_endian): Any mips64vr*el-*-* target should default to
505 * configure: Re-generate.
507 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
509 * mips.igen (ldl): Extend from _16_, not 32.
511 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
513 * interp.c (sim_store_register): Force registers written to by GDB
514 into an un-interpreted state.
516 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
518 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
519 CPU, start periodic background I/O polls.
520 (tx3904sio_poll): New function: periodic I/O poller.
522 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
524 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
526 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
528 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
531 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
533 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
534 (load_word): Call SIM_CORE_SIGNAL hook on error.
535 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
536 starting. For exception dispatching, pass PC instead of NULL_CIA.
537 (decode_coproc): Use COP0_BADVADDR to store faulting address.
538 * sim-main.h (COP0_BADVADDR): Define.
539 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
540 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
541 (_sim_cpu): Add exc_* fields to store register value snapshots.
542 * mips.igen (*): Replace memory-related SignalException* calls
543 with references to SIM_CORE_SIGNAL hook.
545 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
547 * sim-main.c (*): Minor warning cleanups.
549 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
551 * m16.igen (DADDIU5): Correct type-o.
553 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
555 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
558 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
560 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
562 (interp.o): Add dependency on itable.h
563 (oengine.c, gencode): Delete remaining references.
564 (BUILT_SRC_FROM_GEN): Clean up.
566 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
569 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
570 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
572 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
573 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
574 Drop the "64" qualifier to get the HACK generator working.
575 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
576 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
577 qualifier to get the hack generator working.
578 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
580 (DSLLV): Use do_dsllv.
583 (DSRLV): Use do_dsrlv.
584 (BC1): Move *vr4100 to get the HACK generator working.
585 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
586 get the HACK generator working.
587 (MACC) Rename to get the HACK generator working.
588 (DMACC,MACCS,DMACCS): Add the 64.
590 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
592 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
593 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
595 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
597 * mips/interp.c (DEBUG): Cleanups.
599 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
601 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
602 (tx3904sio_tickle): fflush after a stdout character output.
604 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
606 * interp.c (sim_close): Uninstall modules.
608 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
610 * sim-main.h, interp.c (sim_monitor): Change to global
613 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
615 * configure.in (vr4100): Only include vr4100 instructions in
617 * configure: Re-generate.
618 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
620 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
622 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
623 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
626 * configure.in (sim_default_gen, sim_use_gen): Replace with
628 (--enable-sim-igen): Delete config option. Always using IGEN.
629 * configure: Re-generate.
631 * Makefile.in (gencode): Kill, kill, kill.
634 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
636 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
637 bit mips16 igen simulator.
638 * configure: Re-generate.
640 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
641 as part of vr4100 ISA.
642 * vr.igen: Mark all instructions as 64 bit only.
644 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
646 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
649 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
651 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
652 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
653 * configure: Re-generate.
655 * m16.igen (BREAK): Define breakpoint instruction.
656 (JALX32): Mark instruction as mips16 and not r3900.
657 * mips.igen (C.cond.fmt): Fix typo in instruction format.
659 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
661 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
663 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
664 insn as a debug breakpoint.
666 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
668 (PENDING_SCHED): Clean up trace statement.
669 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
670 (PENDING_FILL): Delay write by only one cycle.
671 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
673 * sim-main.c (pending_tick): Clean up trace statements. Add trace
675 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
677 (pending_tick): Move incrementing of index to FOR statement.
678 (pending_tick): Only update PENDING_OUT after a write has occured.
680 * configure.in: Add explicit mips-lsi-* target. Use gencode to
682 * configure: Re-generate.
684 * interp.c (sim_engine_run OLD): Delete explicit call to
685 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
687 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
689 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
690 interrupt level number to match changed SignalExceptionInterrupt
693 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
695 * interp.c: #include "itable.h" if WITH_IGEN.
696 (get_insn_name): New function.
697 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
698 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
700 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
702 * configure: Rebuilt to inhale new common/aclocal.m4.
704 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
706 * dv-tx3904sio.c: Include sim-assert.h.
708 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
710 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
711 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
712 Reorganize target-specific sim-hardware checks.
713 * configure: rebuilt.
714 * interp.c (sim_open): For tx39 target boards, set
715 OPERATING_ENVIRONMENT, add tx3904sio devices.
716 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
717 ROM executables. Install dv-sockser into sim-modules list.
719 * dv-tx3904irc.c: Compiler warning clean-up.
720 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
721 frequent hw-trace messages.
723 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
725 * vr.igen (MulAcc): Identify as a vr4100 specific function.
727 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
729 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
732 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
733 * mips.igen: Define vr4100 model. Include vr.igen.
734 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
736 * mips.igen (check_mf_hilo): Correct check.
738 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
740 * sim-main.h (interrupt_event): Add prototype.
742 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
743 register_ptr, register_value.
744 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
746 * sim-main.h (tracefh): Make extern.
748 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
750 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
751 Reduce unnecessarily high timer event frequency.
752 * dv-tx3904cpu.c: Ditto for interrupt event.
754 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
756 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
758 (interrupt_event): Made non-static.
760 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
761 interchange of configuration values for external vs. internal
764 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
766 * mips.igen (BREAK): Moved code to here for
767 simulator-reserved break instructions.
768 * gencode.c (build_instruction): Ditto.
769 * interp.c (signal_exception): Code moved from here. Non-
770 reserved instructions now use exception vector, rather
772 * sim-main.h: Moved magic constants to here.
774 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
776 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
777 register upon non-zero interrupt event level, clear upon zero
779 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
780 by passing zero event value.
781 (*_io_{read,write}_buffer): Endianness fixes.
782 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
783 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
785 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
786 serial I/O and timer module at base address 0xFFFF0000.
788 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
790 * mips.igen (SWC1) : Correct the handling of ReverseEndian
793 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
795 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
799 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
801 * dv-tx3904tmr.c: New file - implements tx3904 timer.
802 * dv-tx3904{irc,cpu}.c: Mild reformatting.
803 * configure.in: Include tx3904tmr in hw_device list.
804 * configure: Rebuilt.
805 * interp.c (sim_open): Instantiate three timer instances.
806 Fix address typo of tx3904irc instance.
808 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
810 * interp.c (signal_exception): SystemCall exception now uses
811 the exception vector.
813 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
815 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
818 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
820 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
822 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
824 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
826 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
827 sim-main.h. Declare a struct hw_descriptor instead of struct
828 hw_device_descriptor.
830 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
832 * mips.igen (do_store_left, do_load_left): Compute nr of left and
833 right bits and then re-align left hand bytes to correct byte
834 lanes. Fix incorrect computation in do_store_left when loading
835 bytes from second word.
837 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
839 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
840 * interp.c (sim_open): Only create a device tree when HW is
843 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
844 * interp.c (signal_exception): Ditto.
846 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
848 * gencode.c: Mark BEGEZALL as LIKELY.
850 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
852 * sim-main.h (ALU32_END): Sign extend 32 bit results.
853 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
855 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
857 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
858 modules. Recognize TX39 target with "mips*tx39" pattern.
859 * configure: Rebuilt.
860 * sim-main.h (*): Added many macros defining bits in
861 TX39 control registers.
862 (SignalInterrupt): Send actual PC instead of NULL.
863 (SignalNMIReset): New exception type.
864 * interp.c (board): New variable for future use to identify
865 a particular board being simulated.
866 (mips_option_handler,mips_options): Added "--board" option.
867 (interrupt_event): Send actual PC.
868 (sim_open): Make memory layout conditional on board setting.
869 (signal_exception): Initial implementation of hardware interrupt
870 handling. Accept another break instruction variant for simulator
872 (decode_coproc): Implement RFE instruction for TX39.
873 (mips.igen): Decode RFE instruction as such.
874 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
875 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
876 bbegin to implement memory map.
877 * dv-tx3904cpu.c: New file.
878 * dv-tx3904irc.c: New file.
880 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
882 * mips.igen (check_mt_hilo): Create a separate r3900 version.
884 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
886 * tx.igen (madd,maddu): Replace calls to check_op_hilo
887 with calls to check_div_hilo.
889 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
891 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
892 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
893 Add special r3900 version of do_mult_hilo.
894 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
895 with calls to check_mult_hilo.
896 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
897 with calls to check_div_hilo.
899 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
901 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
902 Document a replacement.
904 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
906 * interp.c (sim_monitor): Make mon_printf work.
908 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
910 * sim-main.h (INSN_NAME): New arg `cpu'.
912 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
914 * configure: Regenerated to track ../common/aclocal.m4 changes.
916 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
918 * configure: Regenerated to track ../common/aclocal.m4 changes.
921 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
923 * acconfig.h: New file.
924 * configure.in: Reverted change of Apr 24; use sinclude again.
926 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
928 * configure: Regenerated to track ../common/aclocal.m4 changes.
931 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
933 * configure.in: Don't call sinclude.
935 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
937 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
939 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
941 * mips.igen (ERET): Implement.
943 * interp.c (decode_coproc): Return sign-extended EPC.
945 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
947 * interp.c (signal_exception): Do not ignore Trap.
948 (signal_exception): On TRAP, restart at exception address.
949 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
950 (signal_exception): Update.
951 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
952 so that TRAP instructions are caught.
954 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
956 * sim-main.h (struct hilo_access, struct hilo_history): Define,
957 contains HI/LO access history.
958 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
959 (HIACCESS, LOACCESS): Delete, replace with
960 (HIHISTORY, LOHISTORY): New macros.
961 (CHECKHILO): Delete all, moved to mips.igen
963 * gencode.c (build_instruction): Do not generate checks for
964 correct HI/LO register usage.
966 * interp.c (old_engine_run): Delete checks for correct HI/LO
969 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
970 check_mf_cycles): New functions.
971 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
972 do_divu, domultx, do_mult, do_multu): Use.
974 * tx.igen ("madd", "maddu"): Use.
976 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
978 * mips.igen (DSRAV): Use function do_dsrav.
979 (SRAV): Use new function do_srav.
981 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
982 (B): Sign extend 11 bit immediate.
983 (EXT-B*): Shift 16 bit immediate left by 1.
984 (ADDIU*): Don't sign extend immediate value.
986 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
988 * m16run.c (sim_engine_run): Restore CIA after handling an event.
990 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
993 * mips.igen (delayslot32, nullify_next_insn): New functions.
994 (m16.igen): Always include.
995 (do_*): Add more tracing.
997 * m16.igen (delayslot16): Add NIA argument, could be called by a
998 32 bit MIPS16 instruction.
1000 * interp.c (ifetch16): Move function from here.
1001 * sim-main.c (ifetch16): To here.
1003 * sim-main.c (ifetch16, ifetch32): Update to match current
1004 implementations of LH, LW.
1005 (signal_exception): Don't print out incorrect hex value of illegal
1008 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1010 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1013 * m16.igen: Implement MIPS16 instructions.
1015 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1016 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1017 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1018 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1019 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1020 bodies of corresponding code from 32 bit insn to these. Also used
1021 by MIPS16 versions of functions.
1023 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1024 (IMEM16): Drop NR argument from macro.
1026 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1028 * Makefile.in (SIM_OBJS): Add sim-main.o.
1030 * sim-main.h (address_translation, load_memory, store_memory,
1031 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1033 (pr_addr, pr_uword64): Declare.
1034 (sim-main.c): Include when H_REVEALS_MODULE_P.
1036 * interp.c (address_translation, load_memory, store_memory,
1037 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1039 * sim-main.c: To here. Fix compilation problems.
1041 * configure.in: Enable inlining.
1042 * configure: Re-config.
1044 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1046 * configure: Regenerated to track ../common/aclocal.m4 changes.
1048 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1050 * mips.igen: Include tx.igen.
1051 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1052 * tx.igen: New file, contains MADD and MADDU.
1054 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1055 the hardwired constant `7'.
1056 (store_memory): Ditto.
1057 (LOADDRMASK): Move definition to sim-main.h.
1059 mips.igen (MTC0): Enable for r3900.
1062 mips.igen (do_load_byte): Delete.
1063 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1064 do_store_right): New functions.
1065 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1067 configure.in: Let the tx39 use igen again.
1070 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1072 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1073 not an address sized quantity. Return zero for cache sizes.
1075 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1077 * mips.igen (r3900): r3900 does not support 64 bit integer
1080 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1082 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1084 * configure : Rebuild.
1086 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1088 * configure: Regenerated to track ../common/aclocal.m4 changes.
1090 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1092 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1094 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1096 * configure: Regenerated to track ../common/aclocal.m4 changes.
1097 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1099 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1101 * configure: Regenerated to track ../common/aclocal.m4 changes.
1103 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1105 * interp.c (Max, Min): Comment out functions. Not yet used.
1107 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1109 * configure: Regenerated to track ../common/aclocal.m4 changes.
1111 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1113 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1114 configurable settings for stand-alone simulator.
1116 * configure.in: Added X11 search, just in case.
1118 * configure: Regenerated.
1120 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1122 * interp.c (sim_write, sim_read, load_memory, store_memory):
1123 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1125 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1127 * sim-main.h (GETFCC): Return an unsigned value.
1129 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1131 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1132 (DADD): Result destination is RD not RT.
1134 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1136 * sim-main.h (HIACCESS, LOACCESS): Always define.
1138 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1140 * interp.c (sim_info): Delete.
1142 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1144 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1145 (mips_option_handler): New argument `cpu'.
1146 (sim_open): Update call to sim_add_option_table.
1148 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1150 * mips.igen (CxC1): Add tracing.
1152 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1154 * sim-main.h (Max, Min): Declare.
1156 * interp.c (Max, Min): New functions.
1158 * mips.igen (BC1): Add tracing.
1160 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1162 * interp.c Added memory map for stack in vr4100
1164 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1166 * interp.c (load_memory): Add missing "break"'s.
1168 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1170 * interp.c (sim_store_register, sim_fetch_register): Pass in
1171 length parameter. Return -1.
1173 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1175 * interp.c: Added hardware init hook, fixed warnings.
1177 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1179 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1181 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1183 * interp.c (ifetch16): New function.
1185 * sim-main.h (IMEM32): Rename IMEM.
1186 (IMEM16_IMMED): Define.
1188 (DELAY_SLOT): Update.
1190 * m16run.c (sim_engine_run): New file.
1192 * m16.igen: All instructions except LB.
1193 (LB): Call do_load_byte.
1194 * mips.igen (do_load_byte): New function.
1195 (LB): Call do_load_byte.
1197 * mips.igen: Move spec for insn bit size and high bit from here.
1198 * Makefile.in (tmp-igen, tmp-m16): To here.
1200 * m16.dc: New file, decode mips16 instructions.
1202 * Makefile.in (SIM_NO_ALL): Define.
1203 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1205 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1207 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1208 point unit to 32 bit registers.
1209 * configure: Re-generate.
1211 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1213 * configure.in (sim_use_gen): Make IGEN the default simulator
1214 generator for generic 32 and 64 bit mips targets.
1215 * configure: Re-generate.
1217 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1219 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1222 * interp.c (sim_fetch_register, sim_store_register): Read/write
1223 FGR from correct location.
1224 (sim_open): Set size of FGR's according to
1225 WITH_TARGET_FLOATING_POINT_BITSIZE.
1227 * sim-main.h (FGR): Store floating point registers in a separate
1230 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1232 * configure: Regenerated to track ../common/aclocal.m4 changes.
1234 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1236 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1238 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1240 * interp.c (pending_tick): New function. Deliver pending writes.
1242 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1243 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1244 it can handle mixed sized quantites and single bits.
1246 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1248 * interp.c (oengine.h): Do not include when building with IGEN.
1249 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1250 (sim_info): Ditto for PROCESSOR_64BIT.
1251 (sim_monitor): Replace ut_reg with unsigned_word.
1252 (*): Ditto for t_reg.
1253 (LOADDRMASK): Define.
1254 (sim_open): Remove defunct check that host FP is IEEE compliant,
1255 using software to emulate floating point.
1256 (value_fpr, ...): Always compile, was conditional on HASFPU.
1258 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1260 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1263 * interp.c (SD, CPU): Define.
1264 (mips_option_handler): Set flags in each CPU.
1265 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1266 (sim_close): Do not clear STATE, deleted anyway.
1267 (sim_write, sim_read): Assume CPU zero's vm should be used for
1269 (sim_create_inferior): Set the PC for all processors.
1270 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1272 (mips16_entry): Pass correct nr of args to store_word, load_word.
1273 (ColdReset): Cold reset all cpu's.
1274 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1275 (sim_monitor, load_memory, store_memory, signal_exception): Use
1276 `CPU' instead of STATE_CPU.
1279 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1282 * sim-main.h (signal_exception): Add sim_cpu arg.
1283 (SignalException*): Pass both SD and CPU to signal_exception.
1284 * interp.c (signal_exception): Update.
1286 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1288 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1289 address_translation): Ditto
1290 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1292 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1294 * configure: Regenerated to track ../common/aclocal.m4 changes.
1296 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1298 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1300 * mips.igen (model): Map processor names onto BFD name.
1302 * sim-main.h (CPU_CIA): Delete.
1303 (SET_CIA, GET_CIA): Define
1305 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1307 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1310 * configure.in (default_endian): Configure a big-endian simulator
1312 * configure: Re-generate.
1314 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1316 * configure: Regenerated to track ../common/aclocal.m4 changes.
1318 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1320 * interp.c (sim_monitor): Handle Densan monitor outbyte
1321 and inbyte functions.
1323 1997-12-29 Felix Lee <flee@cygnus.com>
1325 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1327 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1329 * Makefile.in (tmp-igen): Arrange for $zero to always be
1330 reset to zero after every instruction.
1332 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1334 * configure: Regenerated to track ../common/aclocal.m4 changes.
1337 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1339 * mips.igen (MSUB): Fix to work like MADD.
1340 * gencode.c (MSUB): Similarly.
1342 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1344 * configure: Regenerated to track ../common/aclocal.m4 changes.
1346 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1348 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1350 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1352 * sim-main.h (sim-fpu.h): Include.
1354 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1355 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1356 using host independant sim_fpu module.
1358 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1360 * interp.c (signal_exception): Report internal errors with SIGABRT
1363 * sim-main.h (C0_CONFIG): New register.
1364 (signal.h): No longer include.
1366 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1368 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1370 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1372 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1374 * mips.igen: Tag vr5000 instructions.
1375 (ANDI): Was missing mipsIV model, fix assembler syntax.
1376 (do_c_cond_fmt): New function.
1377 (C.cond.fmt): Handle mips I-III which do not support CC field
1379 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1380 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1382 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1383 vr5000 which saves LO in a GPR separatly.
1385 * configure.in (enable-sim-igen): For vr5000, select vr5000
1386 specific instructions.
1387 * configure: Re-generate.
1389 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1391 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1393 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1394 fmt_uninterpreted_64 bit cases to switch. Convert to
1397 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1399 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1400 as specified in IV3.2 spec.
1401 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1403 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1405 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1406 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1407 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1408 PENDING_FILL versions of instructions. Simplify.
1410 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1412 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1414 (MTHI, MFHI): Disable code checking HI-LO.
1416 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1418 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1420 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1422 * gencode.c (build_mips16_operands): Replace IPC with cia.
1424 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1425 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1427 (UndefinedResult): Replace function with macro/function
1429 (sim_engine_run): Don't save PC in IPC.
1431 * sim-main.h (IPC): Delete.
1434 * interp.c (signal_exception, store_word, load_word,
1435 address_translation, load_memory, store_memory, cache_op,
1436 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1437 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1438 current instruction address - cia - argument.
1439 (sim_read, sim_write): Call address_translation directly.
1440 (sim_engine_run): Rename variable vaddr to cia.
1441 (signal_exception): Pass cia to sim_monitor
1443 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1444 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1445 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1447 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1448 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1451 * interp.c (signal_exception): Pass restart address to
1454 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1455 idecode.o): Add dependency.
1457 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1459 (DELAY_SLOT): Update NIA not PC with branch address.
1460 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1462 * mips.igen: Use CIA not PC in branch calculations.
1463 (illegal): Call SignalException.
1464 (BEQ, ADDIU): Fix assembler.
1466 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1468 * m16.igen (JALX): Was missing.
1470 * configure.in (enable-sim-igen): New configuration option.
1471 * configure: Re-generate.
1473 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1475 * interp.c (load_memory, store_memory): Delete parameter RAW.
1476 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1477 bypassing {load,store}_memory.
1479 * sim-main.h (ByteSwapMem): Delete definition.
1481 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1483 * interp.c (sim_do_command, sim_commands): Delete mips specific
1484 commands. Handled by module sim-options.
1486 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1487 (WITH_MODULO_MEMORY): Define.
1489 * interp.c (sim_info): Delete code printing memory size.
1491 * interp.c (mips_size): Nee sim_size, delete function.
1493 (monitor, monitor_base, monitor_size): Delete global variables.
1494 (sim_open, sim_close): Delete code creating monitor and other
1495 memory regions. Use sim-memopts module, via sim_do_commandf, to
1496 manage memory regions.
1497 (load_memory, store_memory): Use sim-core for memory model.
1499 * interp.c (address_translation): Delete all memory map code
1500 except line forcing 32 bit addresses.
1502 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1504 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1507 * interp.c (logfh, logfile): Delete globals.
1508 (sim_open, sim_close): Delete code opening & closing log file.
1509 (mips_option_handler): Delete -l and -n options.
1510 (OPTION mips_options): Ditto.
1512 * interp.c (OPTION mips_options): Rename option trace to dinero.
1513 (mips_option_handler): Update.
1515 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1517 * interp.c (fetch_str): New function.
1518 (sim_monitor): Rewrite using sim_read & sim_write.
1519 (sim_open): Check magic number.
1520 (sim_open): Write monitor vectors into memory using sim_write.
1521 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1522 (sim_read, sim_write): Simplify - transfer data one byte at a
1524 (load_memory, store_memory): Clarify meaning of parameter RAW.
1526 * sim-main.h (isHOST): Defete definition.
1527 (isTARGET): Mark as depreciated.
1528 (address_translation): Delete parameter HOST.
1530 * interp.c (address_translation): Delete parameter HOST.
1532 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1536 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1537 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1539 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1541 * mips.igen: Add model filter field to records.
1543 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1545 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1547 interp.c (sim_engine_run): Do not compile function sim_engine_run
1548 when WITH_IGEN == 1.
1550 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1551 target architecture.
1553 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1554 igen. Replace with configuration variables sim_igen_flags /
1557 * m16.igen: New file. Copy mips16 insns here.
1558 * mips.igen: From here.
1560 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1562 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1564 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1566 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1568 * gencode.c (build_instruction): Follow sim_write's lead in using
1569 BigEndianMem instead of !ByteSwapMem.
1571 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1573 * configure.in (sim_gen): Dependent on target, select type of
1574 generator. Always select old style generator.
1576 configure: Re-generate.
1578 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1580 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1581 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1582 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1583 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1584 SIM_@sim_gen@_*, set by autoconf.
1586 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1588 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1590 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1591 CURRENT_FLOATING_POINT instead.
1593 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1594 (address_translation): Raise exception InstructionFetch when
1595 translation fails and isINSTRUCTION.
1597 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1598 sim_engine_run): Change type of of vaddr and paddr to
1600 (address_translation, prefetch, load_memory, store_memory,
1601 cache_op): Change type of vAddr and pAddr to address_word.
1603 * gencode.c (build_instruction): Change type of vaddr and paddr to
1606 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1608 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1609 macro to obtain result of ALU op.
1611 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1613 * interp.c (sim_info): Call profile_print.
1615 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1617 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1619 * sim-main.h (WITH_PROFILE): Do not define, defined in
1620 common/sim-config.h. Use sim-profile module.
1621 (simPROFILE): Delete defintion.
1623 * interp.c (PROFILE): Delete definition.
1624 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1625 (sim_close): Delete code writing profile histogram.
1626 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1628 (sim_engine_run): Delete code profiling the PC.
1630 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1634 * interp.c (sim_monitor): Make register pointers of type
1637 * sim-main.h: Make registers of type unsigned_word not
1640 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1642 * interp.c (sync_operation): Rename from SyncOperation, make
1643 global, add SD argument.
1644 (prefetch): Rename from Prefetch, make global, add SD argument.
1645 (decode_coproc): Make global.
1647 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1649 * gencode.c (build_instruction): Generate DecodeCoproc not
1650 decode_coproc calls.
1652 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1653 (SizeFGR): Move to sim-main.h
1654 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1655 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1656 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1658 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1659 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1660 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1661 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1662 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1663 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1665 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1667 (sim-alu.h): Include.
1668 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1669 (sim_cia): Typedef to instruction_address.
1671 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1673 * Makefile.in (interp.o): Rename generated file engine.c to
1678 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1680 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1682 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1684 * gencode.c (build_instruction): For "FPSQRT", output correct
1685 number of arguments to Recip.
1687 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1689 * Makefile.in (interp.o): Depends on sim-main.h
1691 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1693 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1694 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1695 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1696 STATE, DSSTATE): Define
1697 (GPR, FGRIDX, ..): Define.
1699 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1700 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1701 (GPR, FGRIDX, ...): Delete macros.
1703 * interp.c: Update names to match defines from sim-main.h
1705 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1707 * interp.c (sim_monitor): Add SD argument.
1708 (sim_warning): Delete. Replace calls with calls to
1710 (sim_error): Delete. Replace calls with sim_io_error.
1711 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1712 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1713 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1715 (mips_size): Rename from sim_size. Add SD argument.
1717 * interp.c (simulator): Delete global variable.
1718 (callback): Delete global variable.
1719 (mips_option_handler, sim_open, sim_write, sim_read,
1720 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1721 sim_size,sim_monitor): Use sim_io_* not callback->*.
1722 (sim_open): ZALLOC simulator struct.
1723 (PROFILE): Do not define.
1725 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1727 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1728 support.h with corresponding code.
1730 * sim-main.h (word64, uword64), support.h: Move definition to
1732 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1735 * Makefile.in: Update dependencies
1736 * interp.c: Do not include.
1738 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1740 * interp.c (address_translation, load_memory, store_memory,
1741 cache_op): Rename to from AddressTranslation et.al., make global,
1744 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1747 * interp.c (SignalException): Rename to signal_exception, make
1750 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1752 * sim-main.h (SignalException, SignalExceptionInterrupt,
1753 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1754 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1755 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1758 * interp.c, support.h: Use.
1760 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1762 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1763 to value_fpr / store_fpr. Add SD argument.
1764 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1765 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1767 * sim-main.h (ValueFPR, StoreFPR): Define.
1769 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1771 * interp.c (sim_engine_run): Check consistency between configure
1772 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1775 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1776 (mips_fpu): Configure WITH_FLOATING_POINT.
1777 (mips_endian): Configure WITH_TARGET_ENDIAN.
1778 * configure: Update.
1780 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1782 * configure: Regenerated to track ../common/aclocal.m4 changes.
1784 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1786 * configure: Regenerated.
1788 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1790 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1792 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1794 * gencode.c (print_igen_insn_models): Assume certain architectures
1795 include all mips* instructions.
1796 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1799 * Makefile.in (tmp.igen): Add target. Generate igen input from
1802 * gencode.c (FEATURE_IGEN): Define.
1803 (main): Add --igen option. Generate output in igen format.
1804 (process_instructions): Format output according to igen option.
1805 (print_igen_insn_format): New function.
1806 (print_igen_insn_models): New function.
1807 (process_instructions): Only issue warnings and ignore
1808 instructions when no FEATURE_IGEN.
1810 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1812 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1815 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1817 * configure: Regenerated to track ../common/aclocal.m4 changes.
1819 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1821 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1822 SIM_RESERVED_BITS): Delete, moved to common.
1823 (SIM_EXTRA_CFLAGS): Update.
1825 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1827 * configure.in: Configure non-strict memory alignment.
1828 * configure: Regenerated to track ../common/aclocal.m4 changes.
1830 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1832 * configure: Regenerated to track ../common/aclocal.m4 changes.
1834 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1836 * gencode.c (SDBBP,DERET): Added (3900) insns.
1837 (RFE): Turn on for 3900.
1838 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1839 (dsstate): Made global.
1840 (SUBTARGET_R3900): Added.
1841 (CANCELDELAYSLOT): New.
1842 (SignalException): Ignore SystemCall rather than ignore and
1843 terminate. Add DebugBreakPoint handling.
1844 (decode_coproc): New insns RFE, DERET; and new registers Debug
1845 and DEPC protected by SUBTARGET_R3900.
1846 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1848 * Makefile.in,configure.in: Add mips subtarget option.
1849 * configure: Update.
1851 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1853 * gencode.c: Add r3900 (tx39).
1856 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1858 * gencode.c (build_instruction): Don't need to subtract 4 for
1861 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1863 * interp.c: Correct some HASFPU problems.
1865 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1867 * configure: Regenerated to track ../common/aclocal.m4 changes.
1869 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1871 * interp.c (mips_options): Fix samples option short form, should
1874 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1876 * interp.c (sim_info): Enable info code. Was just returning.
1878 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1880 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1883 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1885 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1887 (build_instruction): Ditto for LL.
1889 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1891 * configure: Regenerated to track ../common/aclocal.m4 changes.
1893 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1895 * configure: Regenerated to track ../common/aclocal.m4 changes.
1898 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1900 * interp.c (sim_open): Add call to sim_analyze_program, update
1903 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1905 * interp.c (sim_kill): Delete.
1906 (sim_create_inferior): Add ABFD argument. Set PC from same.
1907 (sim_load): Move code initializing trap handlers from here.
1908 (sim_open): To here.
1909 (sim_load): Delete, use sim-hload.c.
1911 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1913 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1915 * configure: Regenerated to track ../common/aclocal.m4 changes.
1918 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1920 * interp.c (sim_open): Add ABFD argument.
1921 (sim_load): Move call to sim_config from here.
1922 (sim_open): To here. Check return status.
1924 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1926 * gencode.c (build_instruction): Two arg MADD should
1927 not assign result to $0.
1929 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1931 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1932 * sim/mips/configure.in: Regenerate.
1934 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1936 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1937 signed8, unsigned8 et.al. types.
1939 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1940 hosts when selecting subreg.
1942 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1944 * interp.c (sim_engine_run): Reset the ZERO register to zero
1945 regardless of FEATURE_WARN_ZERO.
1946 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1948 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1950 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1951 (SignalException): For BreakPoints ignore any mode bits and just
1953 (SignalException): Always set the CAUSE register.
1955 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1957 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1958 exception has been taken.
1960 * interp.c: Implement the ERET and mt/f sr instructions.
1962 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1964 * interp.c (SignalException): Don't bother restarting an
1967 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1969 * interp.c (SignalException): Really take an interrupt.
1970 (interrupt_event): Only deliver interrupts when enabled.
1972 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1974 * interp.c (sim_info): Only print info when verbose.
1975 (sim_info) Use sim_io_printf for output.
1977 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1979 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1982 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1984 * interp.c (sim_do_command): Check for common commands if a
1985 simulator specific command fails.
1987 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1989 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1990 and simBE when DEBUG is defined.
1992 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1994 * interp.c (interrupt_event): New function. Pass exception event
1995 onto exception handler.
1997 * configure.in: Check for stdlib.h.
1998 * configure: Regenerate.
2000 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2001 variable declaration.
2002 (build_instruction): Initialize memval1.
2003 (build_instruction): Add UNUSED attribute to byte, bigend,
2005 (build_operands): Ditto.
2007 * interp.c: Fix GCC warnings.
2008 (sim_get_quit_code): Delete.
2010 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2011 * Makefile.in: Ditto.
2012 * configure: Re-generate.
2014 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2016 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2018 * interp.c (mips_option_handler): New function parse argumes using
2020 (myname): Replace with STATE_MY_NAME.
2021 (sim_open): Delete check for host endianness - performed by
2023 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2024 (sim_open): Move much of the initialization from here.
2025 (sim_load): To here. After the image has been loaded and
2027 (sim_open): Move ColdReset from here.
2028 (sim_create_inferior): To here.
2029 (sim_open): Make FP check less dependant on host endianness.
2031 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2033 * interp.c (sim_set_callbacks): Delete.
2035 * interp.c (membank, membank_base, membank_size): Replace with
2036 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2037 (sim_open): Remove call to callback->init. gdb/run do this.
2041 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2043 * interp.c (big_endian_p): Delete, replaced by
2044 current_target_byte_order.
2046 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2048 * interp.c (host_read_long, host_read_word, host_swap_word,
2049 host_swap_long): Delete. Using common sim-endian.
2050 (sim_fetch_register, sim_store_register): Use H2T.
2051 (pipeline_ticks): Delete. Handled by sim-events.
2053 (sim_engine_run): Update.
2055 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2057 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2059 (SignalException): To here. Signal using sim_engine_halt.
2060 (sim_stop_reason): Delete, moved to common.
2062 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2064 * interp.c (sim_open): Add callback argument.
2065 (sim_set_callbacks): Delete SIM_DESC argument.
2068 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2070 * Makefile.in (SIM_OBJS): Add common modules.
2072 * interp.c (sim_set_callbacks): Also set SD callback.
2073 (set_endianness, xfer_*, swap_*): Delete.
2074 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2075 Change to functions using sim-endian macros.
2076 (control_c, sim_stop): Delete, use common version.
2077 (simulate): Convert into.
2078 (sim_engine_run): This function.
2079 (sim_resume): Delete.
2081 * interp.c (simulation): New variable - the simulator object.
2082 (sim_kind): Delete global - merged into simulation.
2083 (sim_load): Cleanup. Move PC assignment from here.
2084 (sim_create_inferior): To here.
2086 * sim-main.h: New file.
2087 * interp.c (sim-main.h): Include.
2089 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2091 * configure: Regenerated to track ../common/aclocal.m4 changes.
2093 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2095 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2097 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2099 * gencode.c (build_instruction): DIV instructions: check
2100 for division by zero and integer overflow before using
2101 host's division operation.
2103 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2105 * Makefile.in (SIM_OBJS): Add sim-load.o.
2106 * interp.c: #include bfd.h.
2107 (target_byte_order): Delete.
2108 (sim_kind, myname, big_endian_p): New static locals.
2109 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2110 after argument parsing. Recognize -E arg, set endianness accordingly.
2111 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2112 load file into simulator. Set PC from bfd.
2113 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2114 (set_endianness): Use big_endian_p instead of target_byte_order.
2116 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2118 * interp.c (sim_size): Delete prototype - conflicts with
2119 definition in remote-sim.h. Correct definition.
2121 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2123 * configure: Regenerated to track ../common/aclocal.m4 changes.
2126 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2128 * interp.c (sim_open): New arg `kind'.
2130 * configure: Regenerated to track ../common/aclocal.m4 changes.
2132 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2134 * configure: Regenerated to track ../common/aclocal.m4 changes.
2136 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2138 * interp.c (sim_open): Set optind to 0 before calling getopt.
2140 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2142 * configure: Regenerated to track ../common/aclocal.m4 changes.
2144 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2146 * interp.c : Replace uses of pr_addr with pr_uword64
2147 where the bit length is always 64 independent of SIM_ADDR.
2148 (pr_uword64) : added.
2150 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2152 * configure: Re-generate.
2154 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2156 * configure: Regenerate to track ../common/aclocal.m4 changes.
2158 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2160 * interp.c (sim_open): New SIM_DESC result. Argument is now
2162 (other sim_*): New SIM_DESC argument.
2164 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2166 * interp.c: Fix printing of addresses for non-64-bit targets.
2167 (pr_addr): Add function to print address based on size.
2169 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2171 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2173 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2175 * gencode.c (build_mips16_operands): Correct computation of base
2176 address for extended PC relative instruction.
2178 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2180 * interp.c (mips16_entry): Add support for floating point cases.
2181 (SignalException): Pass floating point cases to mips16_entry.
2182 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2184 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2186 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2187 and then set the state to fmt_uninterpreted.
2188 (COP_SW): Temporarily set the state to fmt_word while calling
2191 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2193 * gencode.c (build_instruction): The high order may be set in the
2194 comparison flags at any ISA level, not just ISA 4.
2196 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2198 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2199 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2200 * configure.in: sinclude ../common/aclocal.m4.
2201 * configure: Regenerated.
2203 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2205 * configure: Rebuild after change to aclocal.m4.
2207 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2209 * configure configure.in Makefile.in: Update to new configure
2210 scheme which is more compatible with WinGDB builds.
2211 * configure.in: Improve comment on how to run autoconf.
2212 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2213 * Makefile.in: Use autoconf substitution to install common
2216 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2218 * gencode.c (build_instruction): Use BigEndianCPU instead of
2221 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2223 * interp.c (sim_monitor): Make output to stdout visible in
2224 wingdb's I/O log window.
2226 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2228 * support.h: Undo previous change to SIGTRAP
2231 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2233 * interp.c (store_word, load_word): New static functions.
2234 (mips16_entry): New static function.
2235 (SignalException): Look for mips16 entry and exit instructions.
2236 (simulate): Use the correct index when setting fpr_state after
2237 doing a pending move.
2239 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2241 * interp.c: Fix byte-swapping code throughout to work on
2242 both little- and big-endian hosts.
2244 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2246 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2247 with gdb/config/i386/xm-windows.h.
2249 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2251 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2252 that messes up arithmetic shifts.
2254 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2256 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2257 SIGTRAP and SIGQUIT for _WIN32.
2259 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2261 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2262 force a 64 bit multiplication.
2263 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2264 destination register is 0, since that is the default mips16 nop
2267 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2269 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2270 (build_endian_shift): Don't check proc64.
2271 (build_instruction): Always set memval to uword64. Cast op2 to
2272 uword64 when shifting it left in memory instructions. Always use
2273 the same code for stores--don't special case proc64.
2275 * gencode.c (build_mips16_operands): Fix base PC value for PC
2277 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2279 * interp.c (simJALDELAYSLOT): Define.
2280 (JALDELAYSLOT): Define.
2281 (INDELAYSLOT, INJALDELAYSLOT): Define.
2282 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2284 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2286 * interp.c (sim_open): add flush_cache as a PMON routine
2287 (sim_monitor): handle flush_cache by ignoring it
2289 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2291 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2293 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2294 (BigEndianMem): Rename to ByteSwapMem and change sense.
2295 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2296 BigEndianMem references to !ByteSwapMem.
2297 (set_endianness): New function, with prototype.
2298 (sim_open): Call set_endianness.
2299 (sim_info): Use simBE instead of BigEndianMem.
2300 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2301 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2302 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2303 ifdefs, keeping the prototype declaration.
2304 (swap_word): Rewrite correctly.
2305 (ColdReset): Delete references to CONFIG. Delete endianness related
2306 code; moved to set_endianness.
2308 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2310 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2311 * interp.c (CHECKHILO): Define away.
2312 (simSIGINT): New macro.
2313 (membank_size): Increase from 1MB to 2MB.
2314 (control_c): New function.
2315 (sim_resume): Rename parameter signal to signal_number. Add local
2316 variable prev. Call signal before and after simulate.
2317 (sim_stop_reason): Add simSIGINT support.
2318 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2320 (sim_warning): Delete call to SignalException. Do call printf_filtered
2322 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2323 a call to sim_warning.
2325 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2327 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2328 16 bit instructions.
2330 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2332 Add support for mips16 (16 bit MIPS implementation):
2333 * gencode.c (inst_type): Add mips16 instruction encoding types.
2334 (GETDATASIZEINSN): Define.
2335 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2336 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2338 (MIPS16_DECODE): New table, for mips16 instructions.
2339 (bitmap_val): New static function.
2340 (struct mips16_op): Define.
2341 (mips16_op_table): New table, for mips16 operands.
2342 (build_mips16_operands): New static function.
2343 (process_instructions): If PC is odd, decode a mips16
2344 instruction. Break out instruction handling into new
2345 build_instruction function.
2346 (build_instruction): New static function, broken out of
2347 process_instructions. Check modifiers rather than flags for SHIFT
2348 bit count and m[ft]{hi,lo} direction.
2349 (usage): Pass program name to fprintf.
2350 (main): Remove unused variable this_option_optind. Change
2351 ``*loptarg++'' to ``loptarg++''.
2352 (my_strtoul): Parenthesize && within ||.
2353 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2354 (simulate): If PC is odd, fetch a 16 bit instruction, and
2355 increment PC by 2 rather than 4.
2356 * configure.in: Add case for mips16*-*-*.
2357 * configure: Rebuild.
2359 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2361 * interp.c: Allow -t to enable tracing in standalone simulator.
2362 Fix garbage output in trace file and error messages.
2364 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2366 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2367 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2368 * configure.in: Simplify using macros in ../common/aclocal.m4.
2369 * configure: Regenerated.
2370 * tconfig.in: New file.
2372 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2374 * interp.c: Fix bugs in 64-bit port.
2375 Use ansi function declarations for msvc compiler.
2376 Initialize and test file pointer in trace code.
2377 Prevent duplicate definition of LAST_EMED_REGNUM.
2379 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2381 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2383 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2385 * interp.c (SignalException): Check for explicit terminating
2387 * gencode.c: Pass instruction value through SignalException()
2388 calls for Trap, Breakpoint and Syscall.
2390 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2392 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2393 only used on those hosts that provide it.
2394 * configure.in: Add sqrt() to list of functions to be checked for.
2395 * config.in: Re-generated.
2396 * configure: Re-generated.
2398 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2400 * gencode.c (process_instructions): Call build_endian_shift when
2401 expanding STORE RIGHT, to fix swr.
2402 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2403 clear the high bits.
2404 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2405 Fix float to int conversions to produce signed values.
2407 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2409 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2410 (process_instructions): Correct handling of nor instruction.
2411 Correct shift count for 32 bit shift instructions. Correct sign
2412 extension for arithmetic shifts to not shift the number of bits in
2413 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2414 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2416 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2417 It's OK to have a mult follow a mult. What's not OK is to have a
2418 mult follow an mfhi.
2419 (Convert): Comment out incorrect rounding code.
2421 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2423 * interp.c (sim_monitor): Improved monitor printf
2424 simulation. Tidied up simulator warnings, and added "--log" option
2425 for directing warning message output.
2426 * gencode.c: Use sim_warning() rather than WARNING macro.
2428 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2430 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2431 getopt1.o, rather than on gencode.c. Link objects together.
2432 Don't link against -liberty.
2433 (gencode.o, getopt.o, getopt1.o): New targets.
2434 * gencode.c: Include <ctype.h> and "ansidecl.h".
2435 (AND): Undefine after including "ansidecl.h".
2436 (ULONG_MAX): Define if not defined.
2437 (OP_*): Don't define macros; now defined in opcode/mips.h.
2438 (main): Call my_strtoul rather than strtoul.
2439 (my_strtoul): New static function.
2441 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2443 * gencode.c (process_instructions): Generate word64 and uword64
2444 instead of `long long' and `unsigned long long' data types.
2445 * interp.c: #include sysdep.h to get signals, and define default
2447 * (Convert): Work around for Visual-C++ compiler bug with type
2449 * support.h: Make things compile under Visual-C++ by using
2450 __int64 instead of `long long'. Change many refs to long long
2451 into word64/uword64 typedefs.
2453 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2455 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2456 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2458 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2459 (AC_PROG_INSTALL): Added.
2460 (AC_PROG_CC): Moved to before configure.host call.
2461 * configure: Rebuilt.
2463 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2465 * configure.in: Define @SIMCONF@ depending on mips target.
2466 * configure: Rebuild.
2467 * Makefile.in (run): Add @SIMCONF@ to control simulator
2469 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2470 * interp.c: Remove some debugging, provide more detailed error
2471 messages, update memory accesses to use LOADDRMASK.
2473 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2475 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2476 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2478 * configure: Rebuild.
2479 * config.in: New file, generated by autoheader.
2480 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2481 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2482 HAVE_ANINT and HAVE_AINT, as appropriate.
2483 * Makefile.in (run): Use @LIBS@ rather than -lm.
2484 (interp.o): Depend upon config.h.
2485 (Makefile): Just rebuild Makefile.
2486 (clean): Remove stamp-h.
2487 (mostlyclean): Make the same as clean, not as distclean.
2488 (config.h, stamp-h): New targets.
2490 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2492 * interp.c (ColdReset): Fix boolean test. Make all simulator
2495 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2497 * interp.c (xfer_direct_word, xfer_direct_long,
2498 swap_direct_word, swap_direct_long, xfer_big_word,
2499 xfer_big_long, xfer_little_word, xfer_little_long,
2500 swap_word,swap_long): Added.
2501 * interp.c (ColdReset): Provide function indirection to
2502 host<->simulated_target transfer routines.
2503 * interp.c (sim_store_register, sim_fetch_register): Updated to
2504 make use of indirected transfer routines.
2506 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2508 * gencode.c (process_instructions): Ensure FP ABS instruction
2510 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2511 system call support.
2513 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2515 * interp.c (sim_do_command): Complain if callback structure not
2518 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2520 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2521 support for Sun hosts.
2522 * Makefile.in (gencode): Ensure the host compiler and libraries
2523 used for cross-hosted build.
2525 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2527 * interp.c, gencode.c: Some more (TODO) tidying.
2529 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2531 * gencode.c, interp.c: Replaced explicit long long references with
2532 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2533 * support.h (SET64LO, SET64HI): Macros added.
2535 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2537 * configure: Regenerate with autoconf 2.7.
2539 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2541 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2542 * support.h: Remove superfluous "1" from #if.
2543 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2545 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2547 * interp.c (StoreFPR): Control UndefinedResult() call on
2548 WARN_RESULT manifest.
2550 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2552 * gencode.c: Tidied instruction decoding, and added FP instruction
2555 * interp.c: Added dineroIII, and BSD profiling support. Also
2556 run-time FP handling.
2558 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2560 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2561 gencode.c, interp.c, support.h: created.
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