1 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
3 * configure.ac: Always link against dv-sockser.o.
4 * configure: Regenerate.
6 2012-06-15 Joel Brobecker <brobecker@adacore.com>
8 * config.in, configure: Regenerate.
10 2012-05-18 Nick Clifton <nickc@redhat.com>
13 * interp.c: Include config.h before system header files.
15 2012-03-24 Mike Frysinger <vapier@gentoo.org>
17 * aclocal.m4, config.in, configure: Regenerate.
19 2011-12-03 Mike Frysinger <vapier@gentoo.org>
21 * aclocal.m4: New file.
22 * configure: Regenerate.
24 2011-10-19 Mike Frysinger <vapier@gentoo.org>
26 * configure: Regenerate after common/acinclude.m4 update.
28 2011-10-17 Mike Frysinger <vapier@gentoo.org>
30 * configure.ac: Change include to common/acinclude.m4.
32 2011-10-17 Mike Frysinger <vapier@gentoo.org>
34 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
35 call. Replace common.m4 include with SIM_AC_COMMON.
36 * configure: Regenerate.
38 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
40 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
42 (tmp-mach-multi): Exit early when igen fails.
44 2011-07-05 Mike Frysinger <vapier@gentoo.org>
46 * interp.c (sim_do_command): Delete.
48 2011-02-14 Mike Frysinger <vapier@gentoo.org>
50 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
51 (tx3904sio_fifo_reset): Likewise.
52 * interp.c (sim_monitor): Likewise.
54 2010-04-14 Mike Frysinger <vapier@gentoo.org>
56 * interp.c (sim_write): Add const to buffer arg.
58 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
60 * interp.c: Don't include sysdep.h
62 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
64 * configure: Regenerate.
66 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
68 * config.in: Regenerate.
69 * configure: Likewise.
71 * configure: Regenerate.
73 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
75 * configure: Regenerate to track ../common/common.m4 changes.
78 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
79 Daniel Jacobowitz <dan@codesourcery.com>
80 Joseph Myers <joseph@codesourcery.com>
82 * configure: Regenerate.
84 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
86 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
87 that unconditionally allows fmt_ps.
88 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
89 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
90 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
91 filter from 64,f to 32,f.
92 (PREFX): Change filter from 64 to 32.
93 (LDXC1, LUXC1): Provide separate mips32r2 implementations
94 that use do_load_double instead of do_load. Make both LUXC1
95 versions unpredictable if SizeFGR () != 64.
96 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
97 instead of do_store. Remove unused variable. Make both SUXC1
98 versions unpredictable if SizeFGR () != 64.
100 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
102 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
103 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
104 shifts for that case.
106 2007-09-04 Nick Clifton <nickc@redhat.com>
108 * interp.c (options enum): Add OPTION_INFO_MEMORY.
109 (display_mem_info): New static variable.
110 (mips_option_handler): Handle OPTION_INFO_MEMORY.
111 (mips_options): Add info-memory and memory-info.
112 (sim_open): After processing the command line and board
113 specification, check display_mem_info. If it is set then
114 call the real handler for the --memory-info command line
117 2007-08-24 Joel Brobecker <brobecker@adacore.com>
119 * configure.ac: Change license of multi-run.c to GPL version 3.
120 * configure: Regenerate.
122 2007-06-28 Richard Sandiford <richard@codesourcery.com>
124 * configure.ac, configure: Revert last patch.
126 2007-06-26 Richard Sandiford <richard@codesourcery.com>
128 * configure.ac (sim_mipsisa3264_configs): New variable.
129 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
130 every configuration support all four targets, using the triplet to
131 determine the default.
132 * configure: Regenerate.
134 2007-06-25 Richard Sandiford <richard@codesourcery.com>
136 * Makefile.in (m16run.o): New rule.
138 2007-05-15 Thiemo Seufer <ths@mips.com>
140 * mips3264r2.igen (DSHD): Fix compile warning.
142 2007-05-14 Thiemo Seufer <ths@mips.com>
144 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
145 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
146 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
147 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
150 2007-03-01 Thiemo Seufer <ths@mips.com>
152 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
155 2007-02-20 Thiemo Seufer <ths@mips.com>
157 * dsp.igen: Update copyright notice.
158 * dsp2.igen: Fix copyright notice.
160 2007-02-20 Thiemo Seufer <ths@mips.com>
161 Chao-Ying Fu <fu@mips.com>
163 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
164 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
165 Add dsp2 to sim_igen_machine.
166 * configure: Regenerate.
167 * dsp.igen (do_ph_op): Add MUL support when op = 2.
168 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
169 (mulq_rs.ph): Use do_ph_mulq.
170 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
171 * mips.igen: Add dsp2 model and include dsp2.igen.
172 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
173 for *mips32r2, *mips64r2, *dsp.
174 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
175 for *mips32r2, *mips64r2, *dsp2.
176 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
178 2007-02-19 Thiemo Seufer <ths@mips.com>
179 Nigel Stephens <nigel@mips.com>
181 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
182 jumps with hazard barrier.
184 2007-02-19 Thiemo Seufer <ths@mips.com>
185 Nigel Stephens <nigel@mips.com>
187 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
188 after each call to sim_io_write.
190 2007-02-19 Thiemo Seufer <ths@mips.com>
191 Nigel Stephens <nigel@mips.com>
193 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
194 supported by this simulator.
195 (decode_coproc): Recognise additional CP0 Config registers
198 2007-02-19 Thiemo Seufer <ths@mips.com>
199 Nigel Stephens <nigel@mips.com>
200 David Ung <davidu@mips.com>
202 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
203 uninterpreted formats. If fmt is one of the uninterpreted types
204 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
205 fmt_word, and fmt_uninterpreted_64 like fmt_long.
206 (store_fpr): When writing an invalid odd register, set the
207 matching even register to fmt_unknown, not the following register.
208 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
209 the the memory window at offset 0 set by --memory-size command
211 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
213 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
215 (sim_monitor): When returning the memory size to the MIPS
216 application, use the value in STATE_MEM_SIZE, not an arbitrary
218 (cop_lw): Don' mess around with FPR_STATE, just pass
219 fmt_uninterpreted_32 to StoreFPR.
221 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
223 * mips.igen (not_word_value): Single version for mips32, mips64
226 2007-02-19 Thiemo Seufer <ths@mips.com>
227 Nigel Stephens <nigel@mips.com>
229 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
232 2007-02-17 Thiemo Seufer <ths@mips.com>
234 * configure.ac (mips*-sde-elf*): Move in front of generic machine
236 * configure: Regenerate.
238 2007-02-17 Thiemo Seufer <ths@mips.com>
240 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
241 Add mdmx to sim_igen_machine.
242 (mipsisa64*-*-*): Likewise. Remove dsp.
243 (mipsisa32*-*-*): Remove dsp.
244 * configure: Regenerate.
246 2007-02-13 Thiemo Seufer <ths@mips.com>
248 * configure.ac: Add mips*-sde-elf* target.
249 * configure: Regenerate.
251 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
253 * acconfig.h: Remove.
254 * config.in, configure: Regenerate.
256 2006-11-07 Thiemo Seufer <ths@mips.com>
258 * dsp.igen (do_w_op): Fix compiler warning.
260 2006-08-29 Thiemo Seufer <ths@mips.com>
261 David Ung <davidu@mips.com>
263 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
265 * configure: Regenerate.
266 * mips.igen (model): Add smartmips.
267 (MADDU): Increment ACX if carry.
268 (do_mult): Clear ACX.
269 (ROR,RORV): Add smartmips.
270 (include): Include smartmips.igen.
271 * sim-main.h (ACX): Set to REGISTERS[89].
272 * smartmips.igen: New file.
274 2006-08-29 Thiemo Seufer <ths@mips.com>
275 David Ung <davidu@mips.com>
277 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
278 mips3264r2.igen. Add missing dependency rules.
279 * m16e.igen: Support for mips16e save/restore instructions.
281 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
283 * configure: Regenerated.
285 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
287 * configure: Regenerated.
289 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
291 * configure: Regenerated.
293 2006-05-15 Chao-ying Fu <fu@mips.com>
295 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
297 2006-04-18 Nick Clifton <nickc@redhat.com>
299 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
302 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
304 * configure: Regenerate.
306 2005-12-14 Chao-ying Fu <fu@mips.com>
308 * Makefile.in (SIM_OBJS): Add dsp.o.
309 (dsp.o): New dependency.
310 (IGEN_INCLUDE): Add dsp.igen.
311 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
312 mipsisa64*-*-*): Add dsp to sim_igen_machine.
313 * configure: Regenerate.
314 * mips.igen: Add dsp model and include dsp.igen.
315 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
316 because these instructions are extended in DSP ASE.
317 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
318 adding 6 DSP accumulator registers and 1 DSP control register.
319 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
320 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
321 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
322 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
323 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
324 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
325 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
326 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
327 DSPCR_CCOND_SMASK): New define.
328 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
329 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
331 2005-07-08 Ian Lance Taylor <ian@airs.com>
333 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
335 2005-06-16 David Ung <davidu@mips.com>
336 Nigel Stephens <nigel@mips.com>
338 * mips.igen: New mips16e model and include m16e.igen.
339 (check_u64): Add mips16e tag.
340 * m16e.igen: New file for MIPS16e instructions.
341 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
342 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
344 * configure: Regenerate.
346 2005-05-26 David Ung <davidu@mips.com>
348 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
349 tags to all instructions which are applicable to the new ISAs.
350 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
352 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
354 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
356 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
357 * configure: Regenerate.
359 2005-03-23 Mark Kettenis <kettenis@gnu.org>
361 * configure: Regenerate.
363 2005-01-14 Andrew Cagney <cagney@gnu.org>
365 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
366 explicit call to AC_CONFIG_HEADER.
367 * configure: Regenerate.
369 2005-01-12 Andrew Cagney <cagney@gnu.org>
371 * configure.ac: Update to use ../common/common.m4.
372 * configure: Re-generate.
374 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
376 * configure: Regenerated to track ../common/aclocal.m4 changes.
378 2005-01-07 Andrew Cagney <cagney@gnu.org>
380 * configure.ac: Rename configure.in, require autoconf 2.59.
381 * configure: Re-generate.
383 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
385 * configure: Regenerate for ../common/aclocal.m4 update.
387 2004-09-24 Monika Chaddha <monika@acmet.com>
389 Committed by Andrew Cagney.
390 * m16.igen (CMP, CMPI): Fix assembler.
392 2004-08-18 Chris Demetriou <cgd@broadcom.com>
394 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
395 * configure: Regenerate.
397 2004-06-25 Chris Demetriou <cgd@broadcom.com>
399 * configure.in (sim_m16_machine): Include mipsIII.
400 * configure: Regenerate.
402 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
404 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
406 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
408 2004-04-10 Chris Demetriou <cgd@broadcom.com>
410 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
412 2004-04-09 Chris Demetriou <cgd@broadcom.com>
414 * mips.igen (check_fmt): Remove.
415 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
416 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
417 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
418 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
419 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
420 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
421 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
422 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
423 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
424 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
426 2004-04-09 Chris Demetriou <cgd@broadcom.com>
428 * sb1.igen (check_sbx): New function.
429 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
431 2004-03-29 Chris Demetriou <cgd@broadcom.com>
432 Richard Sandiford <rsandifo@redhat.com>
434 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
435 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
436 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
437 separate implementations for mipsIV and mipsV. Use new macros to
438 determine whether the restrictions apply.
440 2004-01-19 Chris Demetriou <cgd@broadcom.com>
442 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
443 (check_mult_hilo): Improve comments.
444 (check_div_hilo): Likewise. Also, fork off a new version
445 to handle mips32/mips64 (since there are no hazards to check
448 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
450 * mips.igen (do_dmultx): Fix check for negative operands.
452 2003-05-16 Ian Lance Taylor <ian@airs.com>
454 * Makefile.in (SHELL): Make sure this is defined.
455 (various): Use $(SHELL) whenever we invoke move-if-change.
457 2003-05-03 Chris Demetriou <cgd@broadcom.com>
459 * cp1.c: Tweak attribution slightly.
462 * mdmx.igen: Likewise.
463 * mips3d.igen: Likewise.
464 * sb1.igen: Likewise.
466 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
468 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
471 2003-02-27 Andrew Cagney <cagney@redhat.com>
473 * interp.c (sim_open): Rename _bfd to bfd.
474 (sim_create_inferior): Ditto.
476 2003-01-14 Chris Demetriou <cgd@broadcom.com>
478 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
480 2003-01-14 Chris Demetriou <cgd@broadcom.com>
482 * mips.igen (EI, DI): Remove.
484 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
486 * Makefile.in (tmp-run-multi): Fix mips16 filter.
488 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
489 Andrew Cagney <ac131313@redhat.com>
490 Gavin Romig-Koch <gavin@redhat.com>
491 Graydon Hoare <graydon@redhat.com>
492 Aldy Hernandez <aldyh@redhat.com>
493 Dave Brolley <brolley@redhat.com>
494 Chris Demetriou <cgd@broadcom.com>
496 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
497 (sim_mach_default): New variable.
498 (mips64vr-*-*, mips64vrel-*-*): New configurations.
499 Add a new simulator generator, MULTI.
500 * configure: Regenerate.
501 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
502 (multi-run.o): New dependency.
503 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
504 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
505 (tmp-multi): Combine them.
506 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
507 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
508 (distclean-extra): New rule.
509 * sim-main.h: Include bfd.h.
510 (MIPS_MACH): New macro.
511 * mips.igen (vr4120, vr5400, vr5500): New models.
512 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
513 * vr.igen: Replace with new version.
515 2003-01-04 Chris Demetriou <cgd@broadcom.com>
517 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
518 * configure: Regenerate.
520 2002-12-31 Chris Demetriou <cgd@broadcom.com>
522 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
523 * mips.igen: Remove all invocations of check_branch_bug and
526 2002-12-16 Chris Demetriou <cgd@broadcom.com>
528 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
530 2002-07-30 Chris Demetriou <cgd@broadcom.com>
532 * mips.igen (do_load_double, do_store_double): New functions.
533 (LDC1, SDC1): Rename to...
534 (LDC1b, SDC1b): respectively.
535 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
537 2002-07-29 Michael Snyder <msnyder@redhat.com>
539 * cp1.c (fp_recip2): Modify initialization expression so that
540 GCC will recognize it as constant.
542 2002-06-18 Chris Demetriou <cgd@broadcom.com>
544 * mdmx.c (SD_): Delete.
545 (Unpredictable): Re-define, for now, to directly invoke
546 unpredictable_action().
547 (mdmx_acc_op): Fix error in .ob immediate handling.
549 2002-06-18 Andrew Cagney <cagney@redhat.com>
551 * interp.c (sim_firmware_command): Initialize `address'.
553 2002-06-16 Andrew Cagney <ac131313@redhat.com>
555 * configure: Regenerated to track ../common/aclocal.m4 changes.
557 2002-06-14 Chris Demetriou <cgd@broadcom.com>
558 Ed Satterthwaite <ehs@broadcom.com>
560 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
561 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
562 * mips.igen: Include mips3d.igen.
563 (mips3d): New model name for MIPS-3D ASE instructions.
564 (CVT.W.fmt): Don't use this instruction for word (source) format
566 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
567 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
568 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
569 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
570 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
571 (RSquareRoot1, RSquareRoot2): New macros.
572 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
573 (fp_rsqrt2): New functions.
574 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
575 * configure: Regenerate.
577 2002-06-13 Chris Demetriou <cgd@broadcom.com>
578 Ed Satterthwaite <ehs@broadcom.com>
580 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
581 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
582 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
583 (convert): Note that this function is not used for paired-single
585 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
586 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
587 (check_fmt_p): Enable paired-single support.
588 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
589 (PUU.PS): New instructions.
590 (CVT.S.fmt): Don't use this instruction for paired-single format
592 * sim-main.h (FP_formats): New value 'fmt_ps.'
593 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
594 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
596 2002-06-12 Chris Demetriou <cgd@broadcom.com>
598 * mips.igen: Fix formatting of function calls in
601 2002-06-12 Chris Demetriou <cgd@broadcom.com>
603 * mips.igen (MOVN, MOVZ): Trace result.
604 (TNEI): Print "tnei" as the opcode name in traces.
605 (CEIL.W): Add disassembly string for traces.
606 (RSQRT.fmt): Make location of disassembly string consistent
607 with other instructions.
609 2002-06-12 Chris Demetriou <cgd@broadcom.com>
611 * mips.igen (X): Delete unused function.
613 2002-06-08 Andrew Cagney <cagney@redhat.com>
615 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
617 2002-06-07 Chris Demetriou <cgd@broadcom.com>
618 Ed Satterthwaite <ehs@broadcom.com>
620 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
621 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
622 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
623 (fp_nmsub): New prototypes.
624 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
625 (NegMultiplySub): New defines.
626 * mips.igen (RSQRT.fmt): Use RSquareRoot().
627 (MADD.D, MADD.S): Replace with...
628 (MADD.fmt): New instruction.
629 (MSUB.D, MSUB.S): Replace with...
630 (MSUB.fmt): New instruction.
631 (NMADD.D, NMADD.S): Replace with...
632 (NMADD.fmt): New instruction.
633 (NMSUB.D, MSUB.S): Replace with...
634 (NMSUB.fmt): New instruction.
636 2002-06-07 Chris Demetriou <cgd@broadcom.com>
637 Ed Satterthwaite <ehs@broadcom.com>
639 * cp1.c: Fix more comment spelling and formatting.
640 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
641 (denorm_mode): New function.
642 (fpu_unary, fpu_binary): Round results after operation, collect
643 status from rounding operations, and update the FCSR.
644 (convert): Collect status from integer conversions and rounding
645 operations, and update the FCSR. Adjust NaN values that result
646 from conversions. Convert to use sim_io_eprintf rather than
647 fprintf, and remove some debugging code.
648 * cp1.h (fenr_FS): New define.
650 2002-06-07 Chris Demetriou <cgd@broadcom.com>
652 * cp1.c (convert): Remove unusable debugging code, and move MIPS
653 rounding mode to sim FP rounding mode flag conversion code into...
654 (rounding_mode): New function.
656 2002-06-07 Chris Demetriou <cgd@broadcom.com>
658 * cp1.c: Clean up formatting of a few comments.
659 (value_fpr): Reformat switch statement.
661 2002-06-06 Chris Demetriou <cgd@broadcom.com>
662 Ed Satterthwaite <ehs@broadcom.com>
665 * sim-main.h: Include cp1.h.
666 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
667 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
668 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
669 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
670 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
671 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
672 * cp1.c: Don't include sim-fpu.h; already included by
673 sim-main.h. Clean up formatting of some comments.
674 (NaN, Equal, Less): Remove.
675 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
676 (fp_cmp): New functions.
677 * mips.igen (do_c_cond_fmt): Remove.
678 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
679 Compare. Add result tracing.
680 (CxC1): Remove, replace with...
681 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
682 (DMxC1): Remove, replace with...
683 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
684 (MxC1): Remove, replace with...
685 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
687 2002-06-04 Chris Demetriou <cgd@broadcom.com>
689 * sim-main.h (FGRIDX): Remove, replace all uses with...
690 (FGR_BASE): New macro.
691 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
692 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
693 (NR_FGR, FGR): Likewise.
694 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
695 * mips.igen: Likewise.
697 2002-06-04 Chris Demetriou <cgd@broadcom.com>
699 * cp1.c: Add an FSF Copyright notice to this file.
701 2002-06-04 Chris Demetriou <cgd@broadcom.com>
702 Ed Satterthwaite <ehs@broadcom.com>
704 * cp1.c (Infinity): Remove.
705 * sim-main.h (Infinity): Likewise.
707 * cp1.c (fp_unary, fp_binary): New functions.
708 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
709 (fp_sqrt): New functions, implemented in terms of the above.
710 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
711 (Recip, SquareRoot): Remove (replaced by functions above).
712 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
713 (fp_recip, fp_sqrt): New prototypes.
714 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
715 (Recip, SquareRoot): Replace prototypes with #defines which
716 invoke the functions above.
718 2002-06-03 Chris Demetriou <cgd@broadcom.com>
720 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
721 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
722 file, remove PARAMS from prototypes.
723 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
724 simulator state arguments.
725 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
726 pass simulator state arguments.
727 * cp1.c (SD): Redefine as CPU_STATE(cpu).
728 (store_fpr, convert): Remove 'sd' argument.
729 (value_fpr): Likewise. Convert to use 'SD' instead.
731 2002-06-03 Chris Demetriou <cgd@broadcom.com>
733 * cp1.c (Min, Max): Remove #if 0'd functions.
734 * sim-main.h (Min, Max): Remove.
736 2002-06-03 Chris Demetriou <cgd@broadcom.com>
738 * cp1.c: fix formatting of switch case and default labels.
739 * interp.c: Likewise.
740 * sim-main.c: Likewise.
742 2002-06-03 Chris Demetriou <cgd@broadcom.com>
744 * cp1.c: Clean up comments which describe FP formats.
745 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
747 2002-06-03 Chris Demetriou <cgd@broadcom.com>
748 Ed Satterthwaite <ehs@broadcom.com>
750 * configure.in (mipsisa64sb1*-*-*): New target for supporting
751 Broadcom SiByte SB-1 processor configurations.
752 * configure: Regenerate.
753 * sb1.igen: New file.
754 * mips.igen: Include sb1.igen.
756 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
757 * mdmx.igen: Add "sb1" model to all appropriate functions and
759 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
760 (ob_func, ob_acc): Reference the above.
761 (qh_acc): Adjust to keep the same size as ob_acc.
762 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
763 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
765 2002-06-03 Chris Demetriou <cgd@broadcom.com>
767 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
769 2002-06-02 Chris Demetriou <cgd@broadcom.com>
770 Ed Satterthwaite <ehs@broadcom.com>
772 * mips.igen (mdmx): New (pseudo-)model.
773 * mdmx.c, mdmx.igen: New files.
774 * Makefile.in (SIM_OBJS): Add mdmx.o.
775 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
777 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
778 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
779 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
780 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
781 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
782 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
783 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
784 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
785 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
786 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
787 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
788 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
789 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
790 (qh_fmtsel): New macros.
791 (_sim_cpu): New member "acc".
792 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
793 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
795 2002-05-01 Chris Demetriou <cgd@broadcom.com>
797 * interp.c: Use 'deprecated' rather than 'depreciated.'
798 * sim-main.h: Likewise.
800 2002-05-01 Chris Demetriou <cgd@broadcom.com>
802 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
803 which wouldn't compile anyway.
804 * sim-main.h (unpredictable_action): New function prototype.
805 (Unpredictable): Define to call igen function unpredictable().
806 (NotWordValue): New macro to call igen function not_word_value().
807 (UndefinedResult): Remove.
808 * interp.c (undefined_result): Remove.
809 (unpredictable_action): New function.
810 * mips.igen (not_word_value, unpredictable): New functions.
811 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
812 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
813 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
814 NotWordValue() to check for unpredictable inputs, then
815 Unpredictable() to handle them.
817 2002-02-24 Chris Demetriou <cgd@broadcom.com>
819 * mips.igen: Fix formatting of calls to Unpredictable().
821 2002-04-20 Andrew Cagney <ac131313@redhat.com>
823 * interp.c (sim_open): Revert previous change.
825 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
827 * interp.c (sim_open): Disable chunk of code that wrote code in
828 vector table entries.
830 2002-03-19 Chris Demetriou <cgd@broadcom.com>
832 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
833 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
836 2002-03-19 Chris Demetriou <cgd@broadcom.com>
838 * cp1.c: Fix many formatting issues.
840 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
842 * cp1.c (fpu_format_name): New function to replace...
843 (DOFMT): This. Delete, and update all callers.
844 (fpu_rounding_mode_name): New function to replace...
845 (RMMODE): This. Delete, and update all callers.
847 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
849 * interp.c: Move FPU support routines from here to...
850 * cp1.c: Here. New file.
851 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
854 2002-03-12 Chris Demetriou <cgd@broadcom.com>
856 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
857 * mips.igen (mips32, mips64): New models, add to all instructions
858 and functions as appropriate.
859 (loadstore_ea, check_u64): New variant for model mips64.
860 (check_fmt_p): New variant for models mipsV and mips64, remove
861 mipsV model marking fro other variant.
864 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
865 for mips32 and mips64.
866 (DCLO, DCLZ): New instructions for mips64.
868 2002-03-07 Chris Demetriou <cgd@broadcom.com>
870 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
871 immediate or code as a hex value with the "%#lx" format.
872 (ANDI): Likewise, and fix printed instruction name.
874 2002-03-05 Chris Demetriou <cgd@broadcom.com>
876 * sim-main.h (UndefinedResult, Unpredictable): New macros
877 which currently do nothing.
879 2002-03-05 Chris Demetriou <cgd@broadcom.com>
881 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
882 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
883 (status_CU3): New definitions.
885 * sim-main.h (ExceptionCause): Add new values for MIPS32
886 and MIPS64: MDMX, MCheck, CacheErr. Update comments
887 for DebugBreakPoint and NMIReset to note their status in
889 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
890 (SignalExceptionCacheErr): New exception macros.
892 2002-03-05 Chris Demetriou <cgd@broadcom.com>
894 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
895 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
897 (SignalExceptionCoProcessorUnusable): Take as argument the
898 unusable coprocessor number.
900 2002-03-05 Chris Demetriou <cgd@broadcom.com>
902 * mips.igen: Fix formatting of all SignalException calls.
904 2002-03-05 Chris Demetriou <cgd@broadcom.com>
906 * sim-main.h (SIGNEXTEND): Remove.
908 2002-03-04 Chris Demetriou <cgd@broadcom.com>
910 * mips.igen: Remove gencode comment from top of file, fix
911 spelling in another comment.
913 2002-03-04 Chris Demetriou <cgd@broadcom.com>
915 * mips.igen (check_fmt, check_fmt_p): New functions to check
916 whether specific floating point formats are usable.
917 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
918 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
919 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
920 Use the new functions.
921 (do_c_cond_fmt): Remove format checks...
922 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
924 2002-03-03 Chris Demetriou <cgd@broadcom.com>
926 * mips.igen: Fix formatting of check_fpu calls.
928 2002-03-03 Chris Demetriou <cgd@broadcom.com>
930 * mips.igen (FLOOR.L.fmt): Store correct destination register.
932 2002-03-03 Chris Demetriou <cgd@broadcom.com>
934 * mips.igen: Remove whitespace at end of lines.
936 2002-03-02 Chris Demetriou <cgd@broadcom.com>
938 * mips.igen (loadstore_ea): New function to do effective
939 address calculations.
940 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
941 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
942 CACHE): Use loadstore_ea to do effective address computations.
944 2002-03-02 Chris Demetriou <cgd@broadcom.com>
946 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
947 * mips.igen (LL, CxC1, MxC1): Likewise.
949 2002-03-02 Chris Demetriou <cgd@broadcom.com>
951 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
952 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
953 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
954 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
955 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
956 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
957 Don't split opcode fields by hand, use the opcode field values
960 2002-03-01 Chris Demetriou <cgd@broadcom.com>
962 * mips.igen (do_divu): Fix spacing.
964 * mips.igen (do_dsllv): Move to be right before DSLLV,
965 to match the rest of the do_<shift> functions.
967 2002-03-01 Chris Demetriou <cgd@broadcom.com>
969 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
970 DSRL32, do_dsrlv): Trace inputs and results.
972 2002-03-01 Chris Demetriou <cgd@broadcom.com>
974 * mips.igen (CACHE): Provide instruction-printing string.
976 * interp.c (signal_exception): Comment tokens after #endif.
978 2002-02-28 Chris Demetriou <cgd@broadcom.com>
980 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
981 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
982 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
983 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
984 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
985 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
986 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
987 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
989 2002-02-28 Chris Demetriou <cgd@broadcom.com>
991 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
992 instruction-printing string.
993 (LWU): Use '64' as the filter flag.
995 2002-02-28 Chris Demetriou <cgd@broadcom.com>
997 * mips.igen (SDXC1): Fix instruction-printing string.
999 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1001 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1002 filter flags "32,f".
1004 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1006 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1009 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1011 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1012 add a comma) so that it more closely match the MIPS ISA
1013 documentation opcode partitioning.
1014 (PREF): Put useful names on opcode fields, and include
1015 instruction-printing string.
1017 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1019 * mips.igen (check_u64): New function which in the future will
1020 check whether 64-bit instructions are usable and signal an
1021 exception if not. Currently a no-op.
1022 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1023 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1024 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1025 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1027 * mips.igen (check_fpu): New function which in the future will
1028 check whether FPU instructions are usable and signal an exception
1029 if not. Currently a no-op.
1030 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1031 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1032 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1033 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1034 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1035 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1036 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1037 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1039 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1041 * mips.igen (do_load_left, do_load_right): Move to be immediately
1043 (do_store_left, do_store_right): Move to be immediately following
1046 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1048 * mips.igen (mipsV): New model name. Also, add it to
1049 all instructions and functions where it is appropriate.
1051 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1053 * mips.igen: For all functions and instructions, list model
1054 names that support that instruction one per line.
1056 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1058 * mips.igen: Add some additional comments about supported
1059 models, and about which instructions go where.
1060 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1061 order as is used in the rest of the file.
1063 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1065 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1066 indicating that ALU32_END or ALU64_END are there to check
1068 (DADD): Likewise, but also remove previous comment about
1071 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1073 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1074 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1075 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1076 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1077 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1078 fields (i.e., add and move commas) so that they more closely
1079 match the MIPS ISA documentation opcode partitioning.
1081 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1083 * mips.igen (ADDI): Print immediate value.
1084 (BREAK): Print code.
1085 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1086 (SLL): Print "nop" specially, and don't run the code
1087 that does the shift for the "nop" case.
1089 2001-11-17 Fred Fish <fnf@redhat.com>
1091 * sim-main.h (float_operation): Move enum declaration outside
1092 of _sim_cpu struct declaration.
1094 2001-04-12 Jim Blandy <jimb@redhat.com>
1096 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1097 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1099 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1100 PENDING_FILL, and you can get the intended effect gracefully by
1101 calling PENDING_SCHED directly.
1103 2001-02-23 Ben Elliston <bje@redhat.com>
1105 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1106 already defined elsewhere.
1108 2001-02-19 Ben Elliston <bje@redhat.com>
1110 * sim-main.h (sim_monitor): Return an int.
1111 * interp.c (sim_monitor): Add return values.
1112 (signal_exception): Handle error conditions from sim_monitor.
1114 2001-02-08 Ben Elliston <bje@redhat.com>
1116 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1117 (store_memory): Likewise, pass cia to sim_core_write*.
1119 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1121 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1122 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1124 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1126 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1127 * Makefile.in: Don't delete *.igen when cleaning directory.
1129 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1131 * m16.igen (break): Call SignalException not sim_engine_halt.
1133 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1135 From Jason Eckhardt:
1136 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1138 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1140 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1142 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1144 * mips.igen (do_dmultx): Fix typo.
1146 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1148 * configure: Regenerated to track ../common/aclocal.m4 changes.
1150 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1152 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1154 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1156 * sim-main.h (GPR_CLEAR): Define macro.
1158 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1160 * interp.c (decode_coproc): Output long using %lx and not %s.
1162 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1164 * interp.c (sim_open): Sort & extend dummy memory regions for
1165 --board=jmr3904 for eCos.
1167 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1169 * configure: Regenerated.
1171 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1173 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1174 calls, conditional on the simulator being in verbose mode.
1176 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1178 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1179 cache don't get ReservedInstruction traps.
1181 1999-11-29 Mark Salter <msalter@cygnus.com>
1183 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1184 to clear status bits in sdisr register. This is how the hardware works.
1186 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1187 being used by cygmon.
1189 1999-11-11 Andrew Haley <aph@cygnus.com>
1191 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1194 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1196 * mips.igen (MULT): Correct previous mis-applied patch.
1198 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1200 * mips.igen (delayslot32): Handle sequence like
1201 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1202 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1203 (MULT): Actually pass the third register...
1205 1999-09-03 Mark Salter <msalter@cygnus.com>
1207 * interp.c (sim_open): Added more memory aliases for additional
1208 hardware being touched by cygmon on jmr3904 board.
1210 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1212 * configure: Regenerated to track ../common/aclocal.m4 changes.
1214 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1216 * interp.c (sim_store_register): Handle case where client - GDB -
1217 specifies that a 4 byte register is 8 bytes in size.
1218 (sim_fetch_register): Ditto.
1220 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1222 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1223 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1224 (idt_monitor_base): Base address for IDT monitor traps.
1225 (pmon_monitor_base): Ditto for PMON.
1226 (lsipmon_monitor_base): Ditto for LSI PMON.
1227 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1228 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1229 (sim_firmware_command): New function.
1230 (mips_option_handler): Call it for OPTION_FIRMWARE.
1231 (sim_open): Allocate memory for idt_monitor region. If "--board"
1232 option was given, add no monitor by default. Add BREAK hooks only if
1233 monitors are also there.
1235 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1237 * interp.c (sim_monitor): Flush output before reading input.
1239 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1241 * tconfig.in (SIM_HANDLES_LMA): Always define.
1243 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1245 From Mark Salter <msalter@cygnus.com>:
1246 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1247 (sim_open): Add setup for BSP board.
1249 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1251 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1252 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1253 them as unimplemented.
1255 1999-05-08 Felix Lee <flee@cygnus.com>
1257 * configure: Regenerated to track ../common/aclocal.m4 changes.
1259 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1261 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1263 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1265 * configure.in: Any mips64vr5*-*-* target should have
1266 -DTARGET_ENABLE_FR=1.
1267 (default_endian): Any mips64vr*el-*-* target should default to
1269 * configure: Re-generate.
1271 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1273 * mips.igen (ldl): Extend from _16_, not 32.
1275 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1277 * interp.c (sim_store_register): Force registers written to by GDB
1278 into an un-interpreted state.
1280 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1282 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1283 CPU, start periodic background I/O polls.
1284 (tx3904sio_poll): New function: periodic I/O poller.
1286 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1288 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1290 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1292 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1295 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1297 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1298 (load_word): Call SIM_CORE_SIGNAL hook on error.
1299 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1300 starting. For exception dispatching, pass PC instead of NULL_CIA.
1301 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1302 * sim-main.h (COP0_BADVADDR): Define.
1303 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1304 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1305 (_sim_cpu): Add exc_* fields to store register value snapshots.
1306 * mips.igen (*): Replace memory-related SignalException* calls
1307 with references to SIM_CORE_SIGNAL hook.
1309 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1311 * sim-main.c (*): Minor warning cleanups.
1313 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1315 * m16.igen (DADDIU5): Correct type-o.
1317 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1319 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1322 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1324 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1326 (interp.o): Add dependency on itable.h
1327 (oengine.c, gencode): Delete remaining references.
1328 (BUILT_SRC_FROM_GEN): Clean up.
1330 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1333 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1334 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1335 tmp-run-hack) : New.
1336 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1337 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1338 Drop the "64" qualifier to get the HACK generator working.
1339 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1340 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1341 qualifier to get the hack generator working.
1342 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1343 (DSLL): Use do_dsll.
1344 (DSLLV): Use do_dsllv.
1345 (DSRA): Use do_dsra.
1346 (DSRL): Use do_dsrl.
1347 (DSRLV): Use do_dsrlv.
1348 (BC1): Move *vr4100 to get the HACK generator working.
1349 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1350 get the HACK generator working.
1351 (MACC) Rename to get the HACK generator working.
1352 (DMACC,MACCS,DMACCS): Add the 64.
1354 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1356 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1357 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1359 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1361 * mips/interp.c (DEBUG): Cleanups.
1363 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1365 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1366 (tx3904sio_tickle): fflush after a stdout character output.
1368 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1370 * interp.c (sim_close): Uninstall modules.
1372 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1374 * sim-main.h, interp.c (sim_monitor): Change to global
1377 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1379 * configure.in (vr4100): Only include vr4100 instructions in
1381 * configure: Re-generate.
1382 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1384 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1386 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1387 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1390 * configure.in (sim_default_gen, sim_use_gen): Replace with
1392 (--enable-sim-igen): Delete config option. Always using IGEN.
1393 * configure: Re-generate.
1395 * Makefile.in (gencode): Kill, kill, kill.
1398 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1400 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1401 bit mips16 igen simulator.
1402 * configure: Re-generate.
1404 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1405 as part of vr4100 ISA.
1406 * vr.igen: Mark all instructions as 64 bit only.
1408 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1410 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1413 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1415 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1416 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1417 * configure: Re-generate.
1419 * m16.igen (BREAK): Define breakpoint instruction.
1420 (JALX32): Mark instruction as mips16 and not r3900.
1421 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1423 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1425 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1427 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1428 insn as a debug breakpoint.
1430 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1432 (PENDING_SCHED): Clean up trace statement.
1433 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1434 (PENDING_FILL): Delay write by only one cycle.
1435 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1437 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1439 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1441 (pending_tick): Move incrementing of index to FOR statement.
1442 (pending_tick): Only update PENDING_OUT after a write has occured.
1444 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1446 * configure: Re-generate.
1448 * interp.c (sim_engine_run OLD): Delete explicit call to
1449 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1451 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1453 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1454 interrupt level number to match changed SignalExceptionInterrupt
1457 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1459 * interp.c: #include "itable.h" if WITH_IGEN.
1460 (get_insn_name): New function.
1461 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1462 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1464 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1466 * configure: Rebuilt to inhale new common/aclocal.m4.
1468 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1470 * dv-tx3904sio.c: Include sim-assert.h.
1472 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1474 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1475 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1476 Reorganize target-specific sim-hardware checks.
1477 * configure: rebuilt.
1478 * interp.c (sim_open): For tx39 target boards, set
1479 OPERATING_ENVIRONMENT, add tx3904sio devices.
1480 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1481 ROM executables. Install dv-sockser into sim-modules list.
1483 * dv-tx3904irc.c: Compiler warning clean-up.
1484 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1485 frequent hw-trace messages.
1487 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1489 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1491 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1493 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1495 * vr.igen: New file.
1496 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1497 * mips.igen: Define vr4100 model. Include vr.igen.
1498 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1500 * mips.igen (check_mf_hilo): Correct check.
1502 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1504 * sim-main.h (interrupt_event): Add prototype.
1506 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1507 register_ptr, register_value.
1508 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1510 * sim-main.h (tracefh): Make extern.
1512 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1514 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1515 Reduce unnecessarily high timer event frequency.
1516 * dv-tx3904cpu.c: Ditto for interrupt event.
1518 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1520 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1522 (interrupt_event): Made non-static.
1524 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1525 interchange of configuration values for external vs. internal
1528 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1530 * mips.igen (BREAK): Moved code to here for
1531 simulator-reserved break instructions.
1532 * gencode.c (build_instruction): Ditto.
1533 * interp.c (signal_exception): Code moved from here. Non-
1534 reserved instructions now use exception vector, rather
1536 * sim-main.h: Moved magic constants to here.
1538 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1540 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1541 register upon non-zero interrupt event level, clear upon zero
1543 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1544 by passing zero event value.
1545 (*_io_{read,write}_buffer): Endianness fixes.
1546 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1547 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1549 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1550 serial I/O and timer module at base address 0xFFFF0000.
1552 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1554 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1557 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1559 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1561 * configure: Update.
1563 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1565 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1566 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1567 * configure.in: Include tx3904tmr in hw_device list.
1568 * configure: Rebuilt.
1569 * interp.c (sim_open): Instantiate three timer instances.
1570 Fix address typo of tx3904irc instance.
1572 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1574 * interp.c (signal_exception): SystemCall exception now uses
1575 the exception vector.
1577 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1579 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1582 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1584 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1586 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1588 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1590 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1591 sim-main.h. Declare a struct hw_descriptor instead of struct
1592 hw_device_descriptor.
1594 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1596 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1597 right bits and then re-align left hand bytes to correct byte
1598 lanes. Fix incorrect computation in do_store_left when loading
1599 bytes from second word.
1601 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1603 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1604 * interp.c (sim_open): Only create a device tree when HW is
1607 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1608 * interp.c (signal_exception): Ditto.
1610 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1612 * gencode.c: Mark BEGEZALL as LIKELY.
1614 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1616 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1617 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1619 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1621 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1622 modules. Recognize TX39 target with "mips*tx39" pattern.
1623 * configure: Rebuilt.
1624 * sim-main.h (*): Added many macros defining bits in
1625 TX39 control registers.
1626 (SignalInterrupt): Send actual PC instead of NULL.
1627 (SignalNMIReset): New exception type.
1628 * interp.c (board): New variable for future use to identify
1629 a particular board being simulated.
1630 (mips_option_handler,mips_options): Added "--board" option.
1631 (interrupt_event): Send actual PC.
1632 (sim_open): Make memory layout conditional on board setting.
1633 (signal_exception): Initial implementation of hardware interrupt
1634 handling. Accept another break instruction variant for simulator
1636 (decode_coproc): Implement RFE instruction for TX39.
1637 (mips.igen): Decode RFE instruction as such.
1638 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1639 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1640 bbegin to implement memory map.
1641 * dv-tx3904cpu.c: New file.
1642 * dv-tx3904irc.c: New file.
1644 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1646 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1648 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1650 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1651 with calls to check_div_hilo.
1653 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1655 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1656 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1657 Add special r3900 version of do_mult_hilo.
1658 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1659 with calls to check_mult_hilo.
1660 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1661 with calls to check_div_hilo.
1663 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1665 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1666 Document a replacement.
1668 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1670 * interp.c (sim_monitor): Make mon_printf work.
1672 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1674 * sim-main.h (INSN_NAME): New arg `cpu'.
1676 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1678 * configure: Regenerated to track ../common/aclocal.m4 changes.
1680 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1682 * configure: Regenerated to track ../common/aclocal.m4 changes.
1685 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1687 * acconfig.h: New file.
1688 * configure.in: Reverted change of Apr 24; use sinclude again.
1690 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1692 * configure: Regenerated to track ../common/aclocal.m4 changes.
1695 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1697 * configure.in: Don't call sinclude.
1699 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1701 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1703 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1705 * mips.igen (ERET): Implement.
1707 * interp.c (decode_coproc): Return sign-extended EPC.
1709 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1711 * interp.c (signal_exception): Do not ignore Trap.
1712 (signal_exception): On TRAP, restart at exception address.
1713 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1714 (signal_exception): Update.
1715 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1716 so that TRAP instructions are caught.
1718 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1720 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1721 contains HI/LO access history.
1722 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1723 (HIACCESS, LOACCESS): Delete, replace with
1724 (HIHISTORY, LOHISTORY): New macros.
1725 (CHECKHILO): Delete all, moved to mips.igen
1727 * gencode.c (build_instruction): Do not generate checks for
1728 correct HI/LO register usage.
1730 * interp.c (old_engine_run): Delete checks for correct HI/LO
1733 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1734 check_mf_cycles): New functions.
1735 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1736 do_divu, domultx, do_mult, do_multu): Use.
1738 * tx.igen ("madd", "maddu"): Use.
1740 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1742 * mips.igen (DSRAV): Use function do_dsrav.
1743 (SRAV): Use new function do_srav.
1745 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1746 (B): Sign extend 11 bit immediate.
1747 (EXT-B*): Shift 16 bit immediate left by 1.
1748 (ADDIU*): Don't sign extend immediate value.
1750 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1752 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1754 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1757 * mips.igen (delayslot32, nullify_next_insn): New functions.
1758 (m16.igen): Always include.
1759 (do_*): Add more tracing.
1761 * m16.igen (delayslot16): Add NIA argument, could be called by a
1762 32 bit MIPS16 instruction.
1764 * interp.c (ifetch16): Move function from here.
1765 * sim-main.c (ifetch16): To here.
1767 * sim-main.c (ifetch16, ifetch32): Update to match current
1768 implementations of LH, LW.
1769 (signal_exception): Don't print out incorrect hex value of illegal
1772 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1774 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1777 * m16.igen: Implement MIPS16 instructions.
1779 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1780 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1781 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1782 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1783 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1784 bodies of corresponding code from 32 bit insn to these. Also used
1785 by MIPS16 versions of functions.
1787 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1788 (IMEM16): Drop NR argument from macro.
1790 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1792 * Makefile.in (SIM_OBJS): Add sim-main.o.
1794 * sim-main.h (address_translation, load_memory, store_memory,
1795 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1797 (pr_addr, pr_uword64): Declare.
1798 (sim-main.c): Include when H_REVEALS_MODULE_P.
1800 * interp.c (address_translation, load_memory, store_memory,
1801 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1803 * sim-main.c: To here. Fix compilation problems.
1805 * configure.in: Enable inlining.
1806 * configure: Re-config.
1808 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1810 * configure: Regenerated to track ../common/aclocal.m4 changes.
1812 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1814 * mips.igen: Include tx.igen.
1815 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1816 * tx.igen: New file, contains MADD and MADDU.
1818 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1819 the hardwired constant `7'.
1820 (store_memory): Ditto.
1821 (LOADDRMASK): Move definition to sim-main.h.
1823 mips.igen (MTC0): Enable for r3900.
1826 mips.igen (do_load_byte): Delete.
1827 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1828 do_store_right): New functions.
1829 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1831 configure.in: Let the tx39 use igen again.
1834 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1836 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1837 not an address sized quantity. Return zero for cache sizes.
1839 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1841 * mips.igen (r3900): r3900 does not support 64 bit integer
1844 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1846 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1848 * configure : Rebuild.
1850 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1852 * configure: Regenerated to track ../common/aclocal.m4 changes.
1854 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1856 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1858 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1860 * configure: Regenerated to track ../common/aclocal.m4 changes.
1861 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1863 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1865 * configure: Regenerated to track ../common/aclocal.m4 changes.
1867 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1869 * interp.c (Max, Min): Comment out functions. Not yet used.
1871 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1873 * configure: Regenerated to track ../common/aclocal.m4 changes.
1875 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1877 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1878 configurable settings for stand-alone simulator.
1880 * configure.in: Added X11 search, just in case.
1882 * configure: Regenerated.
1884 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1886 * interp.c (sim_write, sim_read, load_memory, store_memory):
1887 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1889 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1891 * sim-main.h (GETFCC): Return an unsigned value.
1893 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1895 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1896 (DADD): Result destination is RD not RT.
1898 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1900 * sim-main.h (HIACCESS, LOACCESS): Always define.
1902 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1904 * interp.c (sim_info): Delete.
1906 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1908 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1909 (mips_option_handler): New argument `cpu'.
1910 (sim_open): Update call to sim_add_option_table.
1912 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1914 * mips.igen (CxC1): Add tracing.
1916 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1918 * sim-main.h (Max, Min): Declare.
1920 * interp.c (Max, Min): New functions.
1922 * mips.igen (BC1): Add tracing.
1924 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1926 * interp.c Added memory map for stack in vr4100
1928 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1930 * interp.c (load_memory): Add missing "break"'s.
1932 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1934 * interp.c (sim_store_register, sim_fetch_register): Pass in
1935 length parameter. Return -1.
1937 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1939 * interp.c: Added hardware init hook, fixed warnings.
1941 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1943 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1945 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1947 * interp.c (ifetch16): New function.
1949 * sim-main.h (IMEM32): Rename IMEM.
1950 (IMEM16_IMMED): Define.
1952 (DELAY_SLOT): Update.
1954 * m16run.c (sim_engine_run): New file.
1956 * m16.igen: All instructions except LB.
1957 (LB): Call do_load_byte.
1958 * mips.igen (do_load_byte): New function.
1959 (LB): Call do_load_byte.
1961 * mips.igen: Move spec for insn bit size and high bit from here.
1962 * Makefile.in (tmp-igen, tmp-m16): To here.
1964 * m16.dc: New file, decode mips16 instructions.
1966 * Makefile.in (SIM_NO_ALL): Define.
1967 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1969 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1971 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1972 point unit to 32 bit registers.
1973 * configure: Re-generate.
1975 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1977 * configure.in (sim_use_gen): Make IGEN the default simulator
1978 generator for generic 32 and 64 bit mips targets.
1979 * configure: Re-generate.
1981 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1983 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1986 * interp.c (sim_fetch_register, sim_store_register): Read/write
1987 FGR from correct location.
1988 (sim_open): Set size of FGR's according to
1989 WITH_TARGET_FLOATING_POINT_BITSIZE.
1991 * sim-main.h (FGR): Store floating point registers in a separate
1994 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1996 * configure: Regenerated to track ../common/aclocal.m4 changes.
1998 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2000 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2002 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2004 * interp.c (pending_tick): New function. Deliver pending writes.
2006 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2007 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2008 it can handle mixed sized quantites and single bits.
2010 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2012 * interp.c (oengine.h): Do not include when building with IGEN.
2013 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2014 (sim_info): Ditto for PROCESSOR_64BIT.
2015 (sim_monitor): Replace ut_reg with unsigned_word.
2016 (*): Ditto for t_reg.
2017 (LOADDRMASK): Define.
2018 (sim_open): Remove defunct check that host FP is IEEE compliant,
2019 using software to emulate floating point.
2020 (value_fpr, ...): Always compile, was conditional on HASFPU.
2022 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2024 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2027 * interp.c (SD, CPU): Define.
2028 (mips_option_handler): Set flags in each CPU.
2029 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2030 (sim_close): Do not clear STATE, deleted anyway.
2031 (sim_write, sim_read): Assume CPU zero's vm should be used for
2033 (sim_create_inferior): Set the PC for all processors.
2034 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2036 (mips16_entry): Pass correct nr of args to store_word, load_word.
2037 (ColdReset): Cold reset all cpu's.
2038 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2039 (sim_monitor, load_memory, store_memory, signal_exception): Use
2040 `CPU' instead of STATE_CPU.
2043 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2046 * sim-main.h (signal_exception): Add sim_cpu arg.
2047 (SignalException*): Pass both SD and CPU to signal_exception.
2048 * interp.c (signal_exception): Update.
2050 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2052 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2053 address_translation): Ditto
2054 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2056 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2058 * configure: Regenerated to track ../common/aclocal.m4 changes.
2060 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2062 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2064 * mips.igen (model): Map processor names onto BFD name.
2066 * sim-main.h (CPU_CIA): Delete.
2067 (SET_CIA, GET_CIA): Define
2069 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2071 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2074 * configure.in (default_endian): Configure a big-endian simulator
2076 * configure: Re-generate.
2078 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2080 * configure: Regenerated to track ../common/aclocal.m4 changes.
2082 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2084 * interp.c (sim_monitor): Handle Densan monitor outbyte
2085 and inbyte functions.
2087 1997-12-29 Felix Lee <flee@cygnus.com>
2089 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2091 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2093 * Makefile.in (tmp-igen): Arrange for $zero to always be
2094 reset to zero after every instruction.
2096 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2098 * configure: Regenerated to track ../common/aclocal.m4 changes.
2101 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2103 * mips.igen (MSUB): Fix to work like MADD.
2104 * gencode.c (MSUB): Similarly.
2106 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2108 * configure: Regenerated to track ../common/aclocal.m4 changes.
2110 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2112 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2114 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2116 * sim-main.h (sim-fpu.h): Include.
2118 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2119 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2120 using host independant sim_fpu module.
2122 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2124 * interp.c (signal_exception): Report internal errors with SIGABRT
2127 * sim-main.h (C0_CONFIG): New register.
2128 (signal.h): No longer include.
2130 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2132 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2134 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2136 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2138 * mips.igen: Tag vr5000 instructions.
2139 (ANDI): Was missing mipsIV model, fix assembler syntax.
2140 (do_c_cond_fmt): New function.
2141 (C.cond.fmt): Handle mips I-III which do not support CC field
2143 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2144 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2146 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2147 vr5000 which saves LO in a GPR separatly.
2149 * configure.in (enable-sim-igen): For vr5000, select vr5000
2150 specific instructions.
2151 * configure: Re-generate.
2153 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2155 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2157 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2158 fmt_uninterpreted_64 bit cases to switch. Convert to
2161 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2163 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2164 as specified in IV3.2 spec.
2165 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2167 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2169 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2170 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2171 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2172 PENDING_FILL versions of instructions. Simplify.
2174 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2176 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2178 (MTHI, MFHI): Disable code checking HI-LO.
2180 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2182 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2184 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2186 * gencode.c (build_mips16_operands): Replace IPC with cia.
2188 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2189 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2191 (UndefinedResult): Replace function with macro/function
2193 (sim_engine_run): Don't save PC in IPC.
2195 * sim-main.h (IPC): Delete.
2198 * interp.c (signal_exception, store_word, load_word,
2199 address_translation, load_memory, store_memory, cache_op,
2200 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2201 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2202 current instruction address - cia - argument.
2203 (sim_read, sim_write): Call address_translation directly.
2204 (sim_engine_run): Rename variable vaddr to cia.
2205 (signal_exception): Pass cia to sim_monitor
2207 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2208 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2209 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2211 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2212 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2215 * interp.c (signal_exception): Pass restart address to
2218 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2219 idecode.o): Add dependency.
2221 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2223 (DELAY_SLOT): Update NIA not PC with branch address.
2224 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2226 * mips.igen: Use CIA not PC in branch calculations.
2227 (illegal): Call SignalException.
2228 (BEQ, ADDIU): Fix assembler.
2230 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2232 * m16.igen (JALX): Was missing.
2234 * configure.in (enable-sim-igen): New configuration option.
2235 * configure: Re-generate.
2237 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2239 * interp.c (load_memory, store_memory): Delete parameter RAW.
2240 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2241 bypassing {load,store}_memory.
2243 * sim-main.h (ByteSwapMem): Delete definition.
2245 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2247 * interp.c (sim_do_command, sim_commands): Delete mips specific
2248 commands. Handled by module sim-options.
2250 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2251 (WITH_MODULO_MEMORY): Define.
2253 * interp.c (sim_info): Delete code printing memory size.
2255 * interp.c (mips_size): Nee sim_size, delete function.
2257 (monitor, monitor_base, monitor_size): Delete global variables.
2258 (sim_open, sim_close): Delete code creating monitor and other
2259 memory regions. Use sim-memopts module, via sim_do_commandf, to
2260 manage memory regions.
2261 (load_memory, store_memory): Use sim-core for memory model.
2263 * interp.c (address_translation): Delete all memory map code
2264 except line forcing 32 bit addresses.
2266 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2268 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2271 * interp.c (logfh, logfile): Delete globals.
2272 (sim_open, sim_close): Delete code opening & closing log file.
2273 (mips_option_handler): Delete -l and -n options.
2274 (OPTION mips_options): Ditto.
2276 * interp.c (OPTION mips_options): Rename option trace to dinero.
2277 (mips_option_handler): Update.
2279 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2281 * interp.c (fetch_str): New function.
2282 (sim_monitor): Rewrite using sim_read & sim_write.
2283 (sim_open): Check magic number.
2284 (sim_open): Write monitor vectors into memory using sim_write.
2285 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2286 (sim_read, sim_write): Simplify - transfer data one byte at a
2288 (load_memory, store_memory): Clarify meaning of parameter RAW.
2290 * sim-main.h (isHOST): Defete definition.
2291 (isTARGET): Mark as depreciated.
2292 (address_translation): Delete parameter HOST.
2294 * interp.c (address_translation): Delete parameter HOST.
2296 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2300 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2301 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2303 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2305 * mips.igen: Add model filter field to records.
2307 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2309 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2311 interp.c (sim_engine_run): Do not compile function sim_engine_run
2312 when WITH_IGEN == 1.
2314 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2315 target architecture.
2317 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2318 igen. Replace with configuration variables sim_igen_flags /
2321 * m16.igen: New file. Copy mips16 insns here.
2322 * mips.igen: From here.
2324 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2326 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2328 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2330 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2332 * gencode.c (build_instruction): Follow sim_write's lead in using
2333 BigEndianMem instead of !ByteSwapMem.
2335 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2337 * configure.in (sim_gen): Dependent on target, select type of
2338 generator. Always select old style generator.
2340 configure: Re-generate.
2342 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2344 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2345 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2346 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2347 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2348 SIM_@sim_gen@_*, set by autoconf.
2350 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2352 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2354 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2355 CURRENT_FLOATING_POINT instead.
2357 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2358 (address_translation): Raise exception InstructionFetch when
2359 translation fails and isINSTRUCTION.
2361 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2362 sim_engine_run): Change type of of vaddr and paddr to
2364 (address_translation, prefetch, load_memory, store_memory,
2365 cache_op): Change type of vAddr and pAddr to address_word.
2367 * gencode.c (build_instruction): Change type of vaddr and paddr to
2370 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2372 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2373 macro to obtain result of ALU op.
2375 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2377 * interp.c (sim_info): Call profile_print.
2379 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2381 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2383 * sim-main.h (WITH_PROFILE): Do not define, defined in
2384 common/sim-config.h. Use sim-profile module.
2385 (simPROFILE): Delete defintion.
2387 * interp.c (PROFILE): Delete definition.
2388 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2389 (sim_close): Delete code writing profile histogram.
2390 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2392 (sim_engine_run): Delete code profiling the PC.
2394 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2396 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2398 * interp.c (sim_monitor): Make register pointers of type
2401 * sim-main.h: Make registers of type unsigned_word not
2404 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2406 * interp.c (sync_operation): Rename from SyncOperation, make
2407 global, add SD argument.
2408 (prefetch): Rename from Prefetch, make global, add SD argument.
2409 (decode_coproc): Make global.
2411 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2413 * gencode.c (build_instruction): Generate DecodeCoproc not
2414 decode_coproc calls.
2416 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2417 (SizeFGR): Move to sim-main.h
2418 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2419 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2420 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2422 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2423 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2424 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2425 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2426 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2427 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2429 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2431 (sim-alu.h): Include.
2432 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2433 (sim_cia): Typedef to instruction_address.
2435 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2437 * Makefile.in (interp.o): Rename generated file engine.c to
2442 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2444 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2446 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2448 * gencode.c (build_instruction): For "FPSQRT", output correct
2449 number of arguments to Recip.
2451 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2453 * Makefile.in (interp.o): Depends on sim-main.h
2455 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2457 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2458 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2459 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2460 STATE, DSSTATE): Define
2461 (GPR, FGRIDX, ..): Define.
2463 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2464 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2465 (GPR, FGRIDX, ...): Delete macros.
2467 * interp.c: Update names to match defines from sim-main.h
2469 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2471 * interp.c (sim_monitor): Add SD argument.
2472 (sim_warning): Delete. Replace calls with calls to
2474 (sim_error): Delete. Replace calls with sim_io_error.
2475 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2476 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2477 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2479 (mips_size): Rename from sim_size. Add SD argument.
2481 * interp.c (simulator): Delete global variable.
2482 (callback): Delete global variable.
2483 (mips_option_handler, sim_open, sim_write, sim_read,
2484 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2485 sim_size,sim_monitor): Use sim_io_* not callback->*.
2486 (sim_open): ZALLOC simulator struct.
2487 (PROFILE): Do not define.
2489 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2491 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2492 support.h with corresponding code.
2494 * sim-main.h (word64, uword64), support.h: Move definition to
2496 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2499 * Makefile.in: Update dependencies
2500 * interp.c: Do not include.
2502 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2504 * interp.c (address_translation, load_memory, store_memory,
2505 cache_op): Rename to from AddressTranslation et.al., make global,
2508 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2511 * interp.c (SignalException): Rename to signal_exception, make
2514 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2516 * sim-main.h (SignalException, SignalExceptionInterrupt,
2517 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2518 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2519 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2522 * interp.c, support.h: Use.
2524 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2526 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2527 to value_fpr / store_fpr. Add SD argument.
2528 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2529 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2531 * sim-main.h (ValueFPR, StoreFPR): Define.
2533 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2535 * interp.c (sim_engine_run): Check consistency between configure
2536 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2539 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2540 (mips_fpu): Configure WITH_FLOATING_POINT.
2541 (mips_endian): Configure WITH_TARGET_ENDIAN.
2542 * configure: Update.
2544 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2546 * configure: Regenerated to track ../common/aclocal.m4 changes.
2548 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2550 * configure: Regenerated.
2552 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2554 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2556 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2558 * gencode.c (print_igen_insn_models): Assume certain architectures
2559 include all mips* instructions.
2560 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2563 * Makefile.in (tmp.igen): Add target. Generate igen input from
2566 * gencode.c (FEATURE_IGEN): Define.
2567 (main): Add --igen option. Generate output in igen format.
2568 (process_instructions): Format output according to igen option.
2569 (print_igen_insn_format): New function.
2570 (print_igen_insn_models): New function.
2571 (process_instructions): Only issue warnings and ignore
2572 instructions when no FEATURE_IGEN.
2574 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2576 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2579 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2581 * configure: Regenerated to track ../common/aclocal.m4 changes.
2583 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2585 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2586 SIM_RESERVED_BITS): Delete, moved to common.
2587 (SIM_EXTRA_CFLAGS): Update.
2589 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2591 * configure.in: Configure non-strict memory alignment.
2592 * configure: Regenerated to track ../common/aclocal.m4 changes.
2594 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2596 * configure: Regenerated to track ../common/aclocal.m4 changes.
2598 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2600 * gencode.c (SDBBP,DERET): Added (3900) insns.
2601 (RFE): Turn on for 3900.
2602 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2603 (dsstate): Made global.
2604 (SUBTARGET_R3900): Added.
2605 (CANCELDELAYSLOT): New.
2606 (SignalException): Ignore SystemCall rather than ignore and
2607 terminate. Add DebugBreakPoint handling.
2608 (decode_coproc): New insns RFE, DERET; and new registers Debug
2609 and DEPC protected by SUBTARGET_R3900.
2610 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2612 * Makefile.in,configure.in: Add mips subtarget option.
2613 * configure: Update.
2615 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2617 * gencode.c: Add r3900 (tx39).
2620 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2622 * gencode.c (build_instruction): Don't need to subtract 4 for
2625 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2627 * interp.c: Correct some HASFPU problems.
2629 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2631 * configure: Regenerated to track ../common/aclocal.m4 changes.
2633 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2635 * interp.c (mips_options): Fix samples option short form, should
2638 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2640 * interp.c (sim_info): Enable info code. Was just returning.
2642 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2644 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2647 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2649 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2651 (build_instruction): Ditto for LL.
2653 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2655 * configure: Regenerated to track ../common/aclocal.m4 changes.
2657 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2659 * configure: Regenerated to track ../common/aclocal.m4 changes.
2662 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2664 * interp.c (sim_open): Add call to sim_analyze_program, update
2667 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2669 * interp.c (sim_kill): Delete.
2670 (sim_create_inferior): Add ABFD argument. Set PC from same.
2671 (sim_load): Move code initializing trap handlers from here.
2672 (sim_open): To here.
2673 (sim_load): Delete, use sim-hload.c.
2675 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2677 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2679 * configure: Regenerated to track ../common/aclocal.m4 changes.
2682 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2684 * interp.c (sim_open): Add ABFD argument.
2685 (sim_load): Move call to sim_config from here.
2686 (sim_open): To here. Check return status.
2688 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2690 * gencode.c (build_instruction): Two arg MADD should
2691 not assign result to $0.
2693 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2695 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2696 * sim/mips/configure.in: Regenerate.
2698 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2700 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2701 signed8, unsigned8 et.al. types.
2703 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2704 hosts when selecting subreg.
2706 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2708 * interp.c (sim_engine_run): Reset the ZERO register to zero
2709 regardless of FEATURE_WARN_ZERO.
2710 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2712 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2714 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2715 (SignalException): For BreakPoints ignore any mode bits and just
2717 (SignalException): Always set the CAUSE register.
2719 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2721 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2722 exception has been taken.
2724 * interp.c: Implement the ERET and mt/f sr instructions.
2726 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2728 * interp.c (SignalException): Don't bother restarting an
2731 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2733 * interp.c (SignalException): Really take an interrupt.
2734 (interrupt_event): Only deliver interrupts when enabled.
2736 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2738 * interp.c (sim_info): Only print info when verbose.
2739 (sim_info) Use sim_io_printf for output.
2741 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2743 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2746 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2748 * interp.c (sim_do_command): Check for common commands if a
2749 simulator specific command fails.
2751 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2753 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2754 and simBE when DEBUG is defined.
2756 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2758 * interp.c (interrupt_event): New function. Pass exception event
2759 onto exception handler.
2761 * configure.in: Check for stdlib.h.
2762 * configure: Regenerate.
2764 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2765 variable declaration.
2766 (build_instruction): Initialize memval1.
2767 (build_instruction): Add UNUSED attribute to byte, bigend,
2769 (build_operands): Ditto.
2771 * interp.c: Fix GCC warnings.
2772 (sim_get_quit_code): Delete.
2774 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2775 * Makefile.in: Ditto.
2776 * configure: Re-generate.
2778 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2780 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2782 * interp.c (mips_option_handler): New function parse argumes using
2784 (myname): Replace with STATE_MY_NAME.
2785 (sim_open): Delete check for host endianness - performed by
2787 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2788 (sim_open): Move much of the initialization from here.
2789 (sim_load): To here. After the image has been loaded and
2791 (sim_open): Move ColdReset from here.
2792 (sim_create_inferior): To here.
2793 (sim_open): Make FP check less dependant on host endianness.
2795 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2797 * interp.c (sim_set_callbacks): Delete.
2799 * interp.c (membank, membank_base, membank_size): Replace with
2800 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2801 (sim_open): Remove call to callback->init. gdb/run do this.
2805 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2807 * interp.c (big_endian_p): Delete, replaced by
2808 current_target_byte_order.
2810 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2812 * interp.c (host_read_long, host_read_word, host_swap_word,
2813 host_swap_long): Delete. Using common sim-endian.
2814 (sim_fetch_register, sim_store_register): Use H2T.
2815 (pipeline_ticks): Delete. Handled by sim-events.
2817 (sim_engine_run): Update.
2819 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2821 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2823 (SignalException): To here. Signal using sim_engine_halt.
2824 (sim_stop_reason): Delete, moved to common.
2826 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2828 * interp.c (sim_open): Add callback argument.
2829 (sim_set_callbacks): Delete SIM_DESC argument.
2832 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2834 * Makefile.in (SIM_OBJS): Add common modules.
2836 * interp.c (sim_set_callbacks): Also set SD callback.
2837 (set_endianness, xfer_*, swap_*): Delete.
2838 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2839 Change to functions using sim-endian macros.
2840 (control_c, sim_stop): Delete, use common version.
2841 (simulate): Convert into.
2842 (sim_engine_run): This function.
2843 (sim_resume): Delete.
2845 * interp.c (simulation): New variable - the simulator object.
2846 (sim_kind): Delete global - merged into simulation.
2847 (sim_load): Cleanup. Move PC assignment from here.
2848 (sim_create_inferior): To here.
2850 * sim-main.h: New file.
2851 * interp.c (sim-main.h): Include.
2853 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2855 * configure: Regenerated to track ../common/aclocal.m4 changes.
2857 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2859 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2861 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2863 * gencode.c (build_instruction): DIV instructions: check
2864 for division by zero and integer overflow before using
2865 host's division operation.
2867 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2869 * Makefile.in (SIM_OBJS): Add sim-load.o.
2870 * interp.c: #include bfd.h.
2871 (target_byte_order): Delete.
2872 (sim_kind, myname, big_endian_p): New static locals.
2873 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2874 after argument parsing. Recognize -E arg, set endianness accordingly.
2875 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2876 load file into simulator. Set PC from bfd.
2877 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2878 (set_endianness): Use big_endian_p instead of target_byte_order.
2880 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2882 * interp.c (sim_size): Delete prototype - conflicts with
2883 definition in remote-sim.h. Correct definition.
2885 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2887 * configure: Regenerated to track ../common/aclocal.m4 changes.
2890 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2892 * interp.c (sim_open): New arg `kind'.
2894 * configure: Regenerated to track ../common/aclocal.m4 changes.
2896 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2898 * configure: Regenerated to track ../common/aclocal.m4 changes.
2900 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2902 * interp.c (sim_open): Set optind to 0 before calling getopt.
2904 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2906 * configure: Regenerated to track ../common/aclocal.m4 changes.
2908 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2910 * interp.c : Replace uses of pr_addr with pr_uword64
2911 where the bit length is always 64 independent of SIM_ADDR.
2912 (pr_uword64) : added.
2914 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2916 * configure: Re-generate.
2918 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2920 * configure: Regenerate to track ../common/aclocal.m4 changes.
2922 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2924 * interp.c (sim_open): New SIM_DESC result. Argument is now
2926 (other sim_*): New SIM_DESC argument.
2928 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2930 * interp.c: Fix printing of addresses for non-64-bit targets.
2931 (pr_addr): Add function to print address based on size.
2933 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2935 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2937 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2939 * gencode.c (build_mips16_operands): Correct computation of base
2940 address for extended PC relative instruction.
2942 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2944 * interp.c (mips16_entry): Add support for floating point cases.
2945 (SignalException): Pass floating point cases to mips16_entry.
2946 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2948 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2950 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2951 and then set the state to fmt_uninterpreted.
2952 (COP_SW): Temporarily set the state to fmt_word while calling
2955 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2957 * gencode.c (build_instruction): The high order may be set in the
2958 comparison flags at any ISA level, not just ISA 4.
2960 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2962 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2963 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2964 * configure.in: sinclude ../common/aclocal.m4.
2965 * configure: Regenerated.
2967 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2969 * configure: Rebuild after change to aclocal.m4.
2971 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2973 * configure configure.in Makefile.in: Update to new configure
2974 scheme which is more compatible with WinGDB builds.
2975 * configure.in: Improve comment on how to run autoconf.
2976 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2977 * Makefile.in: Use autoconf substitution to install common
2980 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2982 * gencode.c (build_instruction): Use BigEndianCPU instead of
2985 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2987 * interp.c (sim_monitor): Make output to stdout visible in
2988 wingdb's I/O log window.
2990 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2992 * support.h: Undo previous change to SIGTRAP
2995 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2997 * interp.c (store_word, load_word): New static functions.
2998 (mips16_entry): New static function.
2999 (SignalException): Look for mips16 entry and exit instructions.
3000 (simulate): Use the correct index when setting fpr_state after
3001 doing a pending move.
3003 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3005 * interp.c: Fix byte-swapping code throughout to work on
3006 both little- and big-endian hosts.
3008 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3010 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3011 with gdb/config/i386/xm-windows.h.
3013 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3015 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3016 that messes up arithmetic shifts.
3018 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3020 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3021 SIGTRAP and SIGQUIT for _WIN32.
3023 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3025 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3026 force a 64 bit multiplication.
3027 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3028 destination register is 0, since that is the default mips16 nop
3031 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3033 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3034 (build_endian_shift): Don't check proc64.
3035 (build_instruction): Always set memval to uword64. Cast op2 to
3036 uword64 when shifting it left in memory instructions. Always use
3037 the same code for stores--don't special case proc64.
3039 * gencode.c (build_mips16_operands): Fix base PC value for PC
3041 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3043 * interp.c (simJALDELAYSLOT): Define.
3044 (JALDELAYSLOT): Define.
3045 (INDELAYSLOT, INJALDELAYSLOT): Define.
3046 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3048 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3050 * interp.c (sim_open): add flush_cache as a PMON routine
3051 (sim_monitor): handle flush_cache by ignoring it
3053 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3055 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3057 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3058 (BigEndianMem): Rename to ByteSwapMem and change sense.
3059 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3060 BigEndianMem references to !ByteSwapMem.
3061 (set_endianness): New function, with prototype.
3062 (sim_open): Call set_endianness.
3063 (sim_info): Use simBE instead of BigEndianMem.
3064 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3065 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3066 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3067 ifdefs, keeping the prototype declaration.
3068 (swap_word): Rewrite correctly.
3069 (ColdReset): Delete references to CONFIG. Delete endianness related
3070 code; moved to set_endianness.
3072 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3074 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3075 * interp.c (CHECKHILO): Define away.
3076 (simSIGINT): New macro.
3077 (membank_size): Increase from 1MB to 2MB.
3078 (control_c): New function.
3079 (sim_resume): Rename parameter signal to signal_number. Add local
3080 variable prev. Call signal before and after simulate.
3081 (sim_stop_reason): Add simSIGINT support.
3082 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3084 (sim_warning): Delete call to SignalException. Do call printf_filtered
3086 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3087 a call to sim_warning.
3089 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3091 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3092 16 bit instructions.
3094 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3096 Add support for mips16 (16 bit MIPS implementation):
3097 * gencode.c (inst_type): Add mips16 instruction encoding types.
3098 (GETDATASIZEINSN): Define.
3099 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3100 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3102 (MIPS16_DECODE): New table, for mips16 instructions.
3103 (bitmap_val): New static function.
3104 (struct mips16_op): Define.
3105 (mips16_op_table): New table, for mips16 operands.
3106 (build_mips16_operands): New static function.
3107 (process_instructions): If PC is odd, decode a mips16
3108 instruction. Break out instruction handling into new
3109 build_instruction function.
3110 (build_instruction): New static function, broken out of
3111 process_instructions. Check modifiers rather than flags for SHIFT
3112 bit count and m[ft]{hi,lo} direction.
3113 (usage): Pass program name to fprintf.
3114 (main): Remove unused variable this_option_optind. Change
3115 ``*loptarg++'' to ``loptarg++''.
3116 (my_strtoul): Parenthesize && within ||.
3117 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3118 (simulate): If PC is odd, fetch a 16 bit instruction, and
3119 increment PC by 2 rather than 4.
3120 * configure.in: Add case for mips16*-*-*.
3121 * configure: Rebuild.
3123 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3125 * interp.c: Allow -t to enable tracing in standalone simulator.
3126 Fix garbage output in trace file and error messages.
3128 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3130 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3131 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3132 * configure.in: Simplify using macros in ../common/aclocal.m4.
3133 * configure: Regenerated.
3134 * tconfig.in: New file.
3136 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3138 * interp.c: Fix bugs in 64-bit port.
3139 Use ansi function declarations for msvc compiler.
3140 Initialize and test file pointer in trace code.
3141 Prevent duplicate definition of LAST_EMED_REGNUM.
3143 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3145 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3147 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3149 * interp.c (SignalException): Check for explicit terminating
3151 * gencode.c: Pass instruction value through SignalException()
3152 calls for Trap, Breakpoint and Syscall.
3154 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3156 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3157 only used on those hosts that provide it.
3158 * configure.in: Add sqrt() to list of functions to be checked for.
3159 * config.in: Re-generated.
3160 * configure: Re-generated.
3162 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3164 * gencode.c (process_instructions): Call build_endian_shift when
3165 expanding STORE RIGHT, to fix swr.
3166 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3167 clear the high bits.
3168 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3169 Fix float to int conversions to produce signed values.
3171 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3173 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3174 (process_instructions): Correct handling of nor instruction.
3175 Correct shift count for 32 bit shift instructions. Correct sign
3176 extension for arithmetic shifts to not shift the number of bits in
3177 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3178 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3180 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3181 It's OK to have a mult follow a mult. What's not OK is to have a
3182 mult follow an mfhi.
3183 (Convert): Comment out incorrect rounding code.
3185 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3187 * interp.c (sim_monitor): Improved monitor printf
3188 simulation. Tidied up simulator warnings, and added "--log" option
3189 for directing warning message output.
3190 * gencode.c: Use sim_warning() rather than WARNING macro.
3192 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3194 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3195 getopt1.o, rather than on gencode.c. Link objects together.
3196 Don't link against -liberty.
3197 (gencode.o, getopt.o, getopt1.o): New targets.
3198 * gencode.c: Include <ctype.h> and "ansidecl.h".
3199 (AND): Undefine after including "ansidecl.h".
3200 (ULONG_MAX): Define if not defined.
3201 (OP_*): Don't define macros; now defined in opcode/mips.h.
3202 (main): Call my_strtoul rather than strtoul.
3203 (my_strtoul): New static function.
3205 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3207 * gencode.c (process_instructions): Generate word64 and uword64
3208 instead of `long long' and `unsigned long long' data types.
3209 * interp.c: #include sysdep.h to get signals, and define default
3211 * (Convert): Work around for Visual-C++ compiler bug with type
3213 * support.h: Make things compile under Visual-C++ by using
3214 __int64 instead of `long long'. Change many refs to long long
3215 into word64/uword64 typedefs.
3217 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3219 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3220 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3222 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3223 (AC_PROG_INSTALL): Added.
3224 (AC_PROG_CC): Moved to before configure.host call.
3225 * configure: Rebuilt.
3227 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3229 * configure.in: Define @SIMCONF@ depending on mips target.
3230 * configure: Rebuild.
3231 * Makefile.in (run): Add @SIMCONF@ to control simulator
3233 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3234 * interp.c: Remove some debugging, provide more detailed error
3235 messages, update memory accesses to use LOADDRMASK.
3237 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3239 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3240 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3242 * configure: Rebuild.
3243 * config.in: New file, generated by autoheader.
3244 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3245 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3246 HAVE_ANINT and HAVE_AINT, as appropriate.
3247 * Makefile.in (run): Use @LIBS@ rather than -lm.
3248 (interp.o): Depend upon config.h.
3249 (Makefile): Just rebuild Makefile.
3250 (clean): Remove stamp-h.
3251 (mostlyclean): Make the same as clean, not as distclean.
3252 (config.h, stamp-h): New targets.
3254 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3256 * interp.c (ColdReset): Fix boolean test. Make all simulator
3259 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3261 * interp.c (xfer_direct_word, xfer_direct_long,
3262 swap_direct_word, swap_direct_long, xfer_big_word,
3263 xfer_big_long, xfer_little_word, xfer_little_long,
3264 swap_word,swap_long): Added.
3265 * interp.c (ColdReset): Provide function indirection to
3266 host<->simulated_target transfer routines.
3267 * interp.c (sim_store_register, sim_fetch_register): Updated to
3268 make use of indirected transfer routines.
3270 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3272 * gencode.c (process_instructions): Ensure FP ABS instruction
3274 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3275 system call support.
3277 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3279 * interp.c (sim_do_command): Complain if callback structure not
3282 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3284 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3285 support for Sun hosts.
3286 * Makefile.in (gencode): Ensure the host compiler and libraries
3287 used for cross-hosted build.
3289 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3291 * interp.c, gencode.c: Some more (TODO) tidying.
3293 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3295 * gencode.c, interp.c: Replaced explicit long long references with
3296 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3297 * support.h (SET64LO, SET64HI): Macros added.
3299 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3301 * configure: Regenerate with autoconf 2.7.
3303 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3305 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3306 * support.h: Remove superfluous "1" from #if.
3307 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3309 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3311 * interp.c (StoreFPR): Control UndefinedResult() call on
3312 WARN_RESULT manifest.
3314 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3316 * gencode.c: Tidied instruction decoding, and added FP instruction
3319 * interp.c: Added dineroIII, and BSD profiling support. Also
3320 run-time FP handling.
3322 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3324 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3325 gencode.c, interp.c, support.h: created.