1 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
3 * interp.c: Move FPU support routines from here to...
4 * cp1.c: Here. New file.
5 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
8 2002-03-12 Chris Demetriou <cgd@broadcom.com>
10 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
11 * mips.igen (mips32, mips64): New models, add to all instructions
12 and functions as appropriate.
13 (loadstore_ea, check_u64): New variant for model mips64.
14 (check_fmt_p): New variant for models mipsV and mips64, remove
15 mipsV model marking fro other variant.
18 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
19 for mips32 and mips64.
20 (DCLO, DCLZ): New instructions for mips64.
22 2002-03-07 Chris Demetriou <cgd@broadcom.com>
24 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
25 immediate or code as a hex value with the "%#lx" format.
26 (ANDI): Likewise, and fix printed instruction name.
28 2002-03-05 Chris Demetriou <cgd@broadcom.com>
30 * sim-main.h (UndefinedResult, Unpredictable): New macros
31 which currently do nothing.
33 2002-03-05 Chris Demetriou <cgd@broadcom.com>
35 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
36 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
37 (status_CU3): New definitions.
39 * sim-main.h (ExceptionCause): Add new values for MIPS32
40 and MIPS64: MDMX, MCheck, CacheErr. Update comments
41 for DebugBreakPoint and NMIReset to note their status in
43 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
44 (SignalExceptionCacheErr): New exception macros.
46 2002-03-05 Chris Demetriou <cgd@broadcom.com>
48 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
49 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
51 (SignalExceptionCoProcessorUnusable): Take as argument the
52 unusable coprocessor number.
54 2002-03-05 Chris Demetriou <cgd@broadcom.com>
56 * mips.igen: Fix formatting of all SignalException calls.
58 2002-03-05 Chris Demetriou <cgd@broadcom.com>
60 * sim-main.h (SIGNEXTEND): Remove.
62 2002-03-04 Chris Demetriou <cgd@broadcom.com>
64 * mips.igen: Remove gencode comment from top of file, fix
65 spelling in another comment.
67 2002-03-04 Chris Demetriou <cgd@broadcom.com>
69 * mips.igen (check_fmt, check_fmt_p): New functions to check
70 whether specific floating point formats are usable.
71 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
72 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
73 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
74 Use the new functions.
75 (do_c_cond_fmt): Remove format checks...
76 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
78 2002-03-03 Chris Demetriou <cgd@broadcom.com>
80 * mips.igen: Fix formatting of check_fpu calls.
82 2002-03-03 Chris Demetriou <cgd@broadcom.com>
84 * mips.igen (FLOOR.L.fmt): Store correct destination register.
86 2002-03-03 Chris Demetriou <cgd@broadcom.com>
88 * mips.igen: Remove whitespace at end of lines.
90 2002-03-02 Chris Demetriou <cgd@broadcom.com>
92 * mips.igen (loadstore_ea): New function to do effective
94 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
95 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
96 CACHE): Use loadstore_ea to do effective address computations.
98 2002-03-02 Chris Demetriou <cgd@broadcom.com>
100 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
101 * mips.igen (LL, CxC1, MxC1): Likewise.
103 2002-03-02 Chris Demetriou <cgd@broadcom.com>
105 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
106 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
107 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
108 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
109 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
110 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
111 Don't split opcode fields by hand, use the opcode field values
114 2002-03-01 Chris Demetriou <cgd@broadcom.com>
116 * mips.igen (do_divu): Fix spacing.
118 * mips.igen (do_dsllv): Move to be right before DSLLV,
119 to match the rest of the do_<shift> functions.
121 2002-03-01 Chris Demetriou <cgd@broadcom.com>
123 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
124 DSRL32, do_dsrlv): Trace inputs and results.
126 2002-03-01 Chris Demetriou <cgd@broadcom.com>
128 * mips.igen (CACHE): Provide instruction-printing string.
130 * interp.c (signal_exception): Comment tokens after #endif.
132 2002-02-28 Chris Demetriou <cgd@broadcom.com>
134 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
135 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
136 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
137 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
138 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
139 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
140 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
141 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
143 2002-02-28 Chris Demetriou <cgd@broadcom.com>
145 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
146 instruction-printing string.
147 (LWU): Use '64' as the filter flag.
149 2002-02-28 Chris Demetriou <cgd@broadcom.com>
151 * mips.igen (SDXC1): Fix instruction-printing string.
153 2002-02-28 Chris Demetriou <cgd@broadcom.com>
155 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
158 2002-02-27 Chris Demetriou <cgd@broadcom.com>
160 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
163 2002-02-27 Chris Demetriou <cgd@broadcom.com>
165 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
166 add a comma) so that it more closely match the MIPS ISA
167 documentation opcode partitioning.
168 (PREF): Put useful names on opcode fields, and include
169 instruction-printing string.
171 2002-02-27 Chris Demetriou <cgd@broadcom.com>
173 * mips.igen (check_u64): New function which in the future will
174 check whether 64-bit instructions are usable and signal an
175 exception if not. Currently a no-op.
176 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
177 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
178 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
179 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
181 * mips.igen (check_fpu): New function which in the future will
182 check whether FPU instructions are usable and signal an exception
183 if not. Currently a no-op.
184 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
185 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
186 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
187 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
188 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
189 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
190 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
191 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
193 2002-02-27 Chris Demetriou <cgd@broadcom.com>
195 * mips.igen (do_load_left, do_load_right): Move to be immediately
197 (do_store_left, do_store_right): Move to be immediately following
200 2002-02-27 Chris Demetriou <cgd@broadcom.com>
202 * mips.igen (mipsV): New model name. Also, add it to
203 all instructions and functions where it is appropriate.
205 2002-02-18 Chris Demetriou <cgd@broadcom.com>
207 * mips.igen: For all functions and instructions, list model
208 names that support that instruction one per line.
210 2002-02-11 Chris Demetriou <cgd@broadcom.com>
212 * mips.igen: Add some additional comments about supported
213 models, and about which instructions go where.
214 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
215 order as is used in the rest of the file.
217 2002-02-11 Chris Demetriou <cgd@broadcom.com>
219 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
220 indicating that ALU32_END or ALU64_END are there to check
222 (DADD): Likewise, but also remove previous comment about
225 2002-02-10 Chris Demetriou <cgd@broadcom.com>
227 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
228 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
229 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
230 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
231 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
232 fields (i.e., add and move commas) so that they more closely
233 match the MIPS ISA documentation opcode partitioning.
235 2002-02-10 Chris Demetriou <cgd@broadcom.com>
237 * mips.igen (ADDI): Print immediate value.
239 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
240 (SLL): Print "nop" specially, and don't run the code
241 that does the shift for the "nop" case.
243 2001-11-17 Fred Fish <fnf@redhat.com>
245 * sim-main.h (float_operation): Move enum declaration outside
246 of _sim_cpu struct declaration.
248 2001-04-12 Jim Blandy <jimb@redhat.com>
250 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
251 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
253 * sim-main.h (COCIDX): Remove definition; this isn't supported by
254 PENDING_FILL, and you can get the intended effect gracefully by
255 calling PENDING_SCHED directly.
257 2001-02-23 Ben Elliston <bje@redhat.com>
259 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
260 already defined elsewhere.
262 2001-02-19 Ben Elliston <bje@redhat.com>
264 * sim-main.h (sim_monitor): Return an int.
265 * interp.c (sim_monitor): Add return values.
266 (signal_exception): Handle error conditions from sim_monitor.
268 2001-02-08 Ben Elliston <bje@redhat.com>
270 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
271 (store_memory): Likewise, pass cia to sim_core_write*.
273 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
275 On advice from Chris G. Demetriou <cgd@sibyte.com>:
276 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
278 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
280 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
281 * Makefile.in: Don't delete *.igen when cleaning directory.
283 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
285 * m16.igen (break): Call SignalException not sim_engine_halt.
287 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
290 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
292 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
294 * mips.igen (MxC1, DMxC1): Fix printf formatting.
296 2000-05-24 Michael Hayes <mhayes@cygnus.com>
298 * mips.igen (do_dmultx): Fix typo.
300 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
302 * configure: Regenerated to track ../common/aclocal.m4 changes.
304 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
306 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
308 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
310 * sim-main.h (GPR_CLEAR): Define macro.
312 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
314 * interp.c (decode_coproc): Output long using %lx and not %s.
316 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
318 * interp.c (sim_open): Sort & extend dummy memory regions for
319 --board=jmr3904 for eCos.
321 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
323 * configure: Regenerated.
325 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
327 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
328 calls, conditional on the simulator being in verbose mode.
330 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
332 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
333 cache don't get ReservedInstruction traps.
335 1999-11-29 Mark Salter <msalter@cygnus.com>
337 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
338 to clear status bits in sdisr register. This is how the hardware works.
340 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
341 being used by cygmon.
343 1999-11-11 Andrew Haley <aph@cygnus.com>
345 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
348 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
350 * mips.igen (MULT): Correct previous mis-applied patch.
352 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
354 * mips.igen (delayslot32): Handle sequence like
355 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
356 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
357 (MULT): Actually pass the third register...
359 1999-09-03 Mark Salter <msalter@cygnus.com>
361 * interp.c (sim_open): Added more memory aliases for additional
362 hardware being touched by cygmon on jmr3904 board.
364 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
366 * configure: Regenerated to track ../common/aclocal.m4 changes.
368 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
370 * interp.c (sim_store_register): Handle case where client - GDB -
371 specifies that a 4 byte register is 8 bytes in size.
372 (sim_fetch_register): Ditto.
374 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
376 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
377 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
378 (idt_monitor_base): Base address for IDT monitor traps.
379 (pmon_monitor_base): Ditto for PMON.
380 (lsipmon_monitor_base): Ditto for LSI PMON.
381 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
382 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
383 (sim_firmware_command): New function.
384 (mips_option_handler): Call it for OPTION_FIRMWARE.
385 (sim_open): Allocate memory for idt_monitor region. If "--board"
386 option was given, add no monitor by default. Add BREAK hooks only if
387 monitors are also there.
389 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
391 * interp.c (sim_monitor): Flush output before reading input.
393 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
395 * tconfig.in (SIM_HANDLES_LMA): Always define.
397 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
399 From Mark Salter <msalter@cygnus.com>:
400 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
401 (sim_open): Add setup for BSP board.
403 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
405 * mips.igen (MULT, MULTU): Add syntax for two operand version.
406 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
407 them as unimplemented.
409 1999-05-08 Felix Lee <flee@cygnus.com>
411 * configure: Regenerated to track ../common/aclocal.m4 changes.
413 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
415 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
417 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
419 * configure.in: Any mips64vr5*-*-* target should have
420 -DTARGET_ENABLE_FR=1.
421 (default_endian): Any mips64vr*el-*-* target should default to
423 * configure: Re-generate.
425 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
427 * mips.igen (ldl): Extend from _16_, not 32.
429 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
431 * interp.c (sim_store_register): Force registers written to by GDB
432 into an un-interpreted state.
434 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
436 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
437 CPU, start periodic background I/O polls.
438 (tx3904sio_poll): New function: periodic I/O poller.
440 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
442 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
444 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
446 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
449 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
451 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
452 (load_word): Call SIM_CORE_SIGNAL hook on error.
453 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
454 starting. For exception dispatching, pass PC instead of NULL_CIA.
455 (decode_coproc): Use COP0_BADVADDR to store faulting address.
456 * sim-main.h (COP0_BADVADDR): Define.
457 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
458 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
459 (_sim_cpu): Add exc_* fields to store register value snapshots.
460 * mips.igen (*): Replace memory-related SignalException* calls
461 with references to SIM_CORE_SIGNAL hook.
463 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
465 * sim-main.c (*): Minor warning cleanups.
467 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
469 * m16.igen (DADDIU5): Correct type-o.
471 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
473 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
476 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
478 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
480 (interp.o): Add dependency on itable.h
481 (oengine.c, gencode): Delete remaining references.
482 (BUILT_SRC_FROM_GEN): Clean up.
484 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
487 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
488 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
490 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
491 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
492 Drop the "64" qualifier to get the HACK generator working.
493 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
494 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
495 qualifier to get the hack generator working.
496 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
498 (DSLLV): Use do_dsllv.
501 (DSRLV): Use do_dsrlv.
502 (BC1): Move *vr4100 to get the HACK generator working.
503 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
504 get the HACK generator working.
505 (MACC) Rename to get the HACK generator working.
506 (DMACC,MACCS,DMACCS): Add the 64.
508 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
510 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
511 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
513 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
515 * mips/interp.c (DEBUG): Cleanups.
517 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
519 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
520 (tx3904sio_tickle): fflush after a stdout character output.
522 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
524 * interp.c (sim_close): Uninstall modules.
526 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
528 * sim-main.h, interp.c (sim_monitor): Change to global
531 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
533 * configure.in (vr4100): Only include vr4100 instructions in
535 * configure: Re-generate.
536 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
538 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
540 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
541 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
544 * configure.in (sim_default_gen, sim_use_gen): Replace with
546 (--enable-sim-igen): Delete config option. Always using IGEN.
547 * configure: Re-generate.
549 * Makefile.in (gencode): Kill, kill, kill.
552 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
554 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
555 bit mips16 igen simulator.
556 * configure: Re-generate.
558 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
559 as part of vr4100 ISA.
560 * vr.igen: Mark all instructions as 64 bit only.
562 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
564 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
567 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
569 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
570 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
571 * configure: Re-generate.
573 * m16.igen (BREAK): Define breakpoint instruction.
574 (JALX32): Mark instruction as mips16 and not r3900.
575 * mips.igen (C.cond.fmt): Fix typo in instruction format.
577 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
579 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
581 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
582 insn as a debug breakpoint.
584 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
586 (PENDING_SCHED): Clean up trace statement.
587 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
588 (PENDING_FILL): Delay write by only one cycle.
589 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
591 * sim-main.c (pending_tick): Clean up trace statements. Add trace
593 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
595 (pending_tick): Move incrementing of index to FOR statement.
596 (pending_tick): Only update PENDING_OUT after a write has occured.
598 * configure.in: Add explicit mips-lsi-* target. Use gencode to
600 * configure: Re-generate.
602 * interp.c (sim_engine_run OLD): Delete explicit call to
603 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
605 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
607 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
608 interrupt level number to match changed SignalExceptionInterrupt
611 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
613 * interp.c: #include "itable.h" if WITH_IGEN.
614 (get_insn_name): New function.
615 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
616 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
618 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
620 * configure: Rebuilt to inhale new common/aclocal.m4.
622 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
624 * dv-tx3904sio.c: Include sim-assert.h.
626 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
628 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
629 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
630 Reorganize target-specific sim-hardware checks.
631 * configure: rebuilt.
632 * interp.c (sim_open): For tx39 target boards, set
633 OPERATING_ENVIRONMENT, add tx3904sio devices.
634 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
635 ROM executables. Install dv-sockser into sim-modules list.
637 * dv-tx3904irc.c: Compiler warning clean-up.
638 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
639 frequent hw-trace messages.
641 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
643 * vr.igen (MulAcc): Identify as a vr4100 specific function.
645 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
647 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
650 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
651 * mips.igen: Define vr4100 model. Include vr.igen.
652 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
654 * mips.igen (check_mf_hilo): Correct check.
656 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
658 * sim-main.h (interrupt_event): Add prototype.
660 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
661 register_ptr, register_value.
662 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
664 * sim-main.h (tracefh): Make extern.
666 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
668 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
669 Reduce unnecessarily high timer event frequency.
670 * dv-tx3904cpu.c: Ditto for interrupt event.
672 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
674 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
676 (interrupt_event): Made non-static.
678 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
679 interchange of configuration values for external vs. internal
682 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
684 * mips.igen (BREAK): Moved code to here for
685 simulator-reserved break instructions.
686 * gencode.c (build_instruction): Ditto.
687 * interp.c (signal_exception): Code moved from here. Non-
688 reserved instructions now use exception vector, rather
690 * sim-main.h: Moved magic constants to here.
692 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
694 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
695 register upon non-zero interrupt event level, clear upon zero
697 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
698 by passing zero event value.
699 (*_io_{read,write}_buffer): Endianness fixes.
700 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
701 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
703 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
704 serial I/O and timer module at base address 0xFFFF0000.
706 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
708 * mips.igen (SWC1) : Correct the handling of ReverseEndian
711 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
713 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
717 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
719 * dv-tx3904tmr.c: New file - implements tx3904 timer.
720 * dv-tx3904{irc,cpu}.c: Mild reformatting.
721 * configure.in: Include tx3904tmr in hw_device list.
722 * configure: Rebuilt.
723 * interp.c (sim_open): Instantiate three timer instances.
724 Fix address typo of tx3904irc instance.
726 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
728 * interp.c (signal_exception): SystemCall exception now uses
729 the exception vector.
731 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
733 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
736 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
738 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
740 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
742 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
744 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
745 sim-main.h. Declare a struct hw_descriptor instead of struct
746 hw_device_descriptor.
748 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
750 * mips.igen (do_store_left, do_load_left): Compute nr of left and
751 right bits and then re-align left hand bytes to correct byte
752 lanes. Fix incorrect computation in do_store_left when loading
753 bytes from second word.
755 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
757 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
758 * interp.c (sim_open): Only create a device tree when HW is
761 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
762 * interp.c (signal_exception): Ditto.
764 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
766 * gencode.c: Mark BEGEZALL as LIKELY.
768 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
770 * sim-main.h (ALU32_END): Sign extend 32 bit results.
771 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
773 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
775 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
776 modules. Recognize TX39 target with "mips*tx39" pattern.
777 * configure: Rebuilt.
778 * sim-main.h (*): Added many macros defining bits in
779 TX39 control registers.
780 (SignalInterrupt): Send actual PC instead of NULL.
781 (SignalNMIReset): New exception type.
782 * interp.c (board): New variable for future use to identify
783 a particular board being simulated.
784 (mips_option_handler,mips_options): Added "--board" option.
785 (interrupt_event): Send actual PC.
786 (sim_open): Make memory layout conditional on board setting.
787 (signal_exception): Initial implementation of hardware interrupt
788 handling. Accept another break instruction variant for simulator
790 (decode_coproc): Implement RFE instruction for TX39.
791 (mips.igen): Decode RFE instruction as such.
792 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
793 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
794 bbegin to implement memory map.
795 * dv-tx3904cpu.c: New file.
796 * dv-tx3904irc.c: New file.
798 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
800 * mips.igen (check_mt_hilo): Create a separate r3900 version.
802 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
804 * tx.igen (madd,maddu): Replace calls to check_op_hilo
805 with calls to check_div_hilo.
807 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
809 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
810 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
811 Add special r3900 version of do_mult_hilo.
812 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
813 with calls to check_mult_hilo.
814 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
815 with calls to check_div_hilo.
817 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
819 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
820 Document a replacement.
822 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
824 * interp.c (sim_monitor): Make mon_printf work.
826 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
828 * sim-main.h (INSN_NAME): New arg `cpu'.
830 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
832 * configure: Regenerated to track ../common/aclocal.m4 changes.
834 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
836 * configure: Regenerated to track ../common/aclocal.m4 changes.
839 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
841 * acconfig.h: New file.
842 * configure.in: Reverted change of Apr 24; use sinclude again.
844 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
846 * configure: Regenerated to track ../common/aclocal.m4 changes.
849 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
851 * configure.in: Don't call sinclude.
853 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
855 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
857 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
859 * mips.igen (ERET): Implement.
861 * interp.c (decode_coproc): Return sign-extended EPC.
863 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
865 * interp.c (signal_exception): Do not ignore Trap.
866 (signal_exception): On TRAP, restart at exception address.
867 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
868 (signal_exception): Update.
869 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
870 so that TRAP instructions are caught.
872 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
874 * sim-main.h (struct hilo_access, struct hilo_history): Define,
875 contains HI/LO access history.
876 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
877 (HIACCESS, LOACCESS): Delete, replace with
878 (HIHISTORY, LOHISTORY): New macros.
879 (CHECKHILO): Delete all, moved to mips.igen
881 * gencode.c (build_instruction): Do not generate checks for
882 correct HI/LO register usage.
884 * interp.c (old_engine_run): Delete checks for correct HI/LO
887 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
888 check_mf_cycles): New functions.
889 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
890 do_divu, domultx, do_mult, do_multu): Use.
892 * tx.igen ("madd", "maddu"): Use.
894 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
896 * mips.igen (DSRAV): Use function do_dsrav.
897 (SRAV): Use new function do_srav.
899 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
900 (B): Sign extend 11 bit immediate.
901 (EXT-B*): Shift 16 bit immediate left by 1.
902 (ADDIU*): Don't sign extend immediate value.
904 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
906 * m16run.c (sim_engine_run): Restore CIA after handling an event.
908 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
911 * mips.igen (delayslot32, nullify_next_insn): New functions.
912 (m16.igen): Always include.
913 (do_*): Add more tracing.
915 * m16.igen (delayslot16): Add NIA argument, could be called by a
916 32 bit MIPS16 instruction.
918 * interp.c (ifetch16): Move function from here.
919 * sim-main.c (ifetch16): To here.
921 * sim-main.c (ifetch16, ifetch32): Update to match current
922 implementations of LH, LW.
923 (signal_exception): Don't print out incorrect hex value of illegal
926 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
928 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
931 * m16.igen: Implement MIPS16 instructions.
933 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
934 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
935 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
936 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
937 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
938 bodies of corresponding code from 32 bit insn to these. Also used
939 by MIPS16 versions of functions.
941 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
942 (IMEM16): Drop NR argument from macro.
944 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
946 * Makefile.in (SIM_OBJS): Add sim-main.o.
948 * sim-main.h (address_translation, load_memory, store_memory,
949 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
951 (pr_addr, pr_uword64): Declare.
952 (sim-main.c): Include when H_REVEALS_MODULE_P.
954 * interp.c (address_translation, load_memory, store_memory,
955 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
957 * sim-main.c: To here. Fix compilation problems.
959 * configure.in: Enable inlining.
960 * configure: Re-config.
962 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
964 * configure: Regenerated to track ../common/aclocal.m4 changes.
966 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
968 * mips.igen: Include tx.igen.
969 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
970 * tx.igen: New file, contains MADD and MADDU.
972 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
973 the hardwired constant `7'.
974 (store_memory): Ditto.
975 (LOADDRMASK): Move definition to sim-main.h.
977 mips.igen (MTC0): Enable for r3900.
980 mips.igen (do_load_byte): Delete.
981 (do_load, do_store, do_load_left, do_load_write, do_store_left,
982 do_store_right): New functions.
983 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
985 configure.in: Let the tx39 use igen again.
988 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
990 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
991 not an address sized quantity. Return zero for cache sizes.
993 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
995 * mips.igen (r3900): r3900 does not support 64 bit integer
998 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1000 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1002 * configure : Rebuild.
1004 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1006 * configure: Regenerated to track ../common/aclocal.m4 changes.
1008 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1010 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1012 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1014 * configure: Regenerated to track ../common/aclocal.m4 changes.
1015 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1017 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1019 * configure: Regenerated to track ../common/aclocal.m4 changes.
1021 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1023 * interp.c (Max, Min): Comment out functions. Not yet used.
1025 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1027 * configure: Regenerated to track ../common/aclocal.m4 changes.
1029 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1031 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1032 configurable settings for stand-alone simulator.
1034 * configure.in: Added X11 search, just in case.
1036 * configure: Regenerated.
1038 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1040 * interp.c (sim_write, sim_read, load_memory, store_memory):
1041 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1043 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1045 * sim-main.h (GETFCC): Return an unsigned value.
1047 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1049 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1050 (DADD): Result destination is RD not RT.
1052 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1054 * sim-main.h (HIACCESS, LOACCESS): Always define.
1056 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1058 * interp.c (sim_info): Delete.
1060 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1062 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1063 (mips_option_handler): New argument `cpu'.
1064 (sim_open): Update call to sim_add_option_table.
1066 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1068 * mips.igen (CxC1): Add tracing.
1070 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1072 * sim-main.h (Max, Min): Declare.
1074 * interp.c (Max, Min): New functions.
1076 * mips.igen (BC1): Add tracing.
1078 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1080 * interp.c Added memory map for stack in vr4100
1082 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1084 * interp.c (load_memory): Add missing "break"'s.
1086 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1088 * interp.c (sim_store_register, sim_fetch_register): Pass in
1089 length parameter. Return -1.
1091 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1093 * interp.c: Added hardware init hook, fixed warnings.
1095 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1097 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1099 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1101 * interp.c (ifetch16): New function.
1103 * sim-main.h (IMEM32): Rename IMEM.
1104 (IMEM16_IMMED): Define.
1106 (DELAY_SLOT): Update.
1108 * m16run.c (sim_engine_run): New file.
1110 * m16.igen: All instructions except LB.
1111 (LB): Call do_load_byte.
1112 * mips.igen (do_load_byte): New function.
1113 (LB): Call do_load_byte.
1115 * mips.igen: Move spec for insn bit size and high bit from here.
1116 * Makefile.in (tmp-igen, tmp-m16): To here.
1118 * m16.dc: New file, decode mips16 instructions.
1120 * Makefile.in (SIM_NO_ALL): Define.
1121 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1123 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1125 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1126 point unit to 32 bit registers.
1127 * configure: Re-generate.
1129 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1131 * configure.in (sim_use_gen): Make IGEN the default simulator
1132 generator for generic 32 and 64 bit mips targets.
1133 * configure: Re-generate.
1135 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1137 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1140 * interp.c (sim_fetch_register, sim_store_register): Read/write
1141 FGR from correct location.
1142 (sim_open): Set size of FGR's according to
1143 WITH_TARGET_FLOATING_POINT_BITSIZE.
1145 * sim-main.h (FGR): Store floating point registers in a separate
1148 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1150 * configure: Regenerated to track ../common/aclocal.m4 changes.
1152 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1154 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1156 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1158 * interp.c (pending_tick): New function. Deliver pending writes.
1160 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1161 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1162 it can handle mixed sized quantites and single bits.
1164 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1166 * interp.c (oengine.h): Do not include when building with IGEN.
1167 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1168 (sim_info): Ditto for PROCESSOR_64BIT.
1169 (sim_monitor): Replace ut_reg with unsigned_word.
1170 (*): Ditto for t_reg.
1171 (LOADDRMASK): Define.
1172 (sim_open): Remove defunct check that host FP is IEEE compliant,
1173 using software to emulate floating point.
1174 (value_fpr, ...): Always compile, was conditional on HASFPU.
1176 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1178 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1181 * interp.c (SD, CPU): Define.
1182 (mips_option_handler): Set flags in each CPU.
1183 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1184 (sim_close): Do not clear STATE, deleted anyway.
1185 (sim_write, sim_read): Assume CPU zero's vm should be used for
1187 (sim_create_inferior): Set the PC for all processors.
1188 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1190 (mips16_entry): Pass correct nr of args to store_word, load_word.
1191 (ColdReset): Cold reset all cpu's.
1192 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1193 (sim_monitor, load_memory, store_memory, signal_exception): Use
1194 `CPU' instead of STATE_CPU.
1197 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1200 * sim-main.h (signal_exception): Add sim_cpu arg.
1201 (SignalException*): Pass both SD and CPU to signal_exception.
1202 * interp.c (signal_exception): Update.
1204 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1206 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1207 address_translation): Ditto
1208 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1210 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1212 * configure: Regenerated to track ../common/aclocal.m4 changes.
1214 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1216 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1218 * mips.igen (model): Map processor names onto BFD name.
1220 * sim-main.h (CPU_CIA): Delete.
1221 (SET_CIA, GET_CIA): Define
1223 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1225 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1228 * configure.in (default_endian): Configure a big-endian simulator
1230 * configure: Re-generate.
1232 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1234 * configure: Regenerated to track ../common/aclocal.m4 changes.
1236 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1238 * interp.c (sim_monitor): Handle Densan monitor outbyte
1239 and inbyte functions.
1241 1997-12-29 Felix Lee <flee@cygnus.com>
1243 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1245 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1247 * Makefile.in (tmp-igen): Arrange for $zero to always be
1248 reset to zero after every instruction.
1250 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1252 * configure: Regenerated to track ../common/aclocal.m4 changes.
1255 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1257 * mips.igen (MSUB): Fix to work like MADD.
1258 * gencode.c (MSUB): Similarly.
1260 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1262 * configure: Regenerated to track ../common/aclocal.m4 changes.
1264 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1266 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1268 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1270 * sim-main.h (sim-fpu.h): Include.
1272 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1273 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1274 using host independant sim_fpu module.
1276 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1278 * interp.c (signal_exception): Report internal errors with SIGABRT
1281 * sim-main.h (C0_CONFIG): New register.
1282 (signal.h): No longer include.
1284 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1286 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1288 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1290 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1292 * mips.igen: Tag vr5000 instructions.
1293 (ANDI): Was missing mipsIV model, fix assembler syntax.
1294 (do_c_cond_fmt): New function.
1295 (C.cond.fmt): Handle mips I-III which do not support CC field
1297 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1298 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1300 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1301 vr5000 which saves LO in a GPR separatly.
1303 * configure.in (enable-sim-igen): For vr5000, select vr5000
1304 specific instructions.
1305 * configure: Re-generate.
1307 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1309 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1311 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1312 fmt_uninterpreted_64 bit cases to switch. Convert to
1315 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1317 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1318 as specified in IV3.2 spec.
1319 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1321 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1323 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1324 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1325 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1326 PENDING_FILL versions of instructions. Simplify.
1328 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1330 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1332 (MTHI, MFHI): Disable code checking HI-LO.
1334 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1336 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1338 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1340 * gencode.c (build_mips16_operands): Replace IPC with cia.
1342 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1343 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1345 (UndefinedResult): Replace function with macro/function
1347 (sim_engine_run): Don't save PC in IPC.
1349 * sim-main.h (IPC): Delete.
1352 * interp.c (signal_exception, store_word, load_word,
1353 address_translation, load_memory, store_memory, cache_op,
1354 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1355 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1356 current instruction address - cia - argument.
1357 (sim_read, sim_write): Call address_translation directly.
1358 (sim_engine_run): Rename variable vaddr to cia.
1359 (signal_exception): Pass cia to sim_monitor
1361 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1362 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1363 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1365 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1366 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1369 * interp.c (signal_exception): Pass restart address to
1372 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1373 idecode.o): Add dependency.
1375 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1377 (DELAY_SLOT): Update NIA not PC with branch address.
1378 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1380 * mips.igen: Use CIA not PC in branch calculations.
1381 (illegal): Call SignalException.
1382 (BEQ, ADDIU): Fix assembler.
1384 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1386 * m16.igen (JALX): Was missing.
1388 * configure.in (enable-sim-igen): New configuration option.
1389 * configure: Re-generate.
1391 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1393 * interp.c (load_memory, store_memory): Delete parameter RAW.
1394 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1395 bypassing {load,store}_memory.
1397 * sim-main.h (ByteSwapMem): Delete definition.
1399 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1401 * interp.c (sim_do_command, sim_commands): Delete mips specific
1402 commands. Handled by module sim-options.
1404 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1405 (WITH_MODULO_MEMORY): Define.
1407 * interp.c (sim_info): Delete code printing memory size.
1409 * interp.c (mips_size): Nee sim_size, delete function.
1411 (monitor, monitor_base, monitor_size): Delete global variables.
1412 (sim_open, sim_close): Delete code creating monitor and other
1413 memory regions. Use sim-memopts module, via sim_do_commandf, to
1414 manage memory regions.
1415 (load_memory, store_memory): Use sim-core for memory model.
1417 * interp.c (address_translation): Delete all memory map code
1418 except line forcing 32 bit addresses.
1420 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1422 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1425 * interp.c (logfh, logfile): Delete globals.
1426 (sim_open, sim_close): Delete code opening & closing log file.
1427 (mips_option_handler): Delete -l and -n options.
1428 (OPTION mips_options): Ditto.
1430 * interp.c (OPTION mips_options): Rename option trace to dinero.
1431 (mips_option_handler): Update.
1433 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1435 * interp.c (fetch_str): New function.
1436 (sim_monitor): Rewrite using sim_read & sim_write.
1437 (sim_open): Check magic number.
1438 (sim_open): Write monitor vectors into memory using sim_write.
1439 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1440 (sim_read, sim_write): Simplify - transfer data one byte at a
1442 (load_memory, store_memory): Clarify meaning of parameter RAW.
1444 * sim-main.h (isHOST): Defete definition.
1445 (isTARGET): Mark as depreciated.
1446 (address_translation): Delete parameter HOST.
1448 * interp.c (address_translation): Delete parameter HOST.
1450 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1454 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1455 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1457 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1459 * mips.igen: Add model filter field to records.
1461 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1463 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1465 interp.c (sim_engine_run): Do not compile function sim_engine_run
1466 when WITH_IGEN == 1.
1468 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1469 target architecture.
1471 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1472 igen. Replace with configuration variables sim_igen_flags /
1475 * m16.igen: New file. Copy mips16 insns here.
1476 * mips.igen: From here.
1478 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1480 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1482 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1484 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1486 * gencode.c (build_instruction): Follow sim_write's lead in using
1487 BigEndianMem instead of !ByteSwapMem.
1489 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1491 * configure.in (sim_gen): Dependent on target, select type of
1492 generator. Always select old style generator.
1494 configure: Re-generate.
1496 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1498 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1499 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1500 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1501 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1502 SIM_@sim_gen@_*, set by autoconf.
1504 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1506 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1508 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1509 CURRENT_FLOATING_POINT instead.
1511 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1512 (address_translation): Raise exception InstructionFetch when
1513 translation fails and isINSTRUCTION.
1515 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1516 sim_engine_run): Change type of of vaddr and paddr to
1518 (address_translation, prefetch, load_memory, store_memory,
1519 cache_op): Change type of vAddr and pAddr to address_word.
1521 * gencode.c (build_instruction): Change type of vaddr and paddr to
1524 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1526 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1527 macro to obtain result of ALU op.
1529 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1531 * interp.c (sim_info): Call profile_print.
1533 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1535 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1537 * sim-main.h (WITH_PROFILE): Do not define, defined in
1538 common/sim-config.h. Use sim-profile module.
1539 (simPROFILE): Delete defintion.
1541 * interp.c (PROFILE): Delete definition.
1542 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1543 (sim_close): Delete code writing profile histogram.
1544 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1546 (sim_engine_run): Delete code profiling the PC.
1548 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1550 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1552 * interp.c (sim_monitor): Make register pointers of type
1555 * sim-main.h: Make registers of type unsigned_word not
1558 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1560 * interp.c (sync_operation): Rename from SyncOperation, make
1561 global, add SD argument.
1562 (prefetch): Rename from Prefetch, make global, add SD argument.
1563 (decode_coproc): Make global.
1565 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1567 * gencode.c (build_instruction): Generate DecodeCoproc not
1568 decode_coproc calls.
1570 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1571 (SizeFGR): Move to sim-main.h
1572 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1573 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1574 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1576 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1577 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1578 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1579 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1580 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1581 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1583 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1585 (sim-alu.h): Include.
1586 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1587 (sim_cia): Typedef to instruction_address.
1589 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1591 * Makefile.in (interp.o): Rename generated file engine.c to
1596 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1598 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1600 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1602 * gencode.c (build_instruction): For "FPSQRT", output correct
1603 number of arguments to Recip.
1605 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1607 * Makefile.in (interp.o): Depends on sim-main.h
1609 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1611 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1612 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1613 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1614 STATE, DSSTATE): Define
1615 (GPR, FGRIDX, ..): Define.
1617 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1618 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1619 (GPR, FGRIDX, ...): Delete macros.
1621 * interp.c: Update names to match defines from sim-main.h
1623 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1625 * interp.c (sim_monitor): Add SD argument.
1626 (sim_warning): Delete. Replace calls with calls to
1628 (sim_error): Delete. Replace calls with sim_io_error.
1629 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1630 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1631 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1633 (mips_size): Rename from sim_size. Add SD argument.
1635 * interp.c (simulator): Delete global variable.
1636 (callback): Delete global variable.
1637 (mips_option_handler, sim_open, sim_write, sim_read,
1638 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1639 sim_size,sim_monitor): Use sim_io_* not callback->*.
1640 (sim_open): ZALLOC simulator struct.
1641 (PROFILE): Do not define.
1643 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1645 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1646 support.h with corresponding code.
1648 * sim-main.h (word64, uword64), support.h: Move definition to
1650 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1653 * Makefile.in: Update dependencies
1654 * interp.c: Do not include.
1656 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1658 * interp.c (address_translation, load_memory, store_memory,
1659 cache_op): Rename to from AddressTranslation et.al., make global,
1662 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1665 * interp.c (SignalException): Rename to signal_exception, make
1668 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1670 * sim-main.h (SignalException, SignalExceptionInterrupt,
1671 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1672 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1673 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1676 * interp.c, support.h: Use.
1678 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1680 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1681 to value_fpr / store_fpr. Add SD argument.
1682 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1683 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1685 * sim-main.h (ValueFPR, StoreFPR): Define.
1687 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1689 * interp.c (sim_engine_run): Check consistency between configure
1690 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1693 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1694 (mips_fpu): Configure WITH_FLOATING_POINT.
1695 (mips_endian): Configure WITH_TARGET_ENDIAN.
1696 * configure: Update.
1698 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1700 * configure: Regenerated to track ../common/aclocal.m4 changes.
1702 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1704 * configure: Regenerated.
1706 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1708 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1710 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1712 * gencode.c (print_igen_insn_models): Assume certain architectures
1713 include all mips* instructions.
1714 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1717 * Makefile.in (tmp.igen): Add target. Generate igen input from
1720 * gencode.c (FEATURE_IGEN): Define.
1721 (main): Add --igen option. Generate output in igen format.
1722 (process_instructions): Format output according to igen option.
1723 (print_igen_insn_format): New function.
1724 (print_igen_insn_models): New function.
1725 (process_instructions): Only issue warnings and ignore
1726 instructions when no FEATURE_IGEN.
1728 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1730 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1733 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1735 * configure: Regenerated to track ../common/aclocal.m4 changes.
1737 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1739 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1740 SIM_RESERVED_BITS): Delete, moved to common.
1741 (SIM_EXTRA_CFLAGS): Update.
1743 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1745 * configure.in: Configure non-strict memory alignment.
1746 * configure: Regenerated to track ../common/aclocal.m4 changes.
1748 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1750 * configure: Regenerated to track ../common/aclocal.m4 changes.
1752 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1754 * gencode.c (SDBBP,DERET): Added (3900) insns.
1755 (RFE): Turn on for 3900.
1756 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1757 (dsstate): Made global.
1758 (SUBTARGET_R3900): Added.
1759 (CANCELDELAYSLOT): New.
1760 (SignalException): Ignore SystemCall rather than ignore and
1761 terminate. Add DebugBreakPoint handling.
1762 (decode_coproc): New insns RFE, DERET; and new registers Debug
1763 and DEPC protected by SUBTARGET_R3900.
1764 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1766 * Makefile.in,configure.in: Add mips subtarget option.
1767 * configure: Update.
1769 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1771 * gencode.c: Add r3900 (tx39).
1774 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1776 * gencode.c (build_instruction): Don't need to subtract 4 for
1779 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1781 * interp.c: Correct some HASFPU problems.
1783 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1785 * configure: Regenerated to track ../common/aclocal.m4 changes.
1787 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1789 * interp.c (mips_options): Fix samples option short form, should
1792 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1794 * interp.c (sim_info): Enable info code. Was just returning.
1796 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1798 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1801 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1803 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1805 (build_instruction): Ditto for LL.
1807 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1809 * configure: Regenerated to track ../common/aclocal.m4 changes.
1811 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1813 * configure: Regenerated to track ../common/aclocal.m4 changes.
1816 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1818 * interp.c (sim_open): Add call to sim_analyze_program, update
1821 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1823 * interp.c (sim_kill): Delete.
1824 (sim_create_inferior): Add ABFD argument. Set PC from same.
1825 (sim_load): Move code initializing trap handlers from here.
1826 (sim_open): To here.
1827 (sim_load): Delete, use sim-hload.c.
1829 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1831 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1833 * configure: Regenerated to track ../common/aclocal.m4 changes.
1836 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1838 * interp.c (sim_open): Add ABFD argument.
1839 (sim_load): Move call to sim_config from here.
1840 (sim_open): To here. Check return status.
1842 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1844 * gencode.c (build_instruction): Two arg MADD should
1845 not assign result to $0.
1847 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1849 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1850 * sim/mips/configure.in: Regenerate.
1852 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1854 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1855 signed8, unsigned8 et.al. types.
1857 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1858 hosts when selecting subreg.
1860 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1862 * interp.c (sim_engine_run): Reset the ZERO register to zero
1863 regardless of FEATURE_WARN_ZERO.
1864 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1866 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1868 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1869 (SignalException): For BreakPoints ignore any mode bits and just
1871 (SignalException): Always set the CAUSE register.
1873 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1875 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1876 exception has been taken.
1878 * interp.c: Implement the ERET and mt/f sr instructions.
1880 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1882 * interp.c (SignalException): Don't bother restarting an
1885 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1887 * interp.c (SignalException): Really take an interrupt.
1888 (interrupt_event): Only deliver interrupts when enabled.
1890 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1892 * interp.c (sim_info): Only print info when verbose.
1893 (sim_info) Use sim_io_printf for output.
1895 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1897 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1900 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1902 * interp.c (sim_do_command): Check for common commands if a
1903 simulator specific command fails.
1905 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1907 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1908 and simBE when DEBUG is defined.
1910 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1912 * interp.c (interrupt_event): New function. Pass exception event
1913 onto exception handler.
1915 * configure.in: Check for stdlib.h.
1916 * configure: Regenerate.
1918 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1919 variable declaration.
1920 (build_instruction): Initialize memval1.
1921 (build_instruction): Add UNUSED attribute to byte, bigend,
1923 (build_operands): Ditto.
1925 * interp.c: Fix GCC warnings.
1926 (sim_get_quit_code): Delete.
1928 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1929 * Makefile.in: Ditto.
1930 * configure: Re-generate.
1932 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1934 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1936 * interp.c (mips_option_handler): New function parse argumes using
1938 (myname): Replace with STATE_MY_NAME.
1939 (sim_open): Delete check for host endianness - performed by
1941 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1942 (sim_open): Move much of the initialization from here.
1943 (sim_load): To here. After the image has been loaded and
1945 (sim_open): Move ColdReset from here.
1946 (sim_create_inferior): To here.
1947 (sim_open): Make FP check less dependant on host endianness.
1949 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1951 * interp.c (sim_set_callbacks): Delete.
1953 * interp.c (membank, membank_base, membank_size): Replace with
1954 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1955 (sim_open): Remove call to callback->init. gdb/run do this.
1959 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1961 * interp.c (big_endian_p): Delete, replaced by
1962 current_target_byte_order.
1964 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1966 * interp.c (host_read_long, host_read_word, host_swap_word,
1967 host_swap_long): Delete. Using common sim-endian.
1968 (sim_fetch_register, sim_store_register): Use H2T.
1969 (pipeline_ticks): Delete. Handled by sim-events.
1971 (sim_engine_run): Update.
1973 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1975 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1977 (SignalException): To here. Signal using sim_engine_halt.
1978 (sim_stop_reason): Delete, moved to common.
1980 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1982 * interp.c (sim_open): Add callback argument.
1983 (sim_set_callbacks): Delete SIM_DESC argument.
1986 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1988 * Makefile.in (SIM_OBJS): Add common modules.
1990 * interp.c (sim_set_callbacks): Also set SD callback.
1991 (set_endianness, xfer_*, swap_*): Delete.
1992 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1993 Change to functions using sim-endian macros.
1994 (control_c, sim_stop): Delete, use common version.
1995 (simulate): Convert into.
1996 (sim_engine_run): This function.
1997 (sim_resume): Delete.
1999 * interp.c (simulation): New variable - the simulator object.
2000 (sim_kind): Delete global - merged into simulation.
2001 (sim_load): Cleanup. Move PC assignment from here.
2002 (sim_create_inferior): To here.
2004 * sim-main.h: New file.
2005 * interp.c (sim-main.h): Include.
2007 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2009 * configure: Regenerated to track ../common/aclocal.m4 changes.
2011 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2013 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2015 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2017 * gencode.c (build_instruction): DIV instructions: check
2018 for division by zero and integer overflow before using
2019 host's division operation.
2021 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2023 * Makefile.in (SIM_OBJS): Add sim-load.o.
2024 * interp.c: #include bfd.h.
2025 (target_byte_order): Delete.
2026 (sim_kind, myname, big_endian_p): New static locals.
2027 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2028 after argument parsing. Recognize -E arg, set endianness accordingly.
2029 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2030 load file into simulator. Set PC from bfd.
2031 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2032 (set_endianness): Use big_endian_p instead of target_byte_order.
2034 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2036 * interp.c (sim_size): Delete prototype - conflicts with
2037 definition in remote-sim.h. Correct definition.
2039 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2041 * configure: Regenerated to track ../common/aclocal.m4 changes.
2044 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2046 * interp.c (sim_open): New arg `kind'.
2048 * configure: Regenerated to track ../common/aclocal.m4 changes.
2050 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2052 * configure: Regenerated to track ../common/aclocal.m4 changes.
2054 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2056 * interp.c (sim_open): Set optind to 0 before calling getopt.
2058 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2060 * configure: Regenerated to track ../common/aclocal.m4 changes.
2062 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2064 * interp.c : Replace uses of pr_addr with pr_uword64
2065 where the bit length is always 64 independent of SIM_ADDR.
2066 (pr_uword64) : added.
2068 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2070 * configure: Re-generate.
2072 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2074 * configure: Regenerate to track ../common/aclocal.m4 changes.
2076 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2078 * interp.c (sim_open): New SIM_DESC result. Argument is now
2080 (other sim_*): New SIM_DESC argument.
2082 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2084 * interp.c: Fix printing of addresses for non-64-bit targets.
2085 (pr_addr): Add function to print address based on size.
2087 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2089 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2091 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2093 * gencode.c (build_mips16_operands): Correct computation of base
2094 address for extended PC relative instruction.
2096 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2098 * interp.c (mips16_entry): Add support for floating point cases.
2099 (SignalException): Pass floating point cases to mips16_entry.
2100 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2102 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2104 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2105 and then set the state to fmt_uninterpreted.
2106 (COP_SW): Temporarily set the state to fmt_word while calling
2109 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2111 * gencode.c (build_instruction): The high order may be set in the
2112 comparison flags at any ISA level, not just ISA 4.
2114 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2116 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2117 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2118 * configure.in: sinclude ../common/aclocal.m4.
2119 * configure: Regenerated.
2121 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2123 * configure: Rebuild after change to aclocal.m4.
2125 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2127 * configure configure.in Makefile.in: Update to new configure
2128 scheme which is more compatible with WinGDB builds.
2129 * configure.in: Improve comment on how to run autoconf.
2130 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2131 * Makefile.in: Use autoconf substitution to install common
2134 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2136 * gencode.c (build_instruction): Use BigEndianCPU instead of
2139 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2141 * interp.c (sim_monitor): Make output to stdout visible in
2142 wingdb's I/O log window.
2144 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2146 * support.h: Undo previous change to SIGTRAP
2149 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2151 * interp.c (store_word, load_word): New static functions.
2152 (mips16_entry): New static function.
2153 (SignalException): Look for mips16 entry and exit instructions.
2154 (simulate): Use the correct index when setting fpr_state after
2155 doing a pending move.
2157 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2159 * interp.c: Fix byte-swapping code throughout to work on
2160 both little- and big-endian hosts.
2162 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2164 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2165 with gdb/config/i386/xm-windows.h.
2167 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2169 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2170 that messes up arithmetic shifts.
2172 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2174 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2175 SIGTRAP and SIGQUIT for _WIN32.
2177 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2179 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2180 force a 64 bit multiplication.
2181 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2182 destination register is 0, since that is the default mips16 nop
2185 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2187 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2188 (build_endian_shift): Don't check proc64.
2189 (build_instruction): Always set memval to uword64. Cast op2 to
2190 uword64 when shifting it left in memory instructions. Always use
2191 the same code for stores--don't special case proc64.
2193 * gencode.c (build_mips16_operands): Fix base PC value for PC
2195 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2197 * interp.c (simJALDELAYSLOT): Define.
2198 (JALDELAYSLOT): Define.
2199 (INDELAYSLOT, INJALDELAYSLOT): Define.
2200 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2202 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2204 * interp.c (sim_open): add flush_cache as a PMON routine
2205 (sim_monitor): handle flush_cache by ignoring it
2207 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2209 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2211 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2212 (BigEndianMem): Rename to ByteSwapMem and change sense.
2213 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2214 BigEndianMem references to !ByteSwapMem.
2215 (set_endianness): New function, with prototype.
2216 (sim_open): Call set_endianness.
2217 (sim_info): Use simBE instead of BigEndianMem.
2218 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2219 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2220 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2221 ifdefs, keeping the prototype declaration.
2222 (swap_word): Rewrite correctly.
2223 (ColdReset): Delete references to CONFIG. Delete endianness related
2224 code; moved to set_endianness.
2226 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2228 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2229 * interp.c (CHECKHILO): Define away.
2230 (simSIGINT): New macro.
2231 (membank_size): Increase from 1MB to 2MB.
2232 (control_c): New function.
2233 (sim_resume): Rename parameter signal to signal_number. Add local
2234 variable prev. Call signal before and after simulate.
2235 (sim_stop_reason): Add simSIGINT support.
2236 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2238 (sim_warning): Delete call to SignalException. Do call printf_filtered
2240 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2241 a call to sim_warning.
2243 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2245 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2246 16 bit instructions.
2248 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2250 Add support for mips16 (16 bit MIPS implementation):
2251 * gencode.c (inst_type): Add mips16 instruction encoding types.
2252 (GETDATASIZEINSN): Define.
2253 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2254 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2256 (MIPS16_DECODE): New table, for mips16 instructions.
2257 (bitmap_val): New static function.
2258 (struct mips16_op): Define.
2259 (mips16_op_table): New table, for mips16 operands.
2260 (build_mips16_operands): New static function.
2261 (process_instructions): If PC is odd, decode a mips16
2262 instruction. Break out instruction handling into new
2263 build_instruction function.
2264 (build_instruction): New static function, broken out of
2265 process_instructions. Check modifiers rather than flags for SHIFT
2266 bit count and m[ft]{hi,lo} direction.
2267 (usage): Pass program name to fprintf.
2268 (main): Remove unused variable this_option_optind. Change
2269 ``*loptarg++'' to ``loptarg++''.
2270 (my_strtoul): Parenthesize && within ||.
2271 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2272 (simulate): If PC is odd, fetch a 16 bit instruction, and
2273 increment PC by 2 rather than 4.
2274 * configure.in: Add case for mips16*-*-*.
2275 * configure: Rebuild.
2277 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2279 * interp.c: Allow -t to enable tracing in standalone simulator.
2280 Fix garbage output in trace file and error messages.
2282 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2284 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2285 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2286 * configure.in: Simplify using macros in ../common/aclocal.m4.
2287 * configure: Regenerated.
2288 * tconfig.in: New file.
2290 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2292 * interp.c: Fix bugs in 64-bit port.
2293 Use ansi function declarations for msvc compiler.
2294 Initialize and test file pointer in trace code.
2295 Prevent duplicate definition of LAST_EMED_REGNUM.
2297 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2299 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2301 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2303 * interp.c (SignalException): Check for explicit terminating
2305 * gencode.c: Pass instruction value through SignalException()
2306 calls for Trap, Breakpoint and Syscall.
2308 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2310 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2311 only used on those hosts that provide it.
2312 * configure.in: Add sqrt() to list of functions to be checked for.
2313 * config.in: Re-generated.
2314 * configure: Re-generated.
2316 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2318 * gencode.c (process_instructions): Call build_endian_shift when
2319 expanding STORE RIGHT, to fix swr.
2320 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2321 clear the high bits.
2322 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2323 Fix float to int conversions to produce signed values.
2325 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2327 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2328 (process_instructions): Correct handling of nor instruction.
2329 Correct shift count for 32 bit shift instructions. Correct sign
2330 extension for arithmetic shifts to not shift the number of bits in
2331 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2332 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2334 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2335 It's OK to have a mult follow a mult. What's not OK is to have a
2336 mult follow an mfhi.
2337 (Convert): Comment out incorrect rounding code.
2339 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2341 * interp.c (sim_monitor): Improved monitor printf
2342 simulation. Tidied up simulator warnings, and added "--log" option
2343 for directing warning message output.
2344 * gencode.c: Use sim_warning() rather than WARNING macro.
2346 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2348 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2349 getopt1.o, rather than on gencode.c. Link objects together.
2350 Don't link against -liberty.
2351 (gencode.o, getopt.o, getopt1.o): New targets.
2352 * gencode.c: Include <ctype.h> and "ansidecl.h".
2353 (AND): Undefine after including "ansidecl.h".
2354 (ULONG_MAX): Define if not defined.
2355 (OP_*): Don't define macros; now defined in opcode/mips.h.
2356 (main): Call my_strtoul rather than strtoul.
2357 (my_strtoul): New static function.
2359 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2361 * gencode.c (process_instructions): Generate word64 and uword64
2362 instead of `long long' and `unsigned long long' data types.
2363 * interp.c: #include sysdep.h to get signals, and define default
2365 * (Convert): Work around for Visual-C++ compiler bug with type
2367 * support.h: Make things compile under Visual-C++ by using
2368 __int64 instead of `long long'. Change many refs to long long
2369 into word64/uword64 typedefs.
2371 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2373 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2374 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2376 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2377 (AC_PROG_INSTALL): Added.
2378 (AC_PROG_CC): Moved to before configure.host call.
2379 * configure: Rebuilt.
2381 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2383 * configure.in: Define @SIMCONF@ depending on mips target.
2384 * configure: Rebuild.
2385 * Makefile.in (run): Add @SIMCONF@ to control simulator
2387 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2388 * interp.c: Remove some debugging, provide more detailed error
2389 messages, update memory accesses to use LOADDRMASK.
2391 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2393 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2394 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2396 * configure: Rebuild.
2397 * config.in: New file, generated by autoheader.
2398 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2399 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2400 HAVE_ANINT and HAVE_AINT, as appropriate.
2401 * Makefile.in (run): Use @LIBS@ rather than -lm.
2402 (interp.o): Depend upon config.h.
2403 (Makefile): Just rebuild Makefile.
2404 (clean): Remove stamp-h.
2405 (mostlyclean): Make the same as clean, not as distclean.
2406 (config.h, stamp-h): New targets.
2408 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2410 * interp.c (ColdReset): Fix boolean test. Make all simulator
2413 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2415 * interp.c (xfer_direct_word, xfer_direct_long,
2416 swap_direct_word, swap_direct_long, xfer_big_word,
2417 xfer_big_long, xfer_little_word, xfer_little_long,
2418 swap_word,swap_long): Added.
2419 * interp.c (ColdReset): Provide function indirection to
2420 host<->simulated_target transfer routines.
2421 * interp.c (sim_store_register, sim_fetch_register): Updated to
2422 make use of indirected transfer routines.
2424 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2426 * gencode.c (process_instructions): Ensure FP ABS instruction
2428 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2429 system call support.
2431 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2433 * interp.c (sim_do_command): Complain if callback structure not
2436 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2438 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2439 support for Sun hosts.
2440 * Makefile.in (gencode): Ensure the host compiler and libraries
2441 used for cross-hosted build.
2443 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2445 * interp.c, gencode.c: Some more (TODO) tidying.
2447 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2449 * gencode.c, interp.c: Replaced explicit long long references with
2450 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2451 * support.h (SET64LO, SET64HI): Macros added.
2453 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2455 * configure: Regenerate with autoconf 2.7.
2457 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2459 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2460 * support.h: Remove superfluous "1" from #if.
2461 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2463 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2465 * interp.c (StoreFPR): Control UndefinedResult() call on
2466 WARN_RESULT manifest.
2468 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2470 * gencode.c: Tidied instruction decoding, and added FP instruction
2473 * interp.c: Added dineroIII, and BSD profiling support. Also
2474 run-time FP handling.
2476 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2478 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2479 gencode.c, interp.c, support.h: created.