1 2002-02-28 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
6 2002-02-27 Chris Demetriou <cgd@broadcom.com>
8 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
11 2002-02-27 Chris Demetriou <cgd@broadcom.com>
13 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
14 add a comma) so that it more closely match the MIPS ISA
15 documentation opcode partitioning.
16 (PREF): Put useful names on opcode fields, and include
17 instruction-printing string.
19 2002-02-27 Chris Demetriou <cgd@broadcom.com>
21 * mips.igen (check_u64): New function which in the future will
22 check whether 64-bit instructions are usable and signal an
23 exception if not. Currently a no-op.
24 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
25 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
26 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
27 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
29 * mips.igen (check_fpu): New function which in the future will
30 check whether FPU instructions are usable and signal an exception
31 if not. Currently a no-op.
32 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
33 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
34 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
35 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
36 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
37 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
38 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
39 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
41 2002-02-27 Chris Demetriou <cgd@broadcom.com>
43 * mips.igen (do_load_left, do_load_right): Move to be immediately
45 (do_store_left, do_store_right): Move to be immediately following
48 2002-02-27 Chris Demetriou <cgd@broadcom.com>
50 * mips.igen (mipsV): New model name. Also, add it to
51 all instructions and functions where it is appropriate.
53 2002-02-18 Chris Demetriou <cgd@broadcom.com>
55 * mips.igen: For all functions and instructions, list model
56 names that support that instruction one per line.
58 2002-02-11 Chris Demetriou <cgd@broadcom.com>
60 * mips.igen: Add some additional comments about supported
61 models, and about which instructions go where.
62 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
63 order as is used in the rest of the file.
65 2002-02-11 Chris Demetriou <cgd@broadcom.com>
67 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
68 indicating that ALU32_END or ALU64_END are there to check
70 (DADD): Likewise, but also remove previous comment about
73 2002-02-10 Chris Demetriou <cgd@broadcom.com>
75 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
76 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
77 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
78 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
79 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
80 fields (i.e., add and move commas) so that they more closely
81 match the MIPS ISA documentation opcode partitioning.
83 2002-02-10 Chris Demetriou <cgd@broadcom.com>
85 * mips.igen (ADDI): Print immediate value.
87 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
88 (SLL): Print "nop" specially, and don't run the code
89 that does the shift for the "nop" case.
91 2001-11-17 Fred Fish <fnf@redhat.com>
93 * sim-main.h (float_operation): Move enum declaration outside
94 of _sim_cpu struct declaration.
96 2001-04-12 Jim Blandy <jimb@redhat.com>
98 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
99 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
101 * sim-main.h (COCIDX): Remove definition; this isn't supported by
102 PENDING_FILL, and you can get the intended effect gracefully by
103 calling PENDING_SCHED directly.
105 2001-02-23 Ben Elliston <bje@redhat.com>
107 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
108 already defined elsewhere.
110 2001-02-19 Ben Elliston <bje@redhat.com>
112 * sim-main.h (sim_monitor): Return an int.
113 * interp.c (sim_monitor): Add return values.
114 (signal_exception): Handle error conditions from sim_monitor.
116 2001-02-08 Ben Elliston <bje@redhat.com>
118 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
119 (store_memory): Likewise, pass cia to sim_core_write*.
121 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
123 On advice from Chris G. Demetriou <cgd@sibyte.com>:
124 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
126 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
128 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
129 * Makefile.in: Don't delete *.igen when cleaning directory.
131 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
133 * m16.igen (break): Call SignalException not sim_engine_halt.
135 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
138 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
140 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
142 * mips.igen (MxC1, DMxC1): Fix printf formatting.
144 2000-05-24 Michael Hayes <mhayes@cygnus.com>
146 * mips.igen (do_dmultx): Fix typo.
148 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
150 * configure: Regenerated to track ../common/aclocal.m4 changes.
152 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
154 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
156 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
158 * sim-main.h (GPR_CLEAR): Define macro.
160 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
162 * interp.c (decode_coproc): Output long using %lx and not %s.
164 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
166 * interp.c (sim_open): Sort & extend dummy memory regions for
167 --board=jmr3904 for eCos.
169 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
171 * configure: Regenerated.
173 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
175 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
176 calls, conditional on the simulator being in verbose mode.
178 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
180 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
181 cache don't get ReservedInstruction traps.
183 1999-11-29 Mark Salter <msalter@cygnus.com>
185 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
186 to clear status bits in sdisr register. This is how the hardware works.
188 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
189 being used by cygmon.
191 1999-11-11 Andrew Haley <aph@cygnus.com>
193 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
196 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
198 * mips.igen (MULT): Correct previous mis-applied patch.
200 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
202 * mips.igen (delayslot32): Handle sequence like
203 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
204 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
205 (MULT): Actually pass the third register...
207 1999-09-03 Mark Salter <msalter@cygnus.com>
209 * interp.c (sim_open): Added more memory aliases for additional
210 hardware being touched by cygmon on jmr3904 board.
212 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
214 * configure: Regenerated to track ../common/aclocal.m4 changes.
216 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
218 * interp.c (sim_store_register): Handle case where client - GDB -
219 specifies that a 4 byte register is 8 bytes in size.
220 (sim_fetch_register): Ditto.
222 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
224 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
225 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
226 (idt_monitor_base): Base address for IDT monitor traps.
227 (pmon_monitor_base): Ditto for PMON.
228 (lsipmon_monitor_base): Ditto for LSI PMON.
229 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
230 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
231 (sim_firmware_command): New function.
232 (mips_option_handler): Call it for OPTION_FIRMWARE.
233 (sim_open): Allocate memory for idt_monitor region. If "--board"
234 option was given, add no monitor by default. Add BREAK hooks only if
235 monitors are also there.
237 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
239 * interp.c (sim_monitor): Flush output before reading input.
241 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
243 * tconfig.in (SIM_HANDLES_LMA): Always define.
245 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
247 From Mark Salter <msalter@cygnus.com>:
248 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
249 (sim_open): Add setup for BSP board.
251 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
253 * mips.igen (MULT, MULTU): Add syntax for two operand version.
254 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
255 them as unimplemented.
257 1999-05-08 Felix Lee <flee@cygnus.com>
259 * configure: Regenerated to track ../common/aclocal.m4 changes.
261 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
263 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
265 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
267 * configure.in: Any mips64vr5*-*-* target should have
268 -DTARGET_ENABLE_FR=1.
269 (default_endian): Any mips64vr*el-*-* target should default to
271 * configure: Re-generate.
273 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
275 * mips.igen (ldl): Extend from _16_, not 32.
277 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
279 * interp.c (sim_store_register): Force registers written to by GDB
280 into an un-interpreted state.
282 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
284 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
285 CPU, start periodic background I/O polls.
286 (tx3904sio_poll): New function: periodic I/O poller.
288 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
290 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
292 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
294 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
297 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
299 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
300 (load_word): Call SIM_CORE_SIGNAL hook on error.
301 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
302 starting. For exception dispatching, pass PC instead of NULL_CIA.
303 (decode_coproc): Use COP0_BADVADDR to store faulting address.
304 * sim-main.h (COP0_BADVADDR): Define.
305 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
306 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
307 (_sim_cpu): Add exc_* fields to store register value snapshots.
308 * mips.igen (*): Replace memory-related SignalException* calls
309 with references to SIM_CORE_SIGNAL hook.
311 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
313 * sim-main.c (*): Minor warning cleanups.
315 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
317 * m16.igen (DADDIU5): Correct type-o.
319 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
321 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
324 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
326 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
328 (interp.o): Add dependency on itable.h
329 (oengine.c, gencode): Delete remaining references.
330 (BUILT_SRC_FROM_GEN): Clean up.
332 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
335 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
336 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
338 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
339 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
340 Drop the "64" qualifier to get the HACK generator working.
341 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
342 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
343 qualifier to get the hack generator working.
344 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
346 (DSLLV): Use do_dsllv.
349 (DSRLV): Use do_dsrlv.
350 (BC1): Move *vr4100 to get the HACK generator working.
351 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
352 get the HACK generator working.
353 (MACC) Rename to get the HACK generator working.
354 (DMACC,MACCS,DMACCS): Add the 64.
356 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
358 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
359 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
361 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
363 * mips/interp.c (DEBUG): Cleanups.
365 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
367 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
368 (tx3904sio_tickle): fflush after a stdout character output.
370 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
372 * interp.c (sim_close): Uninstall modules.
374 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
376 * sim-main.h, interp.c (sim_monitor): Change to global
379 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
381 * configure.in (vr4100): Only include vr4100 instructions in
383 * configure: Re-generate.
384 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
386 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
388 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
389 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
392 * configure.in (sim_default_gen, sim_use_gen): Replace with
394 (--enable-sim-igen): Delete config option. Always using IGEN.
395 * configure: Re-generate.
397 * Makefile.in (gencode): Kill, kill, kill.
400 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
402 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
403 bit mips16 igen simulator.
404 * configure: Re-generate.
406 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
407 as part of vr4100 ISA.
408 * vr.igen: Mark all instructions as 64 bit only.
410 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
412 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
415 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
417 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
418 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
419 * configure: Re-generate.
421 * m16.igen (BREAK): Define breakpoint instruction.
422 (JALX32): Mark instruction as mips16 and not r3900.
423 * mips.igen (C.cond.fmt): Fix typo in instruction format.
425 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
427 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
429 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
430 insn as a debug breakpoint.
432 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
434 (PENDING_SCHED): Clean up trace statement.
435 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
436 (PENDING_FILL): Delay write by only one cycle.
437 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
439 * sim-main.c (pending_tick): Clean up trace statements. Add trace
441 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
443 (pending_tick): Move incrementing of index to FOR statement.
444 (pending_tick): Only update PENDING_OUT after a write has occured.
446 * configure.in: Add explicit mips-lsi-* target. Use gencode to
448 * configure: Re-generate.
450 * interp.c (sim_engine_run OLD): Delete explicit call to
451 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
453 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
455 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
456 interrupt level number to match changed SignalExceptionInterrupt
459 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
461 * interp.c: #include "itable.h" if WITH_IGEN.
462 (get_insn_name): New function.
463 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
464 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
466 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
468 * configure: Rebuilt to inhale new common/aclocal.m4.
470 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
472 * dv-tx3904sio.c: Include sim-assert.h.
474 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
476 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
477 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
478 Reorganize target-specific sim-hardware checks.
479 * configure: rebuilt.
480 * interp.c (sim_open): For tx39 target boards, set
481 OPERATING_ENVIRONMENT, add tx3904sio devices.
482 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
483 ROM executables. Install dv-sockser into sim-modules list.
485 * dv-tx3904irc.c: Compiler warning clean-up.
486 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
487 frequent hw-trace messages.
489 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
491 * vr.igen (MulAcc): Identify as a vr4100 specific function.
493 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
495 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
498 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
499 * mips.igen: Define vr4100 model. Include vr.igen.
500 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
502 * mips.igen (check_mf_hilo): Correct check.
504 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
506 * sim-main.h (interrupt_event): Add prototype.
508 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
509 register_ptr, register_value.
510 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
512 * sim-main.h (tracefh): Make extern.
514 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
516 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
517 Reduce unnecessarily high timer event frequency.
518 * dv-tx3904cpu.c: Ditto for interrupt event.
520 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
522 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
524 (interrupt_event): Made non-static.
526 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
527 interchange of configuration values for external vs. internal
530 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
532 * mips.igen (BREAK): Moved code to here for
533 simulator-reserved break instructions.
534 * gencode.c (build_instruction): Ditto.
535 * interp.c (signal_exception): Code moved from here. Non-
536 reserved instructions now use exception vector, rather
538 * sim-main.h: Moved magic constants to here.
540 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
542 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
543 register upon non-zero interrupt event level, clear upon zero
545 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
546 by passing zero event value.
547 (*_io_{read,write}_buffer): Endianness fixes.
548 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
549 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
551 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
552 serial I/O and timer module at base address 0xFFFF0000.
554 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
556 * mips.igen (SWC1) : Correct the handling of ReverseEndian
559 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
561 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
565 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
567 * dv-tx3904tmr.c: New file - implements tx3904 timer.
568 * dv-tx3904{irc,cpu}.c: Mild reformatting.
569 * configure.in: Include tx3904tmr in hw_device list.
570 * configure: Rebuilt.
571 * interp.c (sim_open): Instantiate three timer instances.
572 Fix address typo of tx3904irc instance.
574 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
576 * interp.c (signal_exception): SystemCall exception now uses
577 the exception vector.
579 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
581 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
584 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
586 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
588 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
590 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
592 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
593 sim-main.h. Declare a struct hw_descriptor instead of struct
594 hw_device_descriptor.
596 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
598 * mips.igen (do_store_left, do_load_left): Compute nr of left and
599 right bits and then re-align left hand bytes to correct byte
600 lanes. Fix incorrect computation in do_store_left when loading
601 bytes from second word.
603 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
605 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
606 * interp.c (sim_open): Only create a device tree when HW is
609 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
610 * interp.c (signal_exception): Ditto.
612 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
614 * gencode.c: Mark BEGEZALL as LIKELY.
616 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
618 * sim-main.h (ALU32_END): Sign extend 32 bit results.
619 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
621 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
623 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
624 modules. Recognize TX39 target with "mips*tx39" pattern.
625 * configure: Rebuilt.
626 * sim-main.h (*): Added many macros defining bits in
627 TX39 control registers.
628 (SignalInterrupt): Send actual PC instead of NULL.
629 (SignalNMIReset): New exception type.
630 * interp.c (board): New variable for future use to identify
631 a particular board being simulated.
632 (mips_option_handler,mips_options): Added "--board" option.
633 (interrupt_event): Send actual PC.
634 (sim_open): Make memory layout conditional on board setting.
635 (signal_exception): Initial implementation of hardware interrupt
636 handling. Accept another break instruction variant for simulator
638 (decode_coproc): Implement RFE instruction for TX39.
639 (mips.igen): Decode RFE instruction as such.
640 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
641 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
642 bbegin to implement memory map.
643 * dv-tx3904cpu.c: New file.
644 * dv-tx3904irc.c: New file.
646 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
648 * mips.igen (check_mt_hilo): Create a separate r3900 version.
650 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
652 * tx.igen (madd,maddu): Replace calls to check_op_hilo
653 with calls to check_div_hilo.
655 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
657 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
658 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
659 Add special r3900 version of do_mult_hilo.
660 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
661 with calls to check_mult_hilo.
662 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
663 with calls to check_div_hilo.
665 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
667 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
668 Document a replacement.
670 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
672 * interp.c (sim_monitor): Make mon_printf work.
674 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
676 * sim-main.h (INSN_NAME): New arg `cpu'.
678 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
680 * configure: Regenerated to track ../common/aclocal.m4 changes.
682 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
684 * configure: Regenerated to track ../common/aclocal.m4 changes.
687 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
689 * acconfig.h: New file.
690 * configure.in: Reverted change of Apr 24; use sinclude again.
692 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
694 * configure: Regenerated to track ../common/aclocal.m4 changes.
697 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
699 * configure.in: Don't call sinclude.
701 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
703 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
705 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
707 * mips.igen (ERET): Implement.
709 * interp.c (decode_coproc): Return sign-extended EPC.
711 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
713 * interp.c (signal_exception): Do not ignore Trap.
714 (signal_exception): On TRAP, restart at exception address.
715 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
716 (signal_exception): Update.
717 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
718 so that TRAP instructions are caught.
720 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
722 * sim-main.h (struct hilo_access, struct hilo_history): Define,
723 contains HI/LO access history.
724 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
725 (HIACCESS, LOACCESS): Delete, replace with
726 (HIHISTORY, LOHISTORY): New macros.
727 (CHECKHILO): Delete all, moved to mips.igen
729 * gencode.c (build_instruction): Do not generate checks for
730 correct HI/LO register usage.
732 * interp.c (old_engine_run): Delete checks for correct HI/LO
735 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
736 check_mf_cycles): New functions.
737 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
738 do_divu, domultx, do_mult, do_multu): Use.
740 * tx.igen ("madd", "maddu"): Use.
742 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
744 * mips.igen (DSRAV): Use function do_dsrav.
745 (SRAV): Use new function do_srav.
747 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
748 (B): Sign extend 11 bit immediate.
749 (EXT-B*): Shift 16 bit immediate left by 1.
750 (ADDIU*): Don't sign extend immediate value.
752 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
754 * m16run.c (sim_engine_run): Restore CIA after handling an event.
756 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
759 * mips.igen (delayslot32, nullify_next_insn): New functions.
760 (m16.igen): Always include.
761 (do_*): Add more tracing.
763 * m16.igen (delayslot16): Add NIA argument, could be called by a
764 32 bit MIPS16 instruction.
766 * interp.c (ifetch16): Move function from here.
767 * sim-main.c (ifetch16): To here.
769 * sim-main.c (ifetch16, ifetch32): Update to match current
770 implementations of LH, LW.
771 (signal_exception): Don't print out incorrect hex value of illegal
774 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
776 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
779 * m16.igen: Implement MIPS16 instructions.
781 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
782 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
783 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
784 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
785 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
786 bodies of corresponding code from 32 bit insn to these. Also used
787 by MIPS16 versions of functions.
789 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
790 (IMEM16): Drop NR argument from macro.
792 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
794 * Makefile.in (SIM_OBJS): Add sim-main.o.
796 * sim-main.h (address_translation, load_memory, store_memory,
797 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
799 (pr_addr, pr_uword64): Declare.
800 (sim-main.c): Include when H_REVEALS_MODULE_P.
802 * interp.c (address_translation, load_memory, store_memory,
803 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
805 * sim-main.c: To here. Fix compilation problems.
807 * configure.in: Enable inlining.
808 * configure: Re-config.
810 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
812 * configure: Regenerated to track ../common/aclocal.m4 changes.
814 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
816 * mips.igen: Include tx.igen.
817 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
818 * tx.igen: New file, contains MADD and MADDU.
820 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
821 the hardwired constant `7'.
822 (store_memory): Ditto.
823 (LOADDRMASK): Move definition to sim-main.h.
825 mips.igen (MTC0): Enable for r3900.
828 mips.igen (do_load_byte): Delete.
829 (do_load, do_store, do_load_left, do_load_write, do_store_left,
830 do_store_right): New functions.
831 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
833 configure.in: Let the tx39 use igen again.
836 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
838 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
839 not an address sized quantity. Return zero for cache sizes.
841 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
843 * mips.igen (r3900): r3900 does not support 64 bit integer
846 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
848 * configure.in (mipstx39*-*-*): Use gencode simulator rather
850 * configure : Rebuild.
852 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
854 * configure: Regenerated to track ../common/aclocal.m4 changes.
856 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
858 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
860 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
862 * configure: Regenerated to track ../common/aclocal.m4 changes.
863 * config.in: Regenerated to track ../common/aclocal.m4 changes.
865 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
867 * configure: Regenerated to track ../common/aclocal.m4 changes.
869 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
871 * interp.c (Max, Min): Comment out functions. Not yet used.
873 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
875 * configure: Regenerated to track ../common/aclocal.m4 changes.
877 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
879 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
880 configurable settings for stand-alone simulator.
882 * configure.in: Added X11 search, just in case.
884 * configure: Regenerated.
886 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
888 * interp.c (sim_write, sim_read, load_memory, store_memory):
889 Replace sim_core_*_map with read_map, write_map, exec_map resp.
891 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
893 * sim-main.h (GETFCC): Return an unsigned value.
895 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
897 * mips.igen (DIV): Fix check for -1 / MIN_INT.
898 (DADD): Result destination is RD not RT.
900 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
902 * sim-main.h (HIACCESS, LOACCESS): Always define.
904 * mdmx.igen (Maxi, Mini): Rename Max, Min.
906 * interp.c (sim_info): Delete.
908 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
910 * interp.c (DECLARE_OPTION_HANDLER): Use it.
911 (mips_option_handler): New argument `cpu'.
912 (sim_open): Update call to sim_add_option_table.
914 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
916 * mips.igen (CxC1): Add tracing.
918 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
920 * sim-main.h (Max, Min): Declare.
922 * interp.c (Max, Min): New functions.
924 * mips.igen (BC1): Add tracing.
926 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
928 * interp.c Added memory map for stack in vr4100
930 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
932 * interp.c (load_memory): Add missing "break"'s.
934 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
936 * interp.c (sim_store_register, sim_fetch_register): Pass in
937 length parameter. Return -1.
939 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
941 * interp.c: Added hardware init hook, fixed warnings.
943 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
945 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
947 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
949 * interp.c (ifetch16): New function.
951 * sim-main.h (IMEM32): Rename IMEM.
952 (IMEM16_IMMED): Define.
954 (DELAY_SLOT): Update.
956 * m16run.c (sim_engine_run): New file.
958 * m16.igen: All instructions except LB.
959 (LB): Call do_load_byte.
960 * mips.igen (do_load_byte): New function.
961 (LB): Call do_load_byte.
963 * mips.igen: Move spec for insn bit size and high bit from here.
964 * Makefile.in (tmp-igen, tmp-m16): To here.
966 * m16.dc: New file, decode mips16 instructions.
968 * Makefile.in (SIM_NO_ALL): Define.
969 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
971 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
973 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
974 point unit to 32 bit registers.
975 * configure: Re-generate.
977 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
979 * configure.in (sim_use_gen): Make IGEN the default simulator
980 generator for generic 32 and 64 bit mips targets.
981 * configure: Re-generate.
983 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
985 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
988 * interp.c (sim_fetch_register, sim_store_register): Read/write
989 FGR from correct location.
990 (sim_open): Set size of FGR's according to
991 WITH_TARGET_FLOATING_POINT_BITSIZE.
993 * sim-main.h (FGR): Store floating point registers in a separate
996 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
998 * configure: Regenerated to track ../common/aclocal.m4 changes.
1000 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1002 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1004 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1006 * interp.c (pending_tick): New function. Deliver pending writes.
1008 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1009 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1010 it can handle mixed sized quantites and single bits.
1012 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1014 * interp.c (oengine.h): Do not include when building with IGEN.
1015 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1016 (sim_info): Ditto for PROCESSOR_64BIT.
1017 (sim_monitor): Replace ut_reg with unsigned_word.
1018 (*): Ditto for t_reg.
1019 (LOADDRMASK): Define.
1020 (sim_open): Remove defunct check that host FP is IEEE compliant,
1021 using software to emulate floating point.
1022 (value_fpr, ...): Always compile, was conditional on HASFPU.
1024 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1026 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1029 * interp.c (SD, CPU): Define.
1030 (mips_option_handler): Set flags in each CPU.
1031 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1032 (sim_close): Do not clear STATE, deleted anyway.
1033 (sim_write, sim_read): Assume CPU zero's vm should be used for
1035 (sim_create_inferior): Set the PC for all processors.
1036 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1038 (mips16_entry): Pass correct nr of args to store_word, load_word.
1039 (ColdReset): Cold reset all cpu's.
1040 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1041 (sim_monitor, load_memory, store_memory, signal_exception): Use
1042 `CPU' instead of STATE_CPU.
1045 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1048 * sim-main.h (signal_exception): Add sim_cpu arg.
1049 (SignalException*): Pass both SD and CPU to signal_exception.
1050 * interp.c (signal_exception): Update.
1052 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1054 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1055 address_translation): Ditto
1056 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1058 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1060 * configure: Regenerated to track ../common/aclocal.m4 changes.
1062 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1064 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1066 * mips.igen (model): Map processor names onto BFD name.
1068 * sim-main.h (CPU_CIA): Delete.
1069 (SET_CIA, GET_CIA): Define
1071 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1073 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1076 * configure.in (default_endian): Configure a big-endian simulator
1078 * configure: Re-generate.
1080 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1082 * configure: Regenerated to track ../common/aclocal.m4 changes.
1084 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1086 * interp.c (sim_monitor): Handle Densan monitor outbyte
1087 and inbyte functions.
1089 1997-12-29 Felix Lee <flee@cygnus.com>
1091 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1093 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1095 * Makefile.in (tmp-igen): Arrange for $zero to always be
1096 reset to zero after every instruction.
1098 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1100 * configure: Regenerated to track ../common/aclocal.m4 changes.
1103 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1105 * mips.igen (MSUB): Fix to work like MADD.
1106 * gencode.c (MSUB): Similarly.
1108 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1110 * configure: Regenerated to track ../common/aclocal.m4 changes.
1112 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1114 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1116 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1118 * sim-main.h (sim-fpu.h): Include.
1120 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1121 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1122 using host independant sim_fpu module.
1124 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1126 * interp.c (signal_exception): Report internal errors with SIGABRT
1129 * sim-main.h (C0_CONFIG): New register.
1130 (signal.h): No longer include.
1132 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1134 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1136 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1138 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1140 * mips.igen: Tag vr5000 instructions.
1141 (ANDI): Was missing mipsIV model, fix assembler syntax.
1142 (do_c_cond_fmt): New function.
1143 (C.cond.fmt): Handle mips I-III which do not support CC field
1145 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1146 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1148 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1149 vr5000 which saves LO in a GPR separatly.
1151 * configure.in (enable-sim-igen): For vr5000, select vr5000
1152 specific instructions.
1153 * configure: Re-generate.
1155 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1157 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1159 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1160 fmt_uninterpreted_64 bit cases to switch. Convert to
1163 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1165 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1166 as specified in IV3.2 spec.
1167 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1169 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1171 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1172 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1173 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1174 PENDING_FILL versions of instructions. Simplify.
1176 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1178 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1180 (MTHI, MFHI): Disable code checking HI-LO.
1182 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1184 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1186 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1188 * gencode.c (build_mips16_operands): Replace IPC with cia.
1190 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1191 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1193 (UndefinedResult): Replace function with macro/function
1195 (sim_engine_run): Don't save PC in IPC.
1197 * sim-main.h (IPC): Delete.
1200 * interp.c (signal_exception, store_word, load_word,
1201 address_translation, load_memory, store_memory, cache_op,
1202 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1203 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1204 current instruction address - cia - argument.
1205 (sim_read, sim_write): Call address_translation directly.
1206 (sim_engine_run): Rename variable vaddr to cia.
1207 (signal_exception): Pass cia to sim_monitor
1209 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1210 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1211 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1213 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1214 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1217 * interp.c (signal_exception): Pass restart address to
1220 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1221 idecode.o): Add dependency.
1223 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1225 (DELAY_SLOT): Update NIA not PC with branch address.
1226 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1228 * mips.igen: Use CIA not PC in branch calculations.
1229 (illegal): Call SignalException.
1230 (BEQ, ADDIU): Fix assembler.
1232 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1234 * m16.igen (JALX): Was missing.
1236 * configure.in (enable-sim-igen): New configuration option.
1237 * configure: Re-generate.
1239 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1241 * interp.c (load_memory, store_memory): Delete parameter RAW.
1242 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1243 bypassing {load,store}_memory.
1245 * sim-main.h (ByteSwapMem): Delete definition.
1247 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1249 * interp.c (sim_do_command, sim_commands): Delete mips specific
1250 commands. Handled by module sim-options.
1252 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1253 (WITH_MODULO_MEMORY): Define.
1255 * interp.c (sim_info): Delete code printing memory size.
1257 * interp.c (mips_size): Nee sim_size, delete function.
1259 (monitor, monitor_base, monitor_size): Delete global variables.
1260 (sim_open, sim_close): Delete code creating monitor and other
1261 memory regions. Use sim-memopts module, via sim_do_commandf, to
1262 manage memory regions.
1263 (load_memory, store_memory): Use sim-core for memory model.
1265 * interp.c (address_translation): Delete all memory map code
1266 except line forcing 32 bit addresses.
1268 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1270 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1273 * interp.c (logfh, logfile): Delete globals.
1274 (sim_open, sim_close): Delete code opening & closing log file.
1275 (mips_option_handler): Delete -l and -n options.
1276 (OPTION mips_options): Ditto.
1278 * interp.c (OPTION mips_options): Rename option trace to dinero.
1279 (mips_option_handler): Update.
1281 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1283 * interp.c (fetch_str): New function.
1284 (sim_monitor): Rewrite using sim_read & sim_write.
1285 (sim_open): Check magic number.
1286 (sim_open): Write monitor vectors into memory using sim_write.
1287 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1288 (sim_read, sim_write): Simplify - transfer data one byte at a
1290 (load_memory, store_memory): Clarify meaning of parameter RAW.
1292 * sim-main.h (isHOST): Defete definition.
1293 (isTARGET): Mark as depreciated.
1294 (address_translation): Delete parameter HOST.
1296 * interp.c (address_translation): Delete parameter HOST.
1298 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1302 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1303 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1305 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1307 * mips.igen: Add model filter field to records.
1309 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1311 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1313 interp.c (sim_engine_run): Do not compile function sim_engine_run
1314 when WITH_IGEN == 1.
1316 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1317 target architecture.
1319 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1320 igen. Replace with configuration variables sim_igen_flags /
1323 * m16.igen: New file. Copy mips16 insns here.
1324 * mips.igen: From here.
1326 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1328 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1330 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1332 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1334 * gencode.c (build_instruction): Follow sim_write's lead in using
1335 BigEndianMem instead of !ByteSwapMem.
1337 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1339 * configure.in (sim_gen): Dependent on target, select type of
1340 generator. Always select old style generator.
1342 configure: Re-generate.
1344 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1346 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1347 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1348 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1349 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1350 SIM_@sim_gen@_*, set by autoconf.
1352 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1354 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1356 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1357 CURRENT_FLOATING_POINT instead.
1359 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1360 (address_translation): Raise exception InstructionFetch when
1361 translation fails and isINSTRUCTION.
1363 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1364 sim_engine_run): Change type of of vaddr and paddr to
1366 (address_translation, prefetch, load_memory, store_memory,
1367 cache_op): Change type of vAddr and pAddr to address_word.
1369 * gencode.c (build_instruction): Change type of vaddr and paddr to
1372 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1374 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1375 macro to obtain result of ALU op.
1377 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1379 * interp.c (sim_info): Call profile_print.
1381 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1383 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1385 * sim-main.h (WITH_PROFILE): Do not define, defined in
1386 common/sim-config.h. Use sim-profile module.
1387 (simPROFILE): Delete defintion.
1389 * interp.c (PROFILE): Delete definition.
1390 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1391 (sim_close): Delete code writing profile histogram.
1392 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1394 (sim_engine_run): Delete code profiling the PC.
1396 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1398 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1400 * interp.c (sim_monitor): Make register pointers of type
1403 * sim-main.h: Make registers of type unsigned_word not
1406 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1408 * interp.c (sync_operation): Rename from SyncOperation, make
1409 global, add SD argument.
1410 (prefetch): Rename from Prefetch, make global, add SD argument.
1411 (decode_coproc): Make global.
1413 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1415 * gencode.c (build_instruction): Generate DecodeCoproc not
1416 decode_coproc calls.
1418 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1419 (SizeFGR): Move to sim-main.h
1420 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1421 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1422 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1424 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1425 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1426 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1427 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1428 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1429 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1431 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1433 (sim-alu.h): Include.
1434 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1435 (sim_cia): Typedef to instruction_address.
1437 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1439 * Makefile.in (interp.o): Rename generated file engine.c to
1444 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1446 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1448 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1450 * gencode.c (build_instruction): For "FPSQRT", output correct
1451 number of arguments to Recip.
1453 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1455 * Makefile.in (interp.o): Depends on sim-main.h
1457 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1459 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1460 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1461 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1462 STATE, DSSTATE): Define
1463 (GPR, FGRIDX, ..): Define.
1465 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1466 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1467 (GPR, FGRIDX, ...): Delete macros.
1469 * interp.c: Update names to match defines from sim-main.h
1471 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1473 * interp.c (sim_monitor): Add SD argument.
1474 (sim_warning): Delete. Replace calls with calls to
1476 (sim_error): Delete. Replace calls with sim_io_error.
1477 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1478 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1479 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1481 (mips_size): Rename from sim_size. Add SD argument.
1483 * interp.c (simulator): Delete global variable.
1484 (callback): Delete global variable.
1485 (mips_option_handler, sim_open, sim_write, sim_read,
1486 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1487 sim_size,sim_monitor): Use sim_io_* not callback->*.
1488 (sim_open): ZALLOC simulator struct.
1489 (PROFILE): Do not define.
1491 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1493 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1494 support.h with corresponding code.
1496 * sim-main.h (word64, uword64), support.h: Move definition to
1498 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1501 * Makefile.in: Update dependencies
1502 * interp.c: Do not include.
1504 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1506 * interp.c (address_translation, load_memory, store_memory,
1507 cache_op): Rename to from AddressTranslation et.al., make global,
1510 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1513 * interp.c (SignalException): Rename to signal_exception, make
1516 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1518 * sim-main.h (SignalException, SignalExceptionInterrupt,
1519 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1520 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1521 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1524 * interp.c, support.h: Use.
1526 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1528 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1529 to value_fpr / store_fpr. Add SD argument.
1530 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1531 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1533 * sim-main.h (ValueFPR, StoreFPR): Define.
1535 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1537 * interp.c (sim_engine_run): Check consistency between configure
1538 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1541 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1542 (mips_fpu): Configure WITH_FLOATING_POINT.
1543 (mips_endian): Configure WITH_TARGET_ENDIAN.
1544 * configure: Update.
1546 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1548 * configure: Regenerated to track ../common/aclocal.m4 changes.
1550 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1552 * configure: Regenerated.
1554 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1556 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1558 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1560 * gencode.c (print_igen_insn_models): Assume certain architectures
1561 include all mips* instructions.
1562 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1565 * Makefile.in (tmp.igen): Add target. Generate igen input from
1568 * gencode.c (FEATURE_IGEN): Define.
1569 (main): Add --igen option. Generate output in igen format.
1570 (process_instructions): Format output according to igen option.
1571 (print_igen_insn_format): New function.
1572 (print_igen_insn_models): New function.
1573 (process_instructions): Only issue warnings and ignore
1574 instructions when no FEATURE_IGEN.
1576 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1578 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1581 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1583 * configure: Regenerated to track ../common/aclocal.m4 changes.
1585 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1587 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1588 SIM_RESERVED_BITS): Delete, moved to common.
1589 (SIM_EXTRA_CFLAGS): Update.
1591 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1593 * configure.in: Configure non-strict memory alignment.
1594 * configure: Regenerated to track ../common/aclocal.m4 changes.
1596 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1598 * configure: Regenerated to track ../common/aclocal.m4 changes.
1600 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1602 * gencode.c (SDBBP,DERET): Added (3900) insns.
1603 (RFE): Turn on for 3900.
1604 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1605 (dsstate): Made global.
1606 (SUBTARGET_R3900): Added.
1607 (CANCELDELAYSLOT): New.
1608 (SignalException): Ignore SystemCall rather than ignore and
1609 terminate. Add DebugBreakPoint handling.
1610 (decode_coproc): New insns RFE, DERET; and new registers Debug
1611 and DEPC protected by SUBTARGET_R3900.
1612 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1614 * Makefile.in,configure.in: Add mips subtarget option.
1615 * configure: Update.
1617 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1619 * gencode.c: Add r3900 (tx39).
1622 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1624 * gencode.c (build_instruction): Don't need to subtract 4 for
1627 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1629 * interp.c: Correct some HASFPU problems.
1631 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1633 * configure: Regenerated to track ../common/aclocal.m4 changes.
1635 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1637 * interp.c (mips_options): Fix samples option short form, should
1640 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1642 * interp.c (sim_info): Enable info code. Was just returning.
1644 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1646 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1649 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1651 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1653 (build_instruction): Ditto for LL.
1655 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1657 * configure: Regenerated to track ../common/aclocal.m4 changes.
1659 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1661 * configure: Regenerated to track ../common/aclocal.m4 changes.
1664 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1666 * interp.c (sim_open): Add call to sim_analyze_program, update
1669 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1671 * interp.c (sim_kill): Delete.
1672 (sim_create_inferior): Add ABFD argument. Set PC from same.
1673 (sim_load): Move code initializing trap handlers from here.
1674 (sim_open): To here.
1675 (sim_load): Delete, use sim-hload.c.
1677 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1679 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1681 * configure: Regenerated to track ../common/aclocal.m4 changes.
1684 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1686 * interp.c (sim_open): Add ABFD argument.
1687 (sim_load): Move call to sim_config from here.
1688 (sim_open): To here. Check return status.
1690 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1692 * gencode.c (build_instruction): Two arg MADD should
1693 not assign result to $0.
1695 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1697 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1698 * sim/mips/configure.in: Regenerate.
1700 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1702 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1703 signed8, unsigned8 et.al. types.
1705 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1706 hosts when selecting subreg.
1708 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1710 * interp.c (sim_engine_run): Reset the ZERO register to zero
1711 regardless of FEATURE_WARN_ZERO.
1712 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1714 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1716 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1717 (SignalException): For BreakPoints ignore any mode bits and just
1719 (SignalException): Always set the CAUSE register.
1721 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1723 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1724 exception has been taken.
1726 * interp.c: Implement the ERET and mt/f sr instructions.
1728 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1730 * interp.c (SignalException): Don't bother restarting an
1733 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1735 * interp.c (SignalException): Really take an interrupt.
1736 (interrupt_event): Only deliver interrupts when enabled.
1738 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1740 * interp.c (sim_info): Only print info when verbose.
1741 (sim_info) Use sim_io_printf for output.
1743 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1745 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1748 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1750 * interp.c (sim_do_command): Check for common commands if a
1751 simulator specific command fails.
1753 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1755 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1756 and simBE when DEBUG is defined.
1758 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1760 * interp.c (interrupt_event): New function. Pass exception event
1761 onto exception handler.
1763 * configure.in: Check for stdlib.h.
1764 * configure: Regenerate.
1766 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1767 variable declaration.
1768 (build_instruction): Initialize memval1.
1769 (build_instruction): Add UNUSED attribute to byte, bigend,
1771 (build_operands): Ditto.
1773 * interp.c: Fix GCC warnings.
1774 (sim_get_quit_code): Delete.
1776 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1777 * Makefile.in: Ditto.
1778 * configure: Re-generate.
1780 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1782 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1784 * interp.c (mips_option_handler): New function parse argumes using
1786 (myname): Replace with STATE_MY_NAME.
1787 (sim_open): Delete check for host endianness - performed by
1789 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1790 (sim_open): Move much of the initialization from here.
1791 (sim_load): To here. After the image has been loaded and
1793 (sim_open): Move ColdReset from here.
1794 (sim_create_inferior): To here.
1795 (sim_open): Make FP check less dependant on host endianness.
1797 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1799 * interp.c (sim_set_callbacks): Delete.
1801 * interp.c (membank, membank_base, membank_size): Replace with
1802 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1803 (sim_open): Remove call to callback->init. gdb/run do this.
1807 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1809 * interp.c (big_endian_p): Delete, replaced by
1810 current_target_byte_order.
1812 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1814 * interp.c (host_read_long, host_read_word, host_swap_word,
1815 host_swap_long): Delete. Using common sim-endian.
1816 (sim_fetch_register, sim_store_register): Use H2T.
1817 (pipeline_ticks): Delete. Handled by sim-events.
1819 (sim_engine_run): Update.
1821 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1823 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1825 (SignalException): To here. Signal using sim_engine_halt.
1826 (sim_stop_reason): Delete, moved to common.
1828 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1830 * interp.c (sim_open): Add callback argument.
1831 (sim_set_callbacks): Delete SIM_DESC argument.
1834 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1836 * Makefile.in (SIM_OBJS): Add common modules.
1838 * interp.c (sim_set_callbacks): Also set SD callback.
1839 (set_endianness, xfer_*, swap_*): Delete.
1840 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1841 Change to functions using sim-endian macros.
1842 (control_c, sim_stop): Delete, use common version.
1843 (simulate): Convert into.
1844 (sim_engine_run): This function.
1845 (sim_resume): Delete.
1847 * interp.c (simulation): New variable - the simulator object.
1848 (sim_kind): Delete global - merged into simulation.
1849 (sim_load): Cleanup. Move PC assignment from here.
1850 (sim_create_inferior): To here.
1852 * sim-main.h: New file.
1853 * interp.c (sim-main.h): Include.
1855 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1857 * configure: Regenerated to track ../common/aclocal.m4 changes.
1859 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1861 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1863 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1865 * gencode.c (build_instruction): DIV instructions: check
1866 for division by zero and integer overflow before using
1867 host's division operation.
1869 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1871 * Makefile.in (SIM_OBJS): Add sim-load.o.
1872 * interp.c: #include bfd.h.
1873 (target_byte_order): Delete.
1874 (sim_kind, myname, big_endian_p): New static locals.
1875 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1876 after argument parsing. Recognize -E arg, set endianness accordingly.
1877 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1878 load file into simulator. Set PC from bfd.
1879 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1880 (set_endianness): Use big_endian_p instead of target_byte_order.
1882 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1884 * interp.c (sim_size): Delete prototype - conflicts with
1885 definition in remote-sim.h. Correct definition.
1887 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1889 * configure: Regenerated to track ../common/aclocal.m4 changes.
1892 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1894 * interp.c (sim_open): New arg `kind'.
1896 * configure: Regenerated to track ../common/aclocal.m4 changes.
1898 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1900 * configure: Regenerated to track ../common/aclocal.m4 changes.
1902 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1904 * interp.c (sim_open): Set optind to 0 before calling getopt.
1906 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1908 * configure: Regenerated to track ../common/aclocal.m4 changes.
1910 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1912 * interp.c : Replace uses of pr_addr with pr_uword64
1913 where the bit length is always 64 independent of SIM_ADDR.
1914 (pr_uword64) : added.
1916 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1918 * configure: Re-generate.
1920 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1922 * configure: Regenerate to track ../common/aclocal.m4 changes.
1924 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1926 * interp.c (sim_open): New SIM_DESC result. Argument is now
1928 (other sim_*): New SIM_DESC argument.
1930 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1932 * interp.c: Fix printing of addresses for non-64-bit targets.
1933 (pr_addr): Add function to print address based on size.
1935 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1937 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1939 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1941 * gencode.c (build_mips16_operands): Correct computation of base
1942 address for extended PC relative instruction.
1944 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1946 * interp.c (mips16_entry): Add support for floating point cases.
1947 (SignalException): Pass floating point cases to mips16_entry.
1948 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1950 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1952 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1953 and then set the state to fmt_uninterpreted.
1954 (COP_SW): Temporarily set the state to fmt_word while calling
1957 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1959 * gencode.c (build_instruction): The high order may be set in the
1960 comparison flags at any ISA level, not just ISA 4.
1962 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1964 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1965 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1966 * configure.in: sinclude ../common/aclocal.m4.
1967 * configure: Regenerated.
1969 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1971 * configure: Rebuild after change to aclocal.m4.
1973 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1975 * configure configure.in Makefile.in: Update to new configure
1976 scheme which is more compatible with WinGDB builds.
1977 * configure.in: Improve comment on how to run autoconf.
1978 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1979 * Makefile.in: Use autoconf substitution to install common
1982 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1984 * gencode.c (build_instruction): Use BigEndianCPU instead of
1987 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1989 * interp.c (sim_monitor): Make output to stdout visible in
1990 wingdb's I/O log window.
1992 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1994 * support.h: Undo previous change to SIGTRAP
1997 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1999 * interp.c (store_word, load_word): New static functions.
2000 (mips16_entry): New static function.
2001 (SignalException): Look for mips16 entry and exit instructions.
2002 (simulate): Use the correct index when setting fpr_state after
2003 doing a pending move.
2005 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2007 * interp.c: Fix byte-swapping code throughout to work on
2008 both little- and big-endian hosts.
2010 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2012 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2013 with gdb/config/i386/xm-windows.h.
2015 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2017 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2018 that messes up arithmetic shifts.
2020 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2022 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2023 SIGTRAP and SIGQUIT for _WIN32.
2025 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2027 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2028 force a 64 bit multiplication.
2029 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2030 destination register is 0, since that is the default mips16 nop
2033 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2035 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2036 (build_endian_shift): Don't check proc64.
2037 (build_instruction): Always set memval to uword64. Cast op2 to
2038 uword64 when shifting it left in memory instructions. Always use
2039 the same code for stores--don't special case proc64.
2041 * gencode.c (build_mips16_operands): Fix base PC value for PC
2043 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2045 * interp.c (simJALDELAYSLOT): Define.
2046 (JALDELAYSLOT): Define.
2047 (INDELAYSLOT, INJALDELAYSLOT): Define.
2048 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2050 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2052 * interp.c (sim_open): add flush_cache as a PMON routine
2053 (sim_monitor): handle flush_cache by ignoring it
2055 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2057 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2059 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2060 (BigEndianMem): Rename to ByteSwapMem and change sense.
2061 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2062 BigEndianMem references to !ByteSwapMem.
2063 (set_endianness): New function, with prototype.
2064 (sim_open): Call set_endianness.
2065 (sim_info): Use simBE instead of BigEndianMem.
2066 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2067 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2068 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2069 ifdefs, keeping the prototype declaration.
2070 (swap_word): Rewrite correctly.
2071 (ColdReset): Delete references to CONFIG. Delete endianness related
2072 code; moved to set_endianness.
2074 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2076 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2077 * interp.c (CHECKHILO): Define away.
2078 (simSIGINT): New macro.
2079 (membank_size): Increase from 1MB to 2MB.
2080 (control_c): New function.
2081 (sim_resume): Rename parameter signal to signal_number. Add local
2082 variable prev. Call signal before and after simulate.
2083 (sim_stop_reason): Add simSIGINT support.
2084 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2086 (sim_warning): Delete call to SignalException. Do call printf_filtered
2088 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2089 a call to sim_warning.
2091 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2093 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2094 16 bit instructions.
2096 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2098 Add support for mips16 (16 bit MIPS implementation):
2099 * gencode.c (inst_type): Add mips16 instruction encoding types.
2100 (GETDATASIZEINSN): Define.
2101 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2102 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2104 (MIPS16_DECODE): New table, for mips16 instructions.
2105 (bitmap_val): New static function.
2106 (struct mips16_op): Define.
2107 (mips16_op_table): New table, for mips16 operands.
2108 (build_mips16_operands): New static function.
2109 (process_instructions): If PC is odd, decode a mips16
2110 instruction. Break out instruction handling into new
2111 build_instruction function.
2112 (build_instruction): New static function, broken out of
2113 process_instructions. Check modifiers rather than flags for SHIFT
2114 bit count and m[ft]{hi,lo} direction.
2115 (usage): Pass program name to fprintf.
2116 (main): Remove unused variable this_option_optind. Change
2117 ``*loptarg++'' to ``loptarg++''.
2118 (my_strtoul): Parenthesize && within ||.
2119 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2120 (simulate): If PC is odd, fetch a 16 bit instruction, and
2121 increment PC by 2 rather than 4.
2122 * configure.in: Add case for mips16*-*-*.
2123 * configure: Rebuild.
2125 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2127 * interp.c: Allow -t to enable tracing in standalone simulator.
2128 Fix garbage output in trace file and error messages.
2130 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2132 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2133 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2134 * configure.in: Simplify using macros in ../common/aclocal.m4.
2135 * configure: Regenerated.
2136 * tconfig.in: New file.
2138 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2140 * interp.c: Fix bugs in 64-bit port.
2141 Use ansi function declarations for msvc compiler.
2142 Initialize and test file pointer in trace code.
2143 Prevent duplicate definition of LAST_EMED_REGNUM.
2145 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2147 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2149 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2151 * interp.c (SignalException): Check for explicit terminating
2153 * gencode.c: Pass instruction value through SignalException()
2154 calls for Trap, Breakpoint and Syscall.
2156 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2158 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2159 only used on those hosts that provide it.
2160 * configure.in: Add sqrt() to list of functions to be checked for.
2161 * config.in: Re-generated.
2162 * configure: Re-generated.
2164 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2166 * gencode.c (process_instructions): Call build_endian_shift when
2167 expanding STORE RIGHT, to fix swr.
2168 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2169 clear the high bits.
2170 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2171 Fix float to int conversions to produce signed values.
2173 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2175 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2176 (process_instructions): Correct handling of nor instruction.
2177 Correct shift count for 32 bit shift instructions. Correct sign
2178 extension for arithmetic shifts to not shift the number of bits in
2179 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2180 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2182 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2183 It's OK to have a mult follow a mult. What's not OK is to have a
2184 mult follow an mfhi.
2185 (Convert): Comment out incorrect rounding code.
2187 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2189 * interp.c (sim_monitor): Improved monitor printf
2190 simulation. Tidied up simulator warnings, and added "--log" option
2191 for directing warning message output.
2192 * gencode.c: Use sim_warning() rather than WARNING macro.
2194 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2196 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2197 getopt1.o, rather than on gencode.c. Link objects together.
2198 Don't link against -liberty.
2199 (gencode.o, getopt.o, getopt1.o): New targets.
2200 * gencode.c: Include <ctype.h> and "ansidecl.h".
2201 (AND): Undefine after including "ansidecl.h".
2202 (ULONG_MAX): Define if not defined.
2203 (OP_*): Don't define macros; now defined in opcode/mips.h.
2204 (main): Call my_strtoul rather than strtoul.
2205 (my_strtoul): New static function.
2207 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2209 * gencode.c (process_instructions): Generate word64 and uword64
2210 instead of `long long' and `unsigned long long' data types.
2211 * interp.c: #include sysdep.h to get signals, and define default
2213 * (Convert): Work around for Visual-C++ compiler bug with type
2215 * support.h: Make things compile under Visual-C++ by using
2216 __int64 instead of `long long'. Change many refs to long long
2217 into word64/uword64 typedefs.
2219 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2221 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2222 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2224 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2225 (AC_PROG_INSTALL): Added.
2226 (AC_PROG_CC): Moved to before configure.host call.
2227 * configure: Rebuilt.
2229 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2231 * configure.in: Define @SIMCONF@ depending on mips target.
2232 * configure: Rebuild.
2233 * Makefile.in (run): Add @SIMCONF@ to control simulator
2235 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2236 * interp.c: Remove some debugging, provide more detailed error
2237 messages, update memory accesses to use LOADDRMASK.
2239 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2241 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2242 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2244 * configure: Rebuild.
2245 * config.in: New file, generated by autoheader.
2246 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2247 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2248 HAVE_ANINT and HAVE_AINT, as appropriate.
2249 * Makefile.in (run): Use @LIBS@ rather than -lm.
2250 (interp.o): Depend upon config.h.
2251 (Makefile): Just rebuild Makefile.
2252 (clean): Remove stamp-h.
2253 (mostlyclean): Make the same as clean, not as distclean.
2254 (config.h, stamp-h): New targets.
2256 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2258 * interp.c (ColdReset): Fix boolean test. Make all simulator
2261 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2263 * interp.c (xfer_direct_word, xfer_direct_long,
2264 swap_direct_word, swap_direct_long, xfer_big_word,
2265 xfer_big_long, xfer_little_word, xfer_little_long,
2266 swap_word,swap_long): Added.
2267 * interp.c (ColdReset): Provide function indirection to
2268 host<->simulated_target transfer routines.
2269 * interp.c (sim_store_register, sim_fetch_register): Updated to
2270 make use of indirected transfer routines.
2272 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2274 * gencode.c (process_instructions): Ensure FP ABS instruction
2276 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2277 system call support.
2279 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2281 * interp.c (sim_do_command): Complain if callback structure not
2284 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2286 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2287 support for Sun hosts.
2288 * Makefile.in (gencode): Ensure the host compiler and libraries
2289 used for cross-hosted build.
2291 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2293 * interp.c, gencode.c: Some more (TODO) tidying.
2295 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2297 * gencode.c, interp.c: Replaced explicit long long references with
2298 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2299 * support.h (SET64LO, SET64HI): Macros added.
2301 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2303 * configure: Regenerate with autoconf 2.7.
2305 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2307 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2308 * support.h: Remove superfluous "1" from #if.
2309 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2311 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2313 * interp.c (StoreFPR): Control UndefinedResult() call on
2314 WARN_RESULT manifest.
2316 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2318 * gencode.c: Tidied instruction decoding, and added FP instruction
2321 * interp.c: Added dineroIII, and BSD profiling support. Also
2322 run-time FP handling.
2324 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2326 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2327 gencode.c, interp.c, support.h: created.
projects / external / binutils.git / blob