1 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
3 * interp.c: Don't include sysdep.h
5 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
7 * configure: Regenerate.
9 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
11 * config.in: Regenerate.
12 * configure: Likewise.
14 * configure: Regenerate.
16 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
18 * configure: Regenerate to track ../common/common.m4 changes.
21 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
22 Daniel Jacobowitz <dan@codesourcery.com>
23 Joseph Myers <joseph@codesourcery.com>
25 * configure: Regenerate.
27 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
29 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
30 that unconditionally allows fmt_ps.
31 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
32 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
33 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
34 filter from 64,f to 32,f.
35 (PREFX): Change filter from 64 to 32.
36 (LDXC1, LUXC1): Provide separate mips32r2 implementations
37 that use do_load_double instead of do_load. Make both LUXC1
38 versions unpredictable if SizeFGR () != 64.
39 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
40 instead of do_store. Remove unused variable. Make both SUXC1
41 versions unpredictable if SizeFGR () != 64.
43 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
45 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
46 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
49 2007-09-04 Nick Clifton <nickc@redhat.com>
51 * interp.c (options enum): Add OPTION_INFO_MEMORY.
52 (display_mem_info): New static variable.
53 (mips_option_handler): Handle OPTION_INFO_MEMORY.
54 (mips_options): Add info-memory and memory-info.
55 (sim_open): After processing the command line and board
56 specification, check display_mem_info. If it is set then
57 call the real handler for the --memory-info command line
60 2007-08-24 Joel Brobecker <brobecker@adacore.com>
62 * configure.ac: Change license of multi-run.c to GPL version 3.
63 * configure: Regenerate.
65 2007-06-28 Richard Sandiford <richard@codesourcery.com>
67 * configure.ac, configure: Revert last patch.
69 2007-06-26 Richard Sandiford <richard@codesourcery.com>
71 * configure.ac (sim_mipsisa3264_configs): New variable.
72 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
73 every configuration support all four targets, using the triplet to
74 determine the default.
75 * configure: Regenerate.
77 2007-06-25 Richard Sandiford <richard@codesourcery.com>
79 * Makefile.in (m16run.o): New rule.
81 2007-05-15 Thiemo Seufer <ths@mips.com>
83 * mips3264r2.igen (DSHD): Fix compile warning.
85 2007-05-14 Thiemo Seufer <ths@mips.com>
87 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
88 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
89 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
90 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
93 2007-03-01 Thiemo Seufer <ths@mips.com>
95 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
98 2007-02-20 Thiemo Seufer <ths@mips.com>
100 * dsp.igen: Update copyright notice.
101 * dsp2.igen: Fix copyright notice.
103 2007-02-20 Thiemo Seufer <ths@mips.com>
104 Chao-Ying Fu <fu@mips.com>
106 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
107 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
108 Add dsp2 to sim_igen_machine.
109 * configure: Regenerate.
110 * dsp.igen (do_ph_op): Add MUL support when op = 2.
111 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
112 (mulq_rs.ph): Use do_ph_mulq.
113 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
114 * mips.igen: Add dsp2 model and include dsp2.igen.
115 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
116 for *mips32r2, *mips64r2, *dsp.
117 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
118 for *mips32r2, *mips64r2, *dsp2.
119 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
121 2007-02-19 Thiemo Seufer <ths@mips.com>
122 Nigel Stephens <nigel@mips.com>
124 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
125 jumps with hazard barrier.
127 2007-02-19 Thiemo Seufer <ths@mips.com>
128 Nigel Stephens <nigel@mips.com>
130 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
131 after each call to sim_io_write.
133 2007-02-19 Thiemo Seufer <ths@mips.com>
134 Nigel Stephens <nigel@mips.com>
136 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
137 supported by this simulator.
138 (decode_coproc): Recognise additional CP0 Config registers
141 2007-02-19 Thiemo Seufer <ths@mips.com>
142 Nigel Stephens <nigel@mips.com>
143 David Ung <davidu@mips.com>
145 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
146 uninterpreted formats. If fmt is one of the uninterpreted types
147 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
148 fmt_word, and fmt_uninterpreted_64 like fmt_long.
149 (store_fpr): When writing an invalid odd register, set the
150 matching even register to fmt_unknown, not the following register.
151 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
152 the the memory window at offset 0 set by --memory-size command
154 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
156 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
158 (sim_monitor): When returning the memory size to the MIPS
159 application, use the value in STATE_MEM_SIZE, not an arbitrary
161 (cop_lw): Don' mess around with FPR_STATE, just pass
162 fmt_uninterpreted_32 to StoreFPR.
164 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
166 * mips.igen (not_word_value): Single version for mips32, mips64
169 2007-02-19 Thiemo Seufer <ths@mips.com>
170 Nigel Stephens <nigel@mips.com>
172 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
175 2007-02-17 Thiemo Seufer <ths@mips.com>
177 * configure.ac (mips*-sde-elf*): Move in front of generic machine
179 * configure: Regenerate.
181 2007-02-17 Thiemo Seufer <ths@mips.com>
183 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
184 Add mdmx to sim_igen_machine.
185 (mipsisa64*-*-*): Likewise. Remove dsp.
186 (mipsisa32*-*-*): Remove dsp.
187 * configure: Regenerate.
189 2007-02-13 Thiemo Seufer <ths@mips.com>
191 * configure.ac: Add mips*-sde-elf* target.
192 * configure: Regenerate.
194 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
196 * acconfig.h: Remove.
197 * config.in, configure: Regenerate.
199 2006-11-07 Thiemo Seufer <ths@mips.com>
201 * dsp.igen (do_w_op): Fix compiler warning.
203 2006-08-29 Thiemo Seufer <ths@mips.com>
204 David Ung <davidu@mips.com>
206 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
208 * configure: Regenerate.
209 * mips.igen (model): Add smartmips.
210 (MADDU): Increment ACX if carry.
211 (do_mult): Clear ACX.
212 (ROR,RORV): Add smartmips.
213 (include): Include smartmips.igen.
214 * sim-main.h (ACX): Set to REGISTERS[89].
215 * smartmips.igen: New file.
217 2006-08-29 Thiemo Seufer <ths@mips.com>
218 David Ung <davidu@mips.com>
220 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
221 mips3264r2.igen. Add missing dependency rules.
222 * m16e.igen: Support for mips16e save/restore instructions.
224 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
226 * configure: Regenerated.
228 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
230 * configure: Regenerated.
232 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
234 * configure: Regenerated.
236 2006-05-15 Chao-ying Fu <fu@mips.com>
238 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
240 2006-04-18 Nick Clifton <nickc@redhat.com>
242 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
245 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
247 * configure: Regenerate.
249 2005-12-14 Chao-ying Fu <fu@mips.com>
251 * Makefile.in (SIM_OBJS): Add dsp.o.
252 (dsp.o): New dependency.
253 (IGEN_INCLUDE): Add dsp.igen.
254 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
255 mipsisa64*-*-*): Add dsp to sim_igen_machine.
256 * configure: Regenerate.
257 * mips.igen: Add dsp model and include dsp.igen.
258 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
259 because these instructions are extended in DSP ASE.
260 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
261 adding 6 DSP accumulator registers and 1 DSP control register.
262 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
263 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
264 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
265 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
266 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
267 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
268 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
269 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
270 DSPCR_CCOND_SMASK): New define.
271 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
272 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
274 2005-07-08 Ian Lance Taylor <ian@airs.com>
276 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
278 2005-06-16 David Ung <davidu@mips.com>
279 Nigel Stephens <nigel@mips.com>
281 * mips.igen: New mips16e model and include m16e.igen.
282 (check_u64): Add mips16e tag.
283 * m16e.igen: New file for MIPS16e instructions.
284 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
285 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
287 * configure: Regenerate.
289 2005-05-26 David Ung <davidu@mips.com>
291 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
292 tags to all instructions which are applicable to the new ISAs.
293 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
295 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
297 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
299 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
300 * configure: Regenerate.
302 2005-03-23 Mark Kettenis <kettenis@gnu.org>
304 * configure: Regenerate.
306 2005-01-14 Andrew Cagney <cagney@gnu.org>
308 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
309 explicit call to AC_CONFIG_HEADER.
310 * configure: Regenerate.
312 2005-01-12 Andrew Cagney <cagney@gnu.org>
314 * configure.ac: Update to use ../common/common.m4.
315 * configure: Re-generate.
317 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
319 * configure: Regenerated to track ../common/aclocal.m4 changes.
321 2005-01-07 Andrew Cagney <cagney@gnu.org>
323 * configure.ac: Rename configure.in, require autoconf 2.59.
324 * configure: Re-generate.
326 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
328 * configure: Regenerate for ../common/aclocal.m4 update.
330 2004-09-24 Monika Chaddha <monika@acmet.com>
332 Committed by Andrew Cagney.
333 * m16.igen (CMP, CMPI): Fix assembler.
335 2004-08-18 Chris Demetriou <cgd@broadcom.com>
337 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
338 * configure: Regenerate.
340 2004-06-25 Chris Demetriou <cgd@broadcom.com>
342 * configure.in (sim_m16_machine): Include mipsIII.
343 * configure: Regenerate.
345 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
347 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
349 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
351 2004-04-10 Chris Demetriou <cgd@broadcom.com>
353 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
355 2004-04-09 Chris Demetriou <cgd@broadcom.com>
357 * mips.igen (check_fmt): Remove.
358 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
359 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
360 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
361 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
362 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
363 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
364 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
365 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
366 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
367 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
369 2004-04-09 Chris Demetriou <cgd@broadcom.com>
371 * sb1.igen (check_sbx): New function.
372 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
374 2004-03-29 Chris Demetriou <cgd@broadcom.com>
375 Richard Sandiford <rsandifo@redhat.com>
377 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
378 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
379 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
380 separate implementations for mipsIV and mipsV. Use new macros to
381 determine whether the restrictions apply.
383 2004-01-19 Chris Demetriou <cgd@broadcom.com>
385 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
386 (check_mult_hilo): Improve comments.
387 (check_div_hilo): Likewise. Also, fork off a new version
388 to handle mips32/mips64 (since there are no hazards to check
391 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
393 * mips.igen (do_dmultx): Fix check for negative operands.
395 2003-05-16 Ian Lance Taylor <ian@airs.com>
397 * Makefile.in (SHELL): Make sure this is defined.
398 (various): Use $(SHELL) whenever we invoke move-if-change.
400 2003-05-03 Chris Demetriou <cgd@broadcom.com>
402 * cp1.c: Tweak attribution slightly.
405 * mdmx.igen: Likewise.
406 * mips3d.igen: Likewise.
407 * sb1.igen: Likewise.
409 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
411 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
414 2003-02-27 Andrew Cagney <cagney@redhat.com>
416 * interp.c (sim_open): Rename _bfd to bfd.
417 (sim_create_inferior): Ditto.
419 2003-01-14 Chris Demetriou <cgd@broadcom.com>
421 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
423 2003-01-14 Chris Demetriou <cgd@broadcom.com>
425 * mips.igen (EI, DI): Remove.
427 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
429 * Makefile.in (tmp-run-multi): Fix mips16 filter.
431 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
432 Andrew Cagney <ac131313@redhat.com>
433 Gavin Romig-Koch <gavin@redhat.com>
434 Graydon Hoare <graydon@redhat.com>
435 Aldy Hernandez <aldyh@redhat.com>
436 Dave Brolley <brolley@redhat.com>
437 Chris Demetriou <cgd@broadcom.com>
439 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
440 (sim_mach_default): New variable.
441 (mips64vr-*-*, mips64vrel-*-*): New configurations.
442 Add a new simulator generator, MULTI.
443 * configure: Regenerate.
444 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
445 (multi-run.o): New dependency.
446 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
447 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
448 (tmp-multi): Combine them.
449 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
450 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
451 (distclean-extra): New rule.
452 * sim-main.h: Include bfd.h.
453 (MIPS_MACH): New macro.
454 * mips.igen (vr4120, vr5400, vr5500): New models.
455 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
456 * vr.igen: Replace with new version.
458 2003-01-04 Chris Demetriou <cgd@broadcom.com>
460 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
461 * configure: Regenerate.
463 2002-12-31 Chris Demetriou <cgd@broadcom.com>
465 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
466 * mips.igen: Remove all invocations of check_branch_bug and
469 2002-12-16 Chris Demetriou <cgd@broadcom.com>
471 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
473 2002-07-30 Chris Demetriou <cgd@broadcom.com>
475 * mips.igen (do_load_double, do_store_double): New functions.
476 (LDC1, SDC1): Rename to...
477 (LDC1b, SDC1b): respectively.
478 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
480 2002-07-29 Michael Snyder <msnyder@redhat.com>
482 * cp1.c (fp_recip2): Modify initialization expression so that
483 GCC will recognize it as constant.
485 2002-06-18 Chris Demetriou <cgd@broadcom.com>
487 * mdmx.c (SD_): Delete.
488 (Unpredictable): Re-define, for now, to directly invoke
489 unpredictable_action().
490 (mdmx_acc_op): Fix error in .ob immediate handling.
492 2002-06-18 Andrew Cagney <cagney@redhat.com>
494 * interp.c (sim_firmware_command): Initialize `address'.
496 2002-06-16 Andrew Cagney <ac131313@redhat.com>
498 * configure: Regenerated to track ../common/aclocal.m4 changes.
500 2002-06-14 Chris Demetriou <cgd@broadcom.com>
501 Ed Satterthwaite <ehs@broadcom.com>
503 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
504 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
505 * mips.igen: Include mips3d.igen.
506 (mips3d): New model name for MIPS-3D ASE instructions.
507 (CVT.W.fmt): Don't use this instruction for word (source) format
509 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
510 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
511 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
512 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
513 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
514 (RSquareRoot1, RSquareRoot2): New macros.
515 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
516 (fp_rsqrt2): New functions.
517 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
518 * configure: Regenerate.
520 2002-06-13 Chris Demetriou <cgd@broadcom.com>
521 Ed Satterthwaite <ehs@broadcom.com>
523 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
524 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
525 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
526 (convert): Note that this function is not used for paired-single
528 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
529 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
530 (check_fmt_p): Enable paired-single support.
531 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
532 (PUU.PS): New instructions.
533 (CVT.S.fmt): Don't use this instruction for paired-single format
535 * sim-main.h (FP_formats): New value 'fmt_ps.'
536 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
537 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
539 2002-06-12 Chris Demetriou <cgd@broadcom.com>
541 * mips.igen: Fix formatting of function calls in
544 2002-06-12 Chris Demetriou <cgd@broadcom.com>
546 * mips.igen (MOVN, MOVZ): Trace result.
547 (TNEI): Print "tnei" as the opcode name in traces.
548 (CEIL.W): Add disassembly string for traces.
549 (RSQRT.fmt): Make location of disassembly string consistent
550 with other instructions.
552 2002-06-12 Chris Demetriou <cgd@broadcom.com>
554 * mips.igen (X): Delete unused function.
556 2002-06-08 Andrew Cagney <cagney@redhat.com>
558 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
560 2002-06-07 Chris Demetriou <cgd@broadcom.com>
561 Ed Satterthwaite <ehs@broadcom.com>
563 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
564 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
565 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
566 (fp_nmsub): New prototypes.
567 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
568 (NegMultiplySub): New defines.
569 * mips.igen (RSQRT.fmt): Use RSquareRoot().
570 (MADD.D, MADD.S): Replace with...
571 (MADD.fmt): New instruction.
572 (MSUB.D, MSUB.S): Replace with...
573 (MSUB.fmt): New instruction.
574 (NMADD.D, NMADD.S): Replace with...
575 (NMADD.fmt): New instruction.
576 (NMSUB.D, MSUB.S): Replace with...
577 (NMSUB.fmt): New instruction.
579 2002-06-07 Chris Demetriou <cgd@broadcom.com>
580 Ed Satterthwaite <ehs@broadcom.com>
582 * cp1.c: Fix more comment spelling and formatting.
583 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
584 (denorm_mode): New function.
585 (fpu_unary, fpu_binary): Round results after operation, collect
586 status from rounding operations, and update the FCSR.
587 (convert): Collect status from integer conversions and rounding
588 operations, and update the FCSR. Adjust NaN values that result
589 from conversions. Convert to use sim_io_eprintf rather than
590 fprintf, and remove some debugging code.
591 * cp1.h (fenr_FS): New define.
593 2002-06-07 Chris Demetriou <cgd@broadcom.com>
595 * cp1.c (convert): Remove unusable debugging code, and move MIPS
596 rounding mode to sim FP rounding mode flag conversion code into...
597 (rounding_mode): New function.
599 2002-06-07 Chris Demetriou <cgd@broadcom.com>
601 * cp1.c: Clean up formatting of a few comments.
602 (value_fpr): Reformat switch statement.
604 2002-06-06 Chris Demetriou <cgd@broadcom.com>
605 Ed Satterthwaite <ehs@broadcom.com>
608 * sim-main.h: Include cp1.h.
609 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
610 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
611 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
612 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
613 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
614 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
615 * cp1.c: Don't include sim-fpu.h; already included by
616 sim-main.h. Clean up formatting of some comments.
617 (NaN, Equal, Less): Remove.
618 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
619 (fp_cmp): New functions.
620 * mips.igen (do_c_cond_fmt): Remove.
621 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
622 Compare. Add result tracing.
623 (CxC1): Remove, replace with...
624 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
625 (DMxC1): Remove, replace with...
626 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
627 (MxC1): Remove, replace with...
628 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
630 2002-06-04 Chris Demetriou <cgd@broadcom.com>
632 * sim-main.h (FGRIDX): Remove, replace all uses with...
633 (FGR_BASE): New macro.
634 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
635 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
636 (NR_FGR, FGR): Likewise.
637 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
638 * mips.igen: Likewise.
640 2002-06-04 Chris Demetriou <cgd@broadcom.com>
642 * cp1.c: Add an FSF Copyright notice to this file.
644 2002-06-04 Chris Demetriou <cgd@broadcom.com>
645 Ed Satterthwaite <ehs@broadcom.com>
647 * cp1.c (Infinity): Remove.
648 * sim-main.h (Infinity): Likewise.
650 * cp1.c (fp_unary, fp_binary): New functions.
651 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
652 (fp_sqrt): New functions, implemented in terms of the above.
653 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
654 (Recip, SquareRoot): Remove (replaced by functions above).
655 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
656 (fp_recip, fp_sqrt): New prototypes.
657 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
658 (Recip, SquareRoot): Replace prototypes with #defines which
659 invoke the functions above.
661 2002-06-03 Chris Demetriou <cgd@broadcom.com>
663 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
664 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
665 file, remove PARAMS from prototypes.
666 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
667 simulator state arguments.
668 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
669 pass simulator state arguments.
670 * cp1.c (SD): Redefine as CPU_STATE(cpu).
671 (store_fpr, convert): Remove 'sd' argument.
672 (value_fpr): Likewise. Convert to use 'SD' instead.
674 2002-06-03 Chris Demetriou <cgd@broadcom.com>
676 * cp1.c (Min, Max): Remove #if 0'd functions.
677 * sim-main.h (Min, Max): Remove.
679 2002-06-03 Chris Demetriou <cgd@broadcom.com>
681 * cp1.c: fix formatting of switch case and default labels.
682 * interp.c: Likewise.
683 * sim-main.c: Likewise.
685 2002-06-03 Chris Demetriou <cgd@broadcom.com>
687 * cp1.c: Clean up comments which describe FP formats.
688 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
690 2002-06-03 Chris Demetriou <cgd@broadcom.com>
691 Ed Satterthwaite <ehs@broadcom.com>
693 * configure.in (mipsisa64sb1*-*-*): New target for supporting
694 Broadcom SiByte SB-1 processor configurations.
695 * configure: Regenerate.
696 * sb1.igen: New file.
697 * mips.igen: Include sb1.igen.
699 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
700 * mdmx.igen: Add "sb1" model to all appropriate functions and
702 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
703 (ob_func, ob_acc): Reference the above.
704 (qh_acc): Adjust to keep the same size as ob_acc.
705 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
706 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
708 2002-06-03 Chris Demetriou <cgd@broadcom.com>
710 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
712 2002-06-02 Chris Demetriou <cgd@broadcom.com>
713 Ed Satterthwaite <ehs@broadcom.com>
715 * mips.igen (mdmx): New (pseudo-)model.
716 * mdmx.c, mdmx.igen: New files.
717 * Makefile.in (SIM_OBJS): Add mdmx.o.
718 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
720 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
721 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
722 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
723 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
724 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
725 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
726 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
727 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
728 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
729 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
730 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
731 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
732 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
733 (qh_fmtsel): New macros.
734 (_sim_cpu): New member "acc".
735 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
736 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
738 2002-05-01 Chris Demetriou <cgd@broadcom.com>
740 * interp.c: Use 'deprecated' rather than 'depreciated.'
741 * sim-main.h: Likewise.
743 2002-05-01 Chris Demetriou <cgd@broadcom.com>
745 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
746 which wouldn't compile anyway.
747 * sim-main.h (unpredictable_action): New function prototype.
748 (Unpredictable): Define to call igen function unpredictable().
749 (NotWordValue): New macro to call igen function not_word_value().
750 (UndefinedResult): Remove.
751 * interp.c (undefined_result): Remove.
752 (unpredictable_action): New function.
753 * mips.igen (not_word_value, unpredictable): New functions.
754 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
755 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
756 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
757 NotWordValue() to check for unpredictable inputs, then
758 Unpredictable() to handle them.
760 2002-02-24 Chris Demetriou <cgd@broadcom.com>
762 * mips.igen: Fix formatting of calls to Unpredictable().
764 2002-04-20 Andrew Cagney <ac131313@redhat.com>
766 * interp.c (sim_open): Revert previous change.
768 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
770 * interp.c (sim_open): Disable chunk of code that wrote code in
771 vector table entries.
773 2002-03-19 Chris Demetriou <cgd@broadcom.com>
775 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
776 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
779 2002-03-19 Chris Demetriou <cgd@broadcom.com>
781 * cp1.c: Fix many formatting issues.
783 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
785 * cp1.c (fpu_format_name): New function to replace...
786 (DOFMT): This. Delete, and update all callers.
787 (fpu_rounding_mode_name): New function to replace...
788 (RMMODE): This. Delete, and update all callers.
790 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
792 * interp.c: Move FPU support routines from here to...
793 * cp1.c: Here. New file.
794 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
797 2002-03-12 Chris Demetriou <cgd@broadcom.com>
799 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
800 * mips.igen (mips32, mips64): New models, add to all instructions
801 and functions as appropriate.
802 (loadstore_ea, check_u64): New variant for model mips64.
803 (check_fmt_p): New variant for models mipsV and mips64, remove
804 mipsV model marking fro other variant.
807 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
808 for mips32 and mips64.
809 (DCLO, DCLZ): New instructions for mips64.
811 2002-03-07 Chris Demetriou <cgd@broadcom.com>
813 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
814 immediate or code as a hex value with the "%#lx" format.
815 (ANDI): Likewise, and fix printed instruction name.
817 2002-03-05 Chris Demetriou <cgd@broadcom.com>
819 * sim-main.h (UndefinedResult, Unpredictable): New macros
820 which currently do nothing.
822 2002-03-05 Chris Demetriou <cgd@broadcom.com>
824 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
825 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
826 (status_CU3): New definitions.
828 * sim-main.h (ExceptionCause): Add new values for MIPS32
829 and MIPS64: MDMX, MCheck, CacheErr. Update comments
830 for DebugBreakPoint and NMIReset to note their status in
832 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
833 (SignalExceptionCacheErr): New exception macros.
835 2002-03-05 Chris Demetriou <cgd@broadcom.com>
837 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
838 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
840 (SignalExceptionCoProcessorUnusable): Take as argument the
841 unusable coprocessor number.
843 2002-03-05 Chris Demetriou <cgd@broadcom.com>
845 * mips.igen: Fix formatting of all SignalException calls.
847 2002-03-05 Chris Demetriou <cgd@broadcom.com>
849 * sim-main.h (SIGNEXTEND): Remove.
851 2002-03-04 Chris Demetriou <cgd@broadcom.com>
853 * mips.igen: Remove gencode comment from top of file, fix
854 spelling in another comment.
856 2002-03-04 Chris Demetriou <cgd@broadcom.com>
858 * mips.igen (check_fmt, check_fmt_p): New functions to check
859 whether specific floating point formats are usable.
860 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
861 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
862 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
863 Use the new functions.
864 (do_c_cond_fmt): Remove format checks...
865 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
867 2002-03-03 Chris Demetriou <cgd@broadcom.com>
869 * mips.igen: Fix formatting of check_fpu calls.
871 2002-03-03 Chris Demetriou <cgd@broadcom.com>
873 * mips.igen (FLOOR.L.fmt): Store correct destination register.
875 2002-03-03 Chris Demetriou <cgd@broadcom.com>
877 * mips.igen: Remove whitespace at end of lines.
879 2002-03-02 Chris Demetriou <cgd@broadcom.com>
881 * mips.igen (loadstore_ea): New function to do effective
882 address calculations.
883 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
884 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
885 CACHE): Use loadstore_ea to do effective address computations.
887 2002-03-02 Chris Demetriou <cgd@broadcom.com>
889 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
890 * mips.igen (LL, CxC1, MxC1): Likewise.
892 2002-03-02 Chris Demetriou <cgd@broadcom.com>
894 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
895 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
896 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
897 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
898 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
899 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
900 Don't split opcode fields by hand, use the opcode field values
903 2002-03-01 Chris Demetriou <cgd@broadcom.com>
905 * mips.igen (do_divu): Fix spacing.
907 * mips.igen (do_dsllv): Move to be right before DSLLV,
908 to match the rest of the do_<shift> functions.
910 2002-03-01 Chris Demetriou <cgd@broadcom.com>
912 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
913 DSRL32, do_dsrlv): Trace inputs and results.
915 2002-03-01 Chris Demetriou <cgd@broadcom.com>
917 * mips.igen (CACHE): Provide instruction-printing string.
919 * interp.c (signal_exception): Comment tokens after #endif.
921 2002-02-28 Chris Demetriou <cgd@broadcom.com>
923 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
924 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
925 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
926 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
927 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
928 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
929 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
930 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
932 2002-02-28 Chris Demetriou <cgd@broadcom.com>
934 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
935 instruction-printing string.
936 (LWU): Use '64' as the filter flag.
938 2002-02-28 Chris Demetriou <cgd@broadcom.com>
940 * mips.igen (SDXC1): Fix instruction-printing string.
942 2002-02-28 Chris Demetriou <cgd@broadcom.com>
944 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
947 2002-02-27 Chris Demetriou <cgd@broadcom.com>
949 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
952 2002-02-27 Chris Demetriou <cgd@broadcom.com>
954 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
955 add a comma) so that it more closely match the MIPS ISA
956 documentation opcode partitioning.
957 (PREF): Put useful names on opcode fields, and include
958 instruction-printing string.
960 2002-02-27 Chris Demetriou <cgd@broadcom.com>
962 * mips.igen (check_u64): New function which in the future will
963 check whether 64-bit instructions are usable and signal an
964 exception if not. Currently a no-op.
965 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
966 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
967 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
968 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
970 * mips.igen (check_fpu): New function which in the future will
971 check whether FPU instructions are usable and signal an exception
972 if not. Currently a no-op.
973 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
974 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
975 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
976 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
977 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
978 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
979 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
980 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
982 2002-02-27 Chris Demetriou <cgd@broadcom.com>
984 * mips.igen (do_load_left, do_load_right): Move to be immediately
986 (do_store_left, do_store_right): Move to be immediately following
989 2002-02-27 Chris Demetriou <cgd@broadcom.com>
991 * mips.igen (mipsV): New model name. Also, add it to
992 all instructions and functions where it is appropriate.
994 2002-02-18 Chris Demetriou <cgd@broadcom.com>
996 * mips.igen: For all functions and instructions, list model
997 names that support that instruction one per line.
999 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1001 * mips.igen: Add some additional comments about supported
1002 models, and about which instructions go where.
1003 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1004 order as is used in the rest of the file.
1006 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1008 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1009 indicating that ALU32_END or ALU64_END are there to check
1011 (DADD): Likewise, but also remove previous comment about
1014 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1016 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1017 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1018 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1019 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1020 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1021 fields (i.e., add and move commas) so that they more closely
1022 match the MIPS ISA documentation opcode partitioning.
1024 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1026 * mips.igen (ADDI): Print immediate value.
1027 (BREAK): Print code.
1028 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1029 (SLL): Print "nop" specially, and don't run the code
1030 that does the shift for the "nop" case.
1032 2001-11-17 Fred Fish <fnf@redhat.com>
1034 * sim-main.h (float_operation): Move enum declaration outside
1035 of _sim_cpu struct declaration.
1037 2001-04-12 Jim Blandy <jimb@redhat.com>
1039 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1040 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1042 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1043 PENDING_FILL, and you can get the intended effect gracefully by
1044 calling PENDING_SCHED directly.
1046 2001-02-23 Ben Elliston <bje@redhat.com>
1048 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1049 already defined elsewhere.
1051 2001-02-19 Ben Elliston <bje@redhat.com>
1053 * sim-main.h (sim_monitor): Return an int.
1054 * interp.c (sim_monitor): Add return values.
1055 (signal_exception): Handle error conditions from sim_monitor.
1057 2001-02-08 Ben Elliston <bje@redhat.com>
1059 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1060 (store_memory): Likewise, pass cia to sim_core_write*.
1062 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1064 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1065 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1067 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1069 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1070 * Makefile.in: Don't delete *.igen when cleaning directory.
1072 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1074 * m16.igen (break): Call SignalException not sim_engine_halt.
1076 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1078 From Jason Eckhardt:
1079 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1081 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1083 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1085 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1087 * mips.igen (do_dmultx): Fix typo.
1089 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1091 * configure: Regenerated to track ../common/aclocal.m4 changes.
1093 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1095 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1097 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1099 * sim-main.h (GPR_CLEAR): Define macro.
1101 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1103 * interp.c (decode_coproc): Output long using %lx and not %s.
1105 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1107 * interp.c (sim_open): Sort & extend dummy memory regions for
1108 --board=jmr3904 for eCos.
1110 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1112 * configure: Regenerated.
1114 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1116 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1117 calls, conditional on the simulator being in verbose mode.
1119 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1121 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1122 cache don't get ReservedInstruction traps.
1124 1999-11-29 Mark Salter <msalter@cygnus.com>
1126 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1127 to clear status bits in sdisr register. This is how the hardware works.
1129 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1130 being used by cygmon.
1132 1999-11-11 Andrew Haley <aph@cygnus.com>
1134 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1137 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1139 * mips.igen (MULT): Correct previous mis-applied patch.
1141 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1143 * mips.igen (delayslot32): Handle sequence like
1144 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1145 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1146 (MULT): Actually pass the third register...
1148 1999-09-03 Mark Salter <msalter@cygnus.com>
1150 * interp.c (sim_open): Added more memory aliases for additional
1151 hardware being touched by cygmon on jmr3904 board.
1153 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1155 * configure: Regenerated to track ../common/aclocal.m4 changes.
1157 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1159 * interp.c (sim_store_register): Handle case where client - GDB -
1160 specifies that a 4 byte register is 8 bytes in size.
1161 (sim_fetch_register): Ditto.
1163 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1165 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1166 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1167 (idt_monitor_base): Base address for IDT monitor traps.
1168 (pmon_monitor_base): Ditto for PMON.
1169 (lsipmon_monitor_base): Ditto for LSI PMON.
1170 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1171 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1172 (sim_firmware_command): New function.
1173 (mips_option_handler): Call it for OPTION_FIRMWARE.
1174 (sim_open): Allocate memory for idt_monitor region. If "--board"
1175 option was given, add no monitor by default. Add BREAK hooks only if
1176 monitors are also there.
1178 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1180 * interp.c (sim_monitor): Flush output before reading input.
1182 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1184 * tconfig.in (SIM_HANDLES_LMA): Always define.
1186 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1188 From Mark Salter <msalter@cygnus.com>:
1189 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1190 (sim_open): Add setup for BSP board.
1192 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1194 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1195 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1196 them as unimplemented.
1198 1999-05-08 Felix Lee <flee@cygnus.com>
1200 * configure: Regenerated to track ../common/aclocal.m4 changes.
1202 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1204 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1206 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1208 * configure.in: Any mips64vr5*-*-* target should have
1209 -DTARGET_ENABLE_FR=1.
1210 (default_endian): Any mips64vr*el-*-* target should default to
1212 * configure: Re-generate.
1214 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1216 * mips.igen (ldl): Extend from _16_, not 32.
1218 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1220 * interp.c (sim_store_register): Force registers written to by GDB
1221 into an un-interpreted state.
1223 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1225 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1226 CPU, start periodic background I/O polls.
1227 (tx3904sio_poll): New function: periodic I/O poller.
1229 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1231 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1233 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1235 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1238 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1240 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1241 (load_word): Call SIM_CORE_SIGNAL hook on error.
1242 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1243 starting. For exception dispatching, pass PC instead of NULL_CIA.
1244 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1245 * sim-main.h (COP0_BADVADDR): Define.
1246 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1247 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1248 (_sim_cpu): Add exc_* fields to store register value snapshots.
1249 * mips.igen (*): Replace memory-related SignalException* calls
1250 with references to SIM_CORE_SIGNAL hook.
1252 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1254 * sim-main.c (*): Minor warning cleanups.
1256 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1258 * m16.igen (DADDIU5): Correct type-o.
1260 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1262 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1265 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1267 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1269 (interp.o): Add dependency on itable.h
1270 (oengine.c, gencode): Delete remaining references.
1271 (BUILT_SRC_FROM_GEN): Clean up.
1273 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1276 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1277 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1278 tmp-run-hack) : New.
1279 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1280 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1281 Drop the "64" qualifier to get the HACK generator working.
1282 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1283 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1284 qualifier to get the hack generator working.
1285 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1286 (DSLL): Use do_dsll.
1287 (DSLLV): Use do_dsllv.
1288 (DSRA): Use do_dsra.
1289 (DSRL): Use do_dsrl.
1290 (DSRLV): Use do_dsrlv.
1291 (BC1): Move *vr4100 to get the HACK generator working.
1292 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1293 get the HACK generator working.
1294 (MACC) Rename to get the HACK generator working.
1295 (DMACC,MACCS,DMACCS): Add the 64.
1297 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1299 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1300 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1302 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1304 * mips/interp.c (DEBUG): Cleanups.
1306 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1308 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1309 (tx3904sio_tickle): fflush after a stdout character output.
1311 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1313 * interp.c (sim_close): Uninstall modules.
1315 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1317 * sim-main.h, interp.c (sim_monitor): Change to global
1320 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1322 * configure.in (vr4100): Only include vr4100 instructions in
1324 * configure: Re-generate.
1325 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1327 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1329 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1330 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1333 * configure.in (sim_default_gen, sim_use_gen): Replace with
1335 (--enable-sim-igen): Delete config option. Always using IGEN.
1336 * configure: Re-generate.
1338 * Makefile.in (gencode): Kill, kill, kill.
1341 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1343 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1344 bit mips16 igen simulator.
1345 * configure: Re-generate.
1347 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1348 as part of vr4100 ISA.
1349 * vr.igen: Mark all instructions as 64 bit only.
1351 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1353 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1356 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1358 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1359 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1360 * configure: Re-generate.
1362 * m16.igen (BREAK): Define breakpoint instruction.
1363 (JALX32): Mark instruction as mips16 and not r3900.
1364 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1366 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1368 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1370 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1371 insn as a debug breakpoint.
1373 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1375 (PENDING_SCHED): Clean up trace statement.
1376 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1377 (PENDING_FILL): Delay write by only one cycle.
1378 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1380 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1382 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1384 (pending_tick): Move incrementing of index to FOR statement.
1385 (pending_tick): Only update PENDING_OUT after a write has occured.
1387 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1389 * configure: Re-generate.
1391 * interp.c (sim_engine_run OLD): Delete explicit call to
1392 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1394 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1396 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1397 interrupt level number to match changed SignalExceptionInterrupt
1400 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1402 * interp.c: #include "itable.h" if WITH_IGEN.
1403 (get_insn_name): New function.
1404 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1405 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1407 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1409 * configure: Rebuilt to inhale new common/aclocal.m4.
1411 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1413 * dv-tx3904sio.c: Include sim-assert.h.
1415 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1417 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1418 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1419 Reorganize target-specific sim-hardware checks.
1420 * configure: rebuilt.
1421 * interp.c (sim_open): For tx39 target boards, set
1422 OPERATING_ENVIRONMENT, add tx3904sio devices.
1423 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1424 ROM executables. Install dv-sockser into sim-modules list.
1426 * dv-tx3904irc.c: Compiler warning clean-up.
1427 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1428 frequent hw-trace messages.
1430 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1432 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1434 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1436 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1438 * vr.igen: New file.
1439 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1440 * mips.igen: Define vr4100 model. Include vr.igen.
1441 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1443 * mips.igen (check_mf_hilo): Correct check.
1445 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1447 * sim-main.h (interrupt_event): Add prototype.
1449 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1450 register_ptr, register_value.
1451 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1453 * sim-main.h (tracefh): Make extern.
1455 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1457 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1458 Reduce unnecessarily high timer event frequency.
1459 * dv-tx3904cpu.c: Ditto for interrupt event.
1461 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1463 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1465 (interrupt_event): Made non-static.
1467 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1468 interchange of configuration values for external vs. internal
1471 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1473 * mips.igen (BREAK): Moved code to here for
1474 simulator-reserved break instructions.
1475 * gencode.c (build_instruction): Ditto.
1476 * interp.c (signal_exception): Code moved from here. Non-
1477 reserved instructions now use exception vector, rather
1479 * sim-main.h: Moved magic constants to here.
1481 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1483 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1484 register upon non-zero interrupt event level, clear upon zero
1486 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1487 by passing zero event value.
1488 (*_io_{read,write}_buffer): Endianness fixes.
1489 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1490 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1492 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1493 serial I/O and timer module at base address 0xFFFF0000.
1495 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1497 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1500 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1502 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1504 * configure: Update.
1506 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1508 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1509 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1510 * configure.in: Include tx3904tmr in hw_device list.
1511 * configure: Rebuilt.
1512 * interp.c (sim_open): Instantiate three timer instances.
1513 Fix address typo of tx3904irc instance.
1515 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1517 * interp.c (signal_exception): SystemCall exception now uses
1518 the exception vector.
1520 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1522 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1525 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1527 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1529 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1531 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1533 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1534 sim-main.h. Declare a struct hw_descriptor instead of struct
1535 hw_device_descriptor.
1537 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1539 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1540 right bits and then re-align left hand bytes to correct byte
1541 lanes. Fix incorrect computation in do_store_left when loading
1542 bytes from second word.
1544 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1546 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1547 * interp.c (sim_open): Only create a device tree when HW is
1550 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1551 * interp.c (signal_exception): Ditto.
1553 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1555 * gencode.c: Mark BEGEZALL as LIKELY.
1557 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1559 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1560 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1562 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1564 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1565 modules. Recognize TX39 target with "mips*tx39" pattern.
1566 * configure: Rebuilt.
1567 * sim-main.h (*): Added many macros defining bits in
1568 TX39 control registers.
1569 (SignalInterrupt): Send actual PC instead of NULL.
1570 (SignalNMIReset): New exception type.
1571 * interp.c (board): New variable for future use to identify
1572 a particular board being simulated.
1573 (mips_option_handler,mips_options): Added "--board" option.
1574 (interrupt_event): Send actual PC.
1575 (sim_open): Make memory layout conditional on board setting.
1576 (signal_exception): Initial implementation of hardware interrupt
1577 handling. Accept another break instruction variant for simulator
1579 (decode_coproc): Implement RFE instruction for TX39.
1580 (mips.igen): Decode RFE instruction as such.
1581 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1582 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1583 bbegin to implement memory map.
1584 * dv-tx3904cpu.c: New file.
1585 * dv-tx3904irc.c: New file.
1587 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1589 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1591 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1593 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1594 with calls to check_div_hilo.
1596 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1598 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1599 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1600 Add special r3900 version of do_mult_hilo.
1601 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1602 with calls to check_mult_hilo.
1603 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1604 with calls to check_div_hilo.
1606 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1608 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1609 Document a replacement.
1611 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1613 * interp.c (sim_monitor): Make mon_printf work.
1615 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1617 * sim-main.h (INSN_NAME): New arg `cpu'.
1619 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1621 * configure: Regenerated to track ../common/aclocal.m4 changes.
1623 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1625 * configure: Regenerated to track ../common/aclocal.m4 changes.
1628 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1630 * acconfig.h: New file.
1631 * configure.in: Reverted change of Apr 24; use sinclude again.
1633 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1635 * configure: Regenerated to track ../common/aclocal.m4 changes.
1638 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1640 * configure.in: Don't call sinclude.
1642 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1644 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1646 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1648 * mips.igen (ERET): Implement.
1650 * interp.c (decode_coproc): Return sign-extended EPC.
1652 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1654 * interp.c (signal_exception): Do not ignore Trap.
1655 (signal_exception): On TRAP, restart at exception address.
1656 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1657 (signal_exception): Update.
1658 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1659 so that TRAP instructions are caught.
1661 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1663 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1664 contains HI/LO access history.
1665 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1666 (HIACCESS, LOACCESS): Delete, replace with
1667 (HIHISTORY, LOHISTORY): New macros.
1668 (CHECKHILO): Delete all, moved to mips.igen
1670 * gencode.c (build_instruction): Do not generate checks for
1671 correct HI/LO register usage.
1673 * interp.c (old_engine_run): Delete checks for correct HI/LO
1676 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1677 check_mf_cycles): New functions.
1678 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1679 do_divu, domultx, do_mult, do_multu): Use.
1681 * tx.igen ("madd", "maddu"): Use.
1683 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1685 * mips.igen (DSRAV): Use function do_dsrav.
1686 (SRAV): Use new function do_srav.
1688 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1689 (B): Sign extend 11 bit immediate.
1690 (EXT-B*): Shift 16 bit immediate left by 1.
1691 (ADDIU*): Don't sign extend immediate value.
1693 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1695 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1697 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1700 * mips.igen (delayslot32, nullify_next_insn): New functions.
1701 (m16.igen): Always include.
1702 (do_*): Add more tracing.
1704 * m16.igen (delayslot16): Add NIA argument, could be called by a
1705 32 bit MIPS16 instruction.
1707 * interp.c (ifetch16): Move function from here.
1708 * sim-main.c (ifetch16): To here.
1710 * sim-main.c (ifetch16, ifetch32): Update to match current
1711 implementations of LH, LW.
1712 (signal_exception): Don't print out incorrect hex value of illegal
1715 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1717 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1720 * m16.igen: Implement MIPS16 instructions.
1722 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1723 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1724 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1725 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1726 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1727 bodies of corresponding code from 32 bit insn to these. Also used
1728 by MIPS16 versions of functions.
1730 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1731 (IMEM16): Drop NR argument from macro.
1733 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1735 * Makefile.in (SIM_OBJS): Add sim-main.o.
1737 * sim-main.h (address_translation, load_memory, store_memory,
1738 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1740 (pr_addr, pr_uword64): Declare.
1741 (sim-main.c): Include when H_REVEALS_MODULE_P.
1743 * interp.c (address_translation, load_memory, store_memory,
1744 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1746 * sim-main.c: To here. Fix compilation problems.
1748 * configure.in: Enable inlining.
1749 * configure: Re-config.
1751 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1753 * configure: Regenerated to track ../common/aclocal.m4 changes.
1755 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1757 * mips.igen: Include tx.igen.
1758 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1759 * tx.igen: New file, contains MADD and MADDU.
1761 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1762 the hardwired constant `7'.
1763 (store_memory): Ditto.
1764 (LOADDRMASK): Move definition to sim-main.h.
1766 mips.igen (MTC0): Enable for r3900.
1769 mips.igen (do_load_byte): Delete.
1770 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1771 do_store_right): New functions.
1772 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1774 configure.in: Let the tx39 use igen again.
1777 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1779 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1780 not an address sized quantity. Return zero for cache sizes.
1782 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1784 * mips.igen (r3900): r3900 does not support 64 bit integer
1787 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1789 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1791 * configure : Rebuild.
1793 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1795 * configure: Regenerated to track ../common/aclocal.m4 changes.
1797 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1799 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1801 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1803 * configure: Regenerated to track ../common/aclocal.m4 changes.
1804 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1806 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1808 * configure: Regenerated to track ../common/aclocal.m4 changes.
1810 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1812 * interp.c (Max, Min): Comment out functions. Not yet used.
1814 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1816 * configure: Regenerated to track ../common/aclocal.m4 changes.
1818 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1820 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1821 configurable settings for stand-alone simulator.
1823 * configure.in: Added X11 search, just in case.
1825 * configure: Regenerated.
1827 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1829 * interp.c (sim_write, sim_read, load_memory, store_memory):
1830 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1832 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1834 * sim-main.h (GETFCC): Return an unsigned value.
1836 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1838 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1839 (DADD): Result destination is RD not RT.
1841 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1843 * sim-main.h (HIACCESS, LOACCESS): Always define.
1845 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1847 * interp.c (sim_info): Delete.
1849 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1851 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1852 (mips_option_handler): New argument `cpu'.
1853 (sim_open): Update call to sim_add_option_table.
1855 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1857 * mips.igen (CxC1): Add tracing.
1859 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1861 * sim-main.h (Max, Min): Declare.
1863 * interp.c (Max, Min): New functions.
1865 * mips.igen (BC1): Add tracing.
1867 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1869 * interp.c Added memory map for stack in vr4100
1871 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1873 * interp.c (load_memory): Add missing "break"'s.
1875 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1877 * interp.c (sim_store_register, sim_fetch_register): Pass in
1878 length parameter. Return -1.
1880 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1882 * interp.c: Added hardware init hook, fixed warnings.
1884 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1886 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1888 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1890 * interp.c (ifetch16): New function.
1892 * sim-main.h (IMEM32): Rename IMEM.
1893 (IMEM16_IMMED): Define.
1895 (DELAY_SLOT): Update.
1897 * m16run.c (sim_engine_run): New file.
1899 * m16.igen: All instructions except LB.
1900 (LB): Call do_load_byte.
1901 * mips.igen (do_load_byte): New function.
1902 (LB): Call do_load_byte.
1904 * mips.igen: Move spec for insn bit size and high bit from here.
1905 * Makefile.in (tmp-igen, tmp-m16): To here.
1907 * m16.dc: New file, decode mips16 instructions.
1909 * Makefile.in (SIM_NO_ALL): Define.
1910 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1912 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1914 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1915 point unit to 32 bit registers.
1916 * configure: Re-generate.
1918 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1920 * configure.in (sim_use_gen): Make IGEN the default simulator
1921 generator for generic 32 and 64 bit mips targets.
1922 * configure: Re-generate.
1924 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1926 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1929 * interp.c (sim_fetch_register, sim_store_register): Read/write
1930 FGR from correct location.
1931 (sim_open): Set size of FGR's according to
1932 WITH_TARGET_FLOATING_POINT_BITSIZE.
1934 * sim-main.h (FGR): Store floating point registers in a separate
1937 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1939 * configure: Regenerated to track ../common/aclocal.m4 changes.
1941 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1943 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1945 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1947 * interp.c (pending_tick): New function. Deliver pending writes.
1949 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1950 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1951 it can handle mixed sized quantites and single bits.
1953 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1955 * interp.c (oengine.h): Do not include when building with IGEN.
1956 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1957 (sim_info): Ditto for PROCESSOR_64BIT.
1958 (sim_monitor): Replace ut_reg with unsigned_word.
1959 (*): Ditto for t_reg.
1960 (LOADDRMASK): Define.
1961 (sim_open): Remove defunct check that host FP is IEEE compliant,
1962 using software to emulate floating point.
1963 (value_fpr, ...): Always compile, was conditional on HASFPU.
1965 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1967 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1970 * interp.c (SD, CPU): Define.
1971 (mips_option_handler): Set flags in each CPU.
1972 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1973 (sim_close): Do not clear STATE, deleted anyway.
1974 (sim_write, sim_read): Assume CPU zero's vm should be used for
1976 (sim_create_inferior): Set the PC for all processors.
1977 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1979 (mips16_entry): Pass correct nr of args to store_word, load_word.
1980 (ColdReset): Cold reset all cpu's.
1981 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1982 (sim_monitor, load_memory, store_memory, signal_exception): Use
1983 `CPU' instead of STATE_CPU.
1986 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1989 * sim-main.h (signal_exception): Add sim_cpu arg.
1990 (SignalException*): Pass both SD and CPU to signal_exception.
1991 * interp.c (signal_exception): Update.
1993 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1995 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1996 address_translation): Ditto
1997 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1999 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2001 * configure: Regenerated to track ../common/aclocal.m4 changes.
2003 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2005 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2007 * mips.igen (model): Map processor names onto BFD name.
2009 * sim-main.h (CPU_CIA): Delete.
2010 (SET_CIA, GET_CIA): Define
2012 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2014 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2017 * configure.in (default_endian): Configure a big-endian simulator
2019 * configure: Re-generate.
2021 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2023 * configure: Regenerated to track ../common/aclocal.m4 changes.
2025 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2027 * interp.c (sim_monitor): Handle Densan monitor outbyte
2028 and inbyte functions.
2030 1997-12-29 Felix Lee <flee@cygnus.com>
2032 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2034 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2036 * Makefile.in (tmp-igen): Arrange for $zero to always be
2037 reset to zero after every instruction.
2039 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2041 * configure: Regenerated to track ../common/aclocal.m4 changes.
2044 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2046 * mips.igen (MSUB): Fix to work like MADD.
2047 * gencode.c (MSUB): Similarly.
2049 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2051 * configure: Regenerated to track ../common/aclocal.m4 changes.
2053 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2055 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2057 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2059 * sim-main.h (sim-fpu.h): Include.
2061 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2062 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2063 using host independant sim_fpu module.
2065 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2067 * interp.c (signal_exception): Report internal errors with SIGABRT
2070 * sim-main.h (C0_CONFIG): New register.
2071 (signal.h): No longer include.
2073 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2075 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2077 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2079 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2081 * mips.igen: Tag vr5000 instructions.
2082 (ANDI): Was missing mipsIV model, fix assembler syntax.
2083 (do_c_cond_fmt): New function.
2084 (C.cond.fmt): Handle mips I-III which do not support CC field
2086 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2087 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2089 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2090 vr5000 which saves LO in a GPR separatly.
2092 * configure.in (enable-sim-igen): For vr5000, select vr5000
2093 specific instructions.
2094 * configure: Re-generate.
2096 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2098 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2100 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2101 fmt_uninterpreted_64 bit cases to switch. Convert to
2104 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2106 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2107 as specified in IV3.2 spec.
2108 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2110 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2112 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2113 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2114 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2115 PENDING_FILL versions of instructions. Simplify.
2117 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2119 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2121 (MTHI, MFHI): Disable code checking HI-LO.
2123 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2125 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2127 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2129 * gencode.c (build_mips16_operands): Replace IPC with cia.
2131 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2132 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2134 (UndefinedResult): Replace function with macro/function
2136 (sim_engine_run): Don't save PC in IPC.
2138 * sim-main.h (IPC): Delete.
2141 * interp.c (signal_exception, store_word, load_word,
2142 address_translation, load_memory, store_memory, cache_op,
2143 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2144 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2145 current instruction address - cia - argument.
2146 (sim_read, sim_write): Call address_translation directly.
2147 (sim_engine_run): Rename variable vaddr to cia.
2148 (signal_exception): Pass cia to sim_monitor
2150 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2151 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2152 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2154 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2155 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2158 * interp.c (signal_exception): Pass restart address to
2161 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2162 idecode.o): Add dependency.
2164 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2166 (DELAY_SLOT): Update NIA not PC with branch address.
2167 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2169 * mips.igen: Use CIA not PC in branch calculations.
2170 (illegal): Call SignalException.
2171 (BEQ, ADDIU): Fix assembler.
2173 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2175 * m16.igen (JALX): Was missing.
2177 * configure.in (enable-sim-igen): New configuration option.
2178 * configure: Re-generate.
2180 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2182 * interp.c (load_memory, store_memory): Delete parameter RAW.
2183 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2184 bypassing {load,store}_memory.
2186 * sim-main.h (ByteSwapMem): Delete definition.
2188 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2190 * interp.c (sim_do_command, sim_commands): Delete mips specific
2191 commands. Handled by module sim-options.
2193 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2194 (WITH_MODULO_MEMORY): Define.
2196 * interp.c (sim_info): Delete code printing memory size.
2198 * interp.c (mips_size): Nee sim_size, delete function.
2200 (monitor, monitor_base, monitor_size): Delete global variables.
2201 (sim_open, sim_close): Delete code creating monitor and other
2202 memory regions. Use sim-memopts module, via sim_do_commandf, to
2203 manage memory regions.
2204 (load_memory, store_memory): Use sim-core for memory model.
2206 * interp.c (address_translation): Delete all memory map code
2207 except line forcing 32 bit addresses.
2209 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2211 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2214 * interp.c (logfh, logfile): Delete globals.
2215 (sim_open, sim_close): Delete code opening & closing log file.
2216 (mips_option_handler): Delete -l and -n options.
2217 (OPTION mips_options): Ditto.
2219 * interp.c (OPTION mips_options): Rename option trace to dinero.
2220 (mips_option_handler): Update.
2222 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2224 * interp.c (fetch_str): New function.
2225 (sim_monitor): Rewrite using sim_read & sim_write.
2226 (sim_open): Check magic number.
2227 (sim_open): Write monitor vectors into memory using sim_write.
2228 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2229 (sim_read, sim_write): Simplify - transfer data one byte at a
2231 (load_memory, store_memory): Clarify meaning of parameter RAW.
2233 * sim-main.h (isHOST): Defete definition.
2234 (isTARGET): Mark as depreciated.
2235 (address_translation): Delete parameter HOST.
2237 * interp.c (address_translation): Delete parameter HOST.
2239 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2243 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2244 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2246 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2248 * mips.igen: Add model filter field to records.
2250 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2252 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2254 interp.c (sim_engine_run): Do not compile function sim_engine_run
2255 when WITH_IGEN == 1.
2257 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2258 target architecture.
2260 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2261 igen. Replace with configuration variables sim_igen_flags /
2264 * m16.igen: New file. Copy mips16 insns here.
2265 * mips.igen: From here.
2267 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2269 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2271 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2273 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2275 * gencode.c (build_instruction): Follow sim_write's lead in using
2276 BigEndianMem instead of !ByteSwapMem.
2278 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2280 * configure.in (sim_gen): Dependent on target, select type of
2281 generator. Always select old style generator.
2283 configure: Re-generate.
2285 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2287 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2288 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2289 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2290 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2291 SIM_@sim_gen@_*, set by autoconf.
2293 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2295 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2297 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2298 CURRENT_FLOATING_POINT instead.
2300 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2301 (address_translation): Raise exception InstructionFetch when
2302 translation fails and isINSTRUCTION.
2304 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2305 sim_engine_run): Change type of of vaddr and paddr to
2307 (address_translation, prefetch, load_memory, store_memory,
2308 cache_op): Change type of vAddr and pAddr to address_word.
2310 * gencode.c (build_instruction): Change type of vaddr and paddr to
2313 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2315 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2316 macro to obtain result of ALU op.
2318 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2320 * interp.c (sim_info): Call profile_print.
2322 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2324 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2326 * sim-main.h (WITH_PROFILE): Do not define, defined in
2327 common/sim-config.h. Use sim-profile module.
2328 (simPROFILE): Delete defintion.
2330 * interp.c (PROFILE): Delete definition.
2331 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2332 (sim_close): Delete code writing profile histogram.
2333 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2335 (sim_engine_run): Delete code profiling the PC.
2337 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2339 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2341 * interp.c (sim_monitor): Make register pointers of type
2344 * sim-main.h: Make registers of type unsigned_word not
2347 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2349 * interp.c (sync_operation): Rename from SyncOperation, make
2350 global, add SD argument.
2351 (prefetch): Rename from Prefetch, make global, add SD argument.
2352 (decode_coproc): Make global.
2354 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2356 * gencode.c (build_instruction): Generate DecodeCoproc not
2357 decode_coproc calls.
2359 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2360 (SizeFGR): Move to sim-main.h
2361 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2362 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2363 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2365 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2366 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2367 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2368 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2369 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2370 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2372 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2374 (sim-alu.h): Include.
2375 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2376 (sim_cia): Typedef to instruction_address.
2378 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2380 * Makefile.in (interp.o): Rename generated file engine.c to
2385 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2387 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2389 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2391 * gencode.c (build_instruction): For "FPSQRT", output correct
2392 number of arguments to Recip.
2394 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2396 * Makefile.in (interp.o): Depends on sim-main.h
2398 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2400 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2401 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2402 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2403 STATE, DSSTATE): Define
2404 (GPR, FGRIDX, ..): Define.
2406 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2407 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2408 (GPR, FGRIDX, ...): Delete macros.
2410 * interp.c: Update names to match defines from sim-main.h
2412 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2414 * interp.c (sim_monitor): Add SD argument.
2415 (sim_warning): Delete. Replace calls with calls to
2417 (sim_error): Delete. Replace calls with sim_io_error.
2418 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2419 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2420 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2422 (mips_size): Rename from sim_size. Add SD argument.
2424 * interp.c (simulator): Delete global variable.
2425 (callback): Delete global variable.
2426 (mips_option_handler, sim_open, sim_write, sim_read,
2427 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2428 sim_size,sim_monitor): Use sim_io_* not callback->*.
2429 (sim_open): ZALLOC simulator struct.
2430 (PROFILE): Do not define.
2432 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2434 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2435 support.h with corresponding code.
2437 * sim-main.h (word64, uword64), support.h: Move definition to
2439 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2442 * Makefile.in: Update dependencies
2443 * interp.c: Do not include.
2445 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2447 * interp.c (address_translation, load_memory, store_memory,
2448 cache_op): Rename to from AddressTranslation et.al., make global,
2451 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2454 * interp.c (SignalException): Rename to signal_exception, make
2457 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2459 * sim-main.h (SignalException, SignalExceptionInterrupt,
2460 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2461 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2462 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2465 * interp.c, support.h: Use.
2467 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2469 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2470 to value_fpr / store_fpr. Add SD argument.
2471 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2472 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2474 * sim-main.h (ValueFPR, StoreFPR): Define.
2476 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2478 * interp.c (sim_engine_run): Check consistency between configure
2479 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2482 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2483 (mips_fpu): Configure WITH_FLOATING_POINT.
2484 (mips_endian): Configure WITH_TARGET_ENDIAN.
2485 * configure: Update.
2487 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2489 * configure: Regenerated to track ../common/aclocal.m4 changes.
2491 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2493 * configure: Regenerated.
2495 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2497 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2499 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2501 * gencode.c (print_igen_insn_models): Assume certain architectures
2502 include all mips* instructions.
2503 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2506 * Makefile.in (tmp.igen): Add target. Generate igen input from
2509 * gencode.c (FEATURE_IGEN): Define.
2510 (main): Add --igen option. Generate output in igen format.
2511 (process_instructions): Format output according to igen option.
2512 (print_igen_insn_format): New function.
2513 (print_igen_insn_models): New function.
2514 (process_instructions): Only issue warnings and ignore
2515 instructions when no FEATURE_IGEN.
2517 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2519 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2522 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2524 * configure: Regenerated to track ../common/aclocal.m4 changes.
2526 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2528 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2529 SIM_RESERVED_BITS): Delete, moved to common.
2530 (SIM_EXTRA_CFLAGS): Update.
2532 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2534 * configure.in: Configure non-strict memory alignment.
2535 * configure: Regenerated to track ../common/aclocal.m4 changes.
2537 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2539 * configure: Regenerated to track ../common/aclocal.m4 changes.
2541 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2543 * gencode.c (SDBBP,DERET): Added (3900) insns.
2544 (RFE): Turn on for 3900.
2545 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2546 (dsstate): Made global.
2547 (SUBTARGET_R3900): Added.
2548 (CANCELDELAYSLOT): New.
2549 (SignalException): Ignore SystemCall rather than ignore and
2550 terminate. Add DebugBreakPoint handling.
2551 (decode_coproc): New insns RFE, DERET; and new registers Debug
2552 and DEPC protected by SUBTARGET_R3900.
2553 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2555 * Makefile.in,configure.in: Add mips subtarget option.
2556 * configure: Update.
2558 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2560 * gencode.c: Add r3900 (tx39).
2563 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2565 * gencode.c (build_instruction): Don't need to subtract 4 for
2568 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2570 * interp.c: Correct some HASFPU problems.
2572 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2574 * configure: Regenerated to track ../common/aclocal.m4 changes.
2576 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2578 * interp.c (mips_options): Fix samples option short form, should
2581 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2583 * interp.c (sim_info): Enable info code. Was just returning.
2585 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2587 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2590 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2592 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2594 (build_instruction): Ditto for LL.
2596 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2598 * configure: Regenerated to track ../common/aclocal.m4 changes.
2600 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2602 * configure: Regenerated to track ../common/aclocal.m4 changes.
2605 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2607 * interp.c (sim_open): Add call to sim_analyze_program, update
2610 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2612 * interp.c (sim_kill): Delete.
2613 (sim_create_inferior): Add ABFD argument. Set PC from same.
2614 (sim_load): Move code initializing trap handlers from here.
2615 (sim_open): To here.
2616 (sim_load): Delete, use sim-hload.c.
2618 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2620 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2622 * configure: Regenerated to track ../common/aclocal.m4 changes.
2625 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2627 * interp.c (sim_open): Add ABFD argument.
2628 (sim_load): Move call to sim_config from here.
2629 (sim_open): To here. Check return status.
2631 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2633 * gencode.c (build_instruction): Two arg MADD should
2634 not assign result to $0.
2636 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2638 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2639 * sim/mips/configure.in: Regenerate.
2641 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2643 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2644 signed8, unsigned8 et.al. types.
2646 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2647 hosts when selecting subreg.
2649 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2651 * interp.c (sim_engine_run): Reset the ZERO register to zero
2652 regardless of FEATURE_WARN_ZERO.
2653 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2655 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2657 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2658 (SignalException): For BreakPoints ignore any mode bits and just
2660 (SignalException): Always set the CAUSE register.
2662 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2664 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2665 exception has been taken.
2667 * interp.c: Implement the ERET and mt/f sr instructions.
2669 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2671 * interp.c (SignalException): Don't bother restarting an
2674 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2676 * interp.c (SignalException): Really take an interrupt.
2677 (interrupt_event): Only deliver interrupts when enabled.
2679 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2681 * interp.c (sim_info): Only print info when verbose.
2682 (sim_info) Use sim_io_printf for output.
2684 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2686 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2689 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2691 * interp.c (sim_do_command): Check for common commands if a
2692 simulator specific command fails.
2694 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2696 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2697 and simBE when DEBUG is defined.
2699 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2701 * interp.c (interrupt_event): New function. Pass exception event
2702 onto exception handler.
2704 * configure.in: Check for stdlib.h.
2705 * configure: Regenerate.
2707 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2708 variable declaration.
2709 (build_instruction): Initialize memval1.
2710 (build_instruction): Add UNUSED attribute to byte, bigend,
2712 (build_operands): Ditto.
2714 * interp.c: Fix GCC warnings.
2715 (sim_get_quit_code): Delete.
2717 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2718 * Makefile.in: Ditto.
2719 * configure: Re-generate.
2721 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2723 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2725 * interp.c (mips_option_handler): New function parse argumes using
2727 (myname): Replace with STATE_MY_NAME.
2728 (sim_open): Delete check for host endianness - performed by
2730 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2731 (sim_open): Move much of the initialization from here.
2732 (sim_load): To here. After the image has been loaded and
2734 (sim_open): Move ColdReset from here.
2735 (sim_create_inferior): To here.
2736 (sim_open): Make FP check less dependant on host endianness.
2738 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2740 * interp.c (sim_set_callbacks): Delete.
2742 * interp.c (membank, membank_base, membank_size): Replace with
2743 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2744 (sim_open): Remove call to callback->init. gdb/run do this.
2748 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2750 * interp.c (big_endian_p): Delete, replaced by
2751 current_target_byte_order.
2753 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2755 * interp.c (host_read_long, host_read_word, host_swap_word,
2756 host_swap_long): Delete. Using common sim-endian.
2757 (sim_fetch_register, sim_store_register): Use H2T.
2758 (pipeline_ticks): Delete. Handled by sim-events.
2760 (sim_engine_run): Update.
2762 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2764 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2766 (SignalException): To here. Signal using sim_engine_halt.
2767 (sim_stop_reason): Delete, moved to common.
2769 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2771 * interp.c (sim_open): Add callback argument.
2772 (sim_set_callbacks): Delete SIM_DESC argument.
2775 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2777 * Makefile.in (SIM_OBJS): Add common modules.
2779 * interp.c (sim_set_callbacks): Also set SD callback.
2780 (set_endianness, xfer_*, swap_*): Delete.
2781 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2782 Change to functions using sim-endian macros.
2783 (control_c, sim_stop): Delete, use common version.
2784 (simulate): Convert into.
2785 (sim_engine_run): This function.
2786 (sim_resume): Delete.
2788 * interp.c (simulation): New variable - the simulator object.
2789 (sim_kind): Delete global - merged into simulation.
2790 (sim_load): Cleanup. Move PC assignment from here.
2791 (sim_create_inferior): To here.
2793 * sim-main.h: New file.
2794 * interp.c (sim-main.h): Include.
2796 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2798 * configure: Regenerated to track ../common/aclocal.m4 changes.
2800 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2802 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2804 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2806 * gencode.c (build_instruction): DIV instructions: check
2807 for division by zero and integer overflow before using
2808 host's division operation.
2810 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2812 * Makefile.in (SIM_OBJS): Add sim-load.o.
2813 * interp.c: #include bfd.h.
2814 (target_byte_order): Delete.
2815 (sim_kind, myname, big_endian_p): New static locals.
2816 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2817 after argument parsing. Recognize -E arg, set endianness accordingly.
2818 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2819 load file into simulator. Set PC from bfd.
2820 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2821 (set_endianness): Use big_endian_p instead of target_byte_order.
2823 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2825 * interp.c (sim_size): Delete prototype - conflicts with
2826 definition in remote-sim.h. Correct definition.
2828 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2830 * configure: Regenerated to track ../common/aclocal.m4 changes.
2833 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2835 * interp.c (sim_open): New arg `kind'.
2837 * configure: Regenerated to track ../common/aclocal.m4 changes.
2839 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2841 * configure: Regenerated to track ../common/aclocal.m4 changes.
2843 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2845 * interp.c (sim_open): Set optind to 0 before calling getopt.
2847 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2849 * configure: Regenerated to track ../common/aclocal.m4 changes.
2851 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2853 * interp.c : Replace uses of pr_addr with pr_uword64
2854 where the bit length is always 64 independent of SIM_ADDR.
2855 (pr_uword64) : added.
2857 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2859 * configure: Re-generate.
2861 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2863 * configure: Regenerate to track ../common/aclocal.m4 changes.
2865 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2867 * interp.c (sim_open): New SIM_DESC result. Argument is now
2869 (other sim_*): New SIM_DESC argument.
2871 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2873 * interp.c: Fix printing of addresses for non-64-bit targets.
2874 (pr_addr): Add function to print address based on size.
2876 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2878 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2880 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2882 * gencode.c (build_mips16_operands): Correct computation of base
2883 address for extended PC relative instruction.
2885 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2887 * interp.c (mips16_entry): Add support for floating point cases.
2888 (SignalException): Pass floating point cases to mips16_entry.
2889 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2891 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2893 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2894 and then set the state to fmt_uninterpreted.
2895 (COP_SW): Temporarily set the state to fmt_word while calling
2898 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2900 * gencode.c (build_instruction): The high order may be set in the
2901 comparison flags at any ISA level, not just ISA 4.
2903 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2905 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2906 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2907 * configure.in: sinclude ../common/aclocal.m4.
2908 * configure: Regenerated.
2910 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2912 * configure: Rebuild after change to aclocal.m4.
2914 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2916 * configure configure.in Makefile.in: Update to new configure
2917 scheme which is more compatible with WinGDB builds.
2918 * configure.in: Improve comment on how to run autoconf.
2919 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2920 * Makefile.in: Use autoconf substitution to install common
2923 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2925 * gencode.c (build_instruction): Use BigEndianCPU instead of
2928 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2930 * interp.c (sim_monitor): Make output to stdout visible in
2931 wingdb's I/O log window.
2933 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2935 * support.h: Undo previous change to SIGTRAP
2938 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2940 * interp.c (store_word, load_word): New static functions.
2941 (mips16_entry): New static function.
2942 (SignalException): Look for mips16 entry and exit instructions.
2943 (simulate): Use the correct index when setting fpr_state after
2944 doing a pending move.
2946 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2948 * interp.c: Fix byte-swapping code throughout to work on
2949 both little- and big-endian hosts.
2951 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2953 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2954 with gdb/config/i386/xm-windows.h.
2956 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2958 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2959 that messes up arithmetic shifts.
2961 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2963 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2964 SIGTRAP and SIGQUIT for _WIN32.
2966 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2968 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2969 force a 64 bit multiplication.
2970 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2971 destination register is 0, since that is the default mips16 nop
2974 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2976 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2977 (build_endian_shift): Don't check proc64.
2978 (build_instruction): Always set memval to uword64. Cast op2 to
2979 uword64 when shifting it left in memory instructions. Always use
2980 the same code for stores--don't special case proc64.
2982 * gencode.c (build_mips16_operands): Fix base PC value for PC
2984 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2986 * interp.c (simJALDELAYSLOT): Define.
2987 (JALDELAYSLOT): Define.
2988 (INDELAYSLOT, INJALDELAYSLOT): Define.
2989 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2991 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2993 * interp.c (sim_open): add flush_cache as a PMON routine
2994 (sim_monitor): handle flush_cache by ignoring it
2996 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2998 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3000 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3001 (BigEndianMem): Rename to ByteSwapMem and change sense.
3002 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3003 BigEndianMem references to !ByteSwapMem.
3004 (set_endianness): New function, with prototype.
3005 (sim_open): Call set_endianness.
3006 (sim_info): Use simBE instead of BigEndianMem.
3007 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3008 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3009 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3010 ifdefs, keeping the prototype declaration.
3011 (swap_word): Rewrite correctly.
3012 (ColdReset): Delete references to CONFIG. Delete endianness related
3013 code; moved to set_endianness.
3015 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3017 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3018 * interp.c (CHECKHILO): Define away.
3019 (simSIGINT): New macro.
3020 (membank_size): Increase from 1MB to 2MB.
3021 (control_c): New function.
3022 (sim_resume): Rename parameter signal to signal_number. Add local
3023 variable prev. Call signal before and after simulate.
3024 (sim_stop_reason): Add simSIGINT support.
3025 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3027 (sim_warning): Delete call to SignalException. Do call printf_filtered
3029 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3030 a call to sim_warning.
3032 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3034 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3035 16 bit instructions.
3037 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3039 Add support for mips16 (16 bit MIPS implementation):
3040 * gencode.c (inst_type): Add mips16 instruction encoding types.
3041 (GETDATASIZEINSN): Define.
3042 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3043 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3045 (MIPS16_DECODE): New table, for mips16 instructions.
3046 (bitmap_val): New static function.
3047 (struct mips16_op): Define.
3048 (mips16_op_table): New table, for mips16 operands.
3049 (build_mips16_operands): New static function.
3050 (process_instructions): If PC is odd, decode a mips16
3051 instruction. Break out instruction handling into new
3052 build_instruction function.
3053 (build_instruction): New static function, broken out of
3054 process_instructions. Check modifiers rather than flags for SHIFT
3055 bit count and m[ft]{hi,lo} direction.
3056 (usage): Pass program name to fprintf.
3057 (main): Remove unused variable this_option_optind. Change
3058 ``*loptarg++'' to ``loptarg++''.
3059 (my_strtoul): Parenthesize && within ||.
3060 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3061 (simulate): If PC is odd, fetch a 16 bit instruction, and
3062 increment PC by 2 rather than 4.
3063 * configure.in: Add case for mips16*-*-*.
3064 * configure: Rebuild.
3066 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3068 * interp.c: Allow -t to enable tracing in standalone simulator.
3069 Fix garbage output in trace file and error messages.
3071 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3073 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3074 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3075 * configure.in: Simplify using macros in ../common/aclocal.m4.
3076 * configure: Regenerated.
3077 * tconfig.in: New file.
3079 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3081 * interp.c: Fix bugs in 64-bit port.
3082 Use ansi function declarations for msvc compiler.
3083 Initialize and test file pointer in trace code.
3084 Prevent duplicate definition of LAST_EMED_REGNUM.
3086 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3088 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3090 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3092 * interp.c (SignalException): Check for explicit terminating
3094 * gencode.c: Pass instruction value through SignalException()
3095 calls for Trap, Breakpoint and Syscall.
3097 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3099 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3100 only used on those hosts that provide it.
3101 * configure.in: Add sqrt() to list of functions to be checked for.
3102 * config.in: Re-generated.
3103 * configure: Re-generated.
3105 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3107 * gencode.c (process_instructions): Call build_endian_shift when
3108 expanding STORE RIGHT, to fix swr.
3109 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3110 clear the high bits.
3111 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3112 Fix float to int conversions to produce signed values.
3114 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3116 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3117 (process_instructions): Correct handling of nor instruction.
3118 Correct shift count for 32 bit shift instructions. Correct sign
3119 extension for arithmetic shifts to not shift the number of bits in
3120 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3121 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3123 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3124 It's OK to have a mult follow a mult. What's not OK is to have a
3125 mult follow an mfhi.
3126 (Convert): Comment out incorrect rounding code.
3128 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3130 * interp.c (sim_monitor): Improved monitor printf
3131 simulation. Tidied up simulator warnings, and added "--log" option
3132 for directing warning message output.
3133 * gencode.c: Use sim_warning() rather than WARNING macro.
3135 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3137 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3138 getopt1.o, rather than on gencode.c. Link objects together.
3139 Don't link against -liberty.
3140 (gencode.o, getopt.o, getopt1.o): New targets.
3141 * gencode.c: Include <ctype.h> and "ansidecl.h".
3142 (AND): Undefine after including "ansidecl.h".
3143 (ULONG_MAX): Define if not defined.
3144 (OP_*): Don't define macros; now defined in opcode/mips.h.
3145 (main): Call my_strtoul rather than strtoul.
3146 (my_strtoul): New static function.
3148 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3150 * gencode.c (process_instructions): Generate word64 and uword64
3151 instead of `long long' and `unsigned long long' data types.
3152 * interp.c: #include sysdep.h to get signals, and define default
3154 * (Convert): Work around for Visual-C++ compiler bug with type
3156 * support.h: Make things compile under Visual-C++ by using
3157 __int64 instead of `long long'. Change many refs to long long
3158 into word64/uword64 typedefs.
3160 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3162 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3163 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3165 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3166 (AC_PROG_INSTALL): Added.
3167 (AC_PROG_CC): Moved to before configure.host call.
3168 * configure: Rebuilt.
3170 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3172 * configure.in: Define @SIMCONF@ depending on mips target.
3173 * configure: Rebuild.
3174 * Makefile.in (run): Add @SIMCONF@ to control simulator
3176 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3177 * interp.c: Remove some debugging, provide more detailed error
3178 messages, update memory accesses to use LOADDRMASK.
3180 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3182 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3183 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3185 * configure: Rebuild.
3186 * config.in: New file, generated by autoheader.
3187 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3188 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3189 HAVE_ANINT and HAVE_AINT, as appropriate.
3190 * Makefile.in (run): Use @LIBS@ rather than -lm.
3191 (interp.o): Depend upon config.h.
3192 (Makefile): Just rebuild Makefile.
3193 (clean): Remove stamp-h.
3194 (mostlyclean): Make the same as clean, not as distclean.
3195 (config.h, stamp-h): New targets.
3197 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3199 * interp.c (ColdReset): Fix boolean test. Make all simulator
3202 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3204 * interp.c (xfer_direct_word, xfer_direct_long,
3205 swap_direct_word, swap_direct_long, xfer_big_word,
3206 xfer_big_long, xfer_little_word, xfer_little_long,
3207 swap_word,swap_long): Added.
3208 * interp.c (ColdReset): Provide function indirection to
3209 host<->simulated_target transfer routines.
3210 * interp.c (sim_store_register, sim_fetch_register): Updated to
3211 make use of indirected transfer routines.
3213 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3215 * gencode.c (process_instructions): Ensure FP ABS instruction
3217 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3218 system call support.
3220 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3222 * interp.c (sim_do_command): Complain if callback structure not
3225 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3227 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3228 support for Sun hosts.
3229 * Makefile.in (gencode): Ensure the host compiler and libraries
3230 used for cross-hosted build.
3232 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3234 * interp.c, gencode.c: Some more (TODO) tidying.
3236 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3238 * gencode.c, interp.c: Replaced explicit long long references with
3239 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3240 * support.h (SET64LO, SET64HI): Macros added.
3242 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3244 * configure: Regenerate with autoconf 2.7.
3246 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3248 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3249 * support.h: Remove superfluous "1" from #if.
3250 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3252 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3254 * interp.c (StoreFPR): Control UndefinedResult() call on
3255 WARN_RESULT manifest.
3257 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3259 * gencode.c: Tidied instruction decoding, and added FP instruction
3262 * interp.c: Added dineroIII, and BSD profiling support. Also
3263 run-time FP handling.
3265 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3267 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3268 gencode.c, interp.c, support.h: created.